KR20070071001A - Image sensor and method for manufacturing the same - Google Patents

Abstract

An image sensor is provided to prevent crosstalk of an image sensor by preventing the charges generated from the periphery of a pixel from being introduced into a photodiode. A dummy gate electrode(24a) is formed on a substrate to surround a photodiode(29) so that the charges generated in the periphery of a pixel are not introduced into the photodiode. The dummy gate electrode can be connected to a power voltage terminal. The photodiode can be a quadrilateral having four surfaces. The dummy gate electrode can surround the three surfaces of the photodiode.

Description

Image sensor and manufacturing method thereof {IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME}

1 is a circuit diagram showing a unit pixel of a general CMOS image sensor.

2 is a plan view showing unit pixels of a general CMOS image sensor;

3 is a cross-sectional view taken along the line II ′ of FIG. 2;

4 is a plan view illustrating unit pixels of a CMOS image sensor according to an exemplary embodiment of the present invention.

5 is a cross-sectional view taken along the line II ′ of FIG. 4;

6A to 6G are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to an exemplary embodiment of the present invention illustrated in FIG. 5.

<Description of the symbols for the main parts of the drawings>

20: substrate

21: device isolation film

22: gate oxide film

23: threshold voltage control ion implantation process

24: polysilicon film

25, 27, 30, 34: photoresist pattern

24a: dummy gate electrode

24b: gate electrode for transfer transistor

24c: gate electrode for reset transistor

24d: gate electrode for drive transistor

24e: gate electrode for select transistor

29: photodiode

31: LDD ion implantation process

32: low concentration junction area

33: spacer

35 source / drain ion implantation process

36: high concentration junction region

37: floating diffusion region

The present invention relates to an image sensor and a method of manufacturing the same, and more particularly, to a CMOS image sensor including a photodiode and a method of manufacturing the same.

Recently, the demand of digital cameras is exploding with the development of video communication using the Internet. Moreover, the demand for small camera modules increases as the popularity of mobile communication terminals such as PDAs equipped with cameras, International Mobile Telecommunications-2000 (IMT-2000), Code Division Multiple Access (CDMA) terminals, etc. increases. Doing.

As a camera module, an image sensor module using a Charge Coupled Device (CCD) or a Complementary Metal-Oxide-Semiconductor (CMOS) image sensor, which are basic components, is widely used.

In general, a CMOS image sensor implements an image by forming a photodiode and a MOS transistor in a unit pixel and sequentially detecting a signal in a switching manner. Currently, a unit pixel of most CMOS image sensors is implemented. One photodiode and four NMOS transistors in which control signals Tx, Rx, Dx, and Sx are respectively input to the gate are configured.

1 is a circuit diagram illustrating a unit pixel of a general CMOS image sensor.

Referring to FIG. 1, a unit pixel of a CMOS image sensor includes a photo diode 15 that receives light to generate photocharges, and a floating diffusion node for floating the photocharges collected from the photo diodes 15. A source follower buffer amplifier (Source Follower) to amplify the potential of the transfer transistor 1 for transport to the FD, the reset transistor 2 for resetting the potential of the floating diffusion node FD, and the floating diffusion node FD. A drive transistor 3 serving as a buffer amplifier and a select transistor 4 serving as a switching function to output a signal amplified from the drive transistor 3. Herein, reference numeral '5', which is not described, refers to a load transistor receiving an R _L control signal.

FIG. 2 is a plan view illustrating unit pixels of a general CMOS image sensor, and FIG. 3 is a cross-sectional view taken along the line II ′ of FIG. 2.

Hereinafter, an operation principle of obtaining an output from the unit pixel will be described with reference to FIGS. 1 to 3.

end. First, as the reset transistor 2 is turned on, the floating diffusion node FD becomes V _DD , and accordingly, the gate potential of the driver transistor 3 becomes V _DD . At this time, the select transistor 4 is turned on to detect the potential Vout of the signal line.

I. Next, when light is incident on the photodiode 15 from the outside while the reset transistor 2 is turned off, an electron hole pair (EHP) in the photodiode 15 is proportional thereto. Is generated. Then, the potential of the photodiode 15 is changed in proportion to the amount of EHP generated in the photodiode 15.

All. At this time, when the transfer transistor 1 is turned on, the charge accumulated in the photodiode 15 is transferred to the floating diffusion node FD, and the potential of the floating diffusion node FD changes in proportion to the transferred charge amount. Accordingly, the gate potential of the driver transistor 3 is changed to change the source (or drain) 17b potential of the driver transistor 3, so that the potential Vout of the signal line when the select transistor 4 is turned on. ) Will change.

la. When the reset transistor 2 is turned on again, the process from 'a' to 'da' is repeated.

In general, in this case, the efficiency of the photodiode 15 is determined by the amount of electron hole pair (EHP) generated according to the amount of light incident on the photodiode 15.

However, according to the related art, undesired electron hole pairs are generated around the pixel by light incident to the periphery of the pixel, for example, around the photodiode 15. At this time, the generated electron hole pairs act as a cause of noise affecting neighboring pixels, causing electrical crosstalk, which causes chip malfunction.

2 and 3, reference numerals '13b', '13c', and '13d', which are not described, represent gate electrodes of reset transistors, gate electrodes of drive transistors, and gate electrodes of select transistors, respectively. And a gate conductive film 12 in a stacked structure.

Accordingly, an object of the present invention is to provide an image sensor and a method of manufacturing the same, which are designed to solve the above-described problems of the prior art, and which can suppress electrical interference caused by light incident to the periphery of a photodiode. There is this.

According to an aspect of the present invention, there is provided an image sensor including a photodiode including a photodiode, wherein the photodiode is prevented from being introduced into the photodiode. It provides an image sensor including a dummy gate electrode formed on the substrate to surround the.

In one aspect of the invention, the dummy gate electrode is connected to a power supply voltage terminal.

In one aspect of the present invention, the photodiode has a quadrangular shape having four sides, and preferably, the dummy gate electrode is formed to surround three sides of the photodiode.

In one aspect of the present invention, a gate electrode for a transfer transistor for transporting charges accumulated in the photodiode is formed on one surface of the photodiode in which the dummy gate electrode is not formed.

According to another aspect of the present invention, there is provided a method including providing a substrate defined by an active region and a field region, and forming a plurality of transistor gate electrodes including a dummy gate electrode on the substrate. And forming a photodiode in the substrate of the active region exposed to one side of the dummy gate electrode.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

4 is a plan view illustrating a unit pixel of a CMOS image sensor according to an exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along the line II ′ of FIG. 4. Here, for convenience of description, a transistor for controlling the charge of the photodiode is used as an NMOS transistor as an example, and a unit pixel composed of one photodiode and four NMOS transistors is illustrated.

4 and 5, a CMOS image sensor according to an embodiment of the present invention includes a substrate 20 defined as an active region A and a field region (not shown), and a substrate 20 in the active region A. The photodiode 29 formed locally in Fig. 2) and the substrate 20 to enclose the photodiode 29 to prevent the charges generated around the pixel, for example electrons (-), from entering the photodiode 29. And a dummy gate electrode 24a formed thereon.

Here, since the dummy gate electrode 24a is electrically connected to the power supply voltage terminal V _DD through a predetermined contact plug (not shown), the power supply voltage is applied to the dummy gate electrode 24a and is generated around the pixel. The electrons can be obtained at the bottom of the dummy gate electrode 24a. Therefore, since the electrons generated in the periphery of the pixel can be prevented from flowing into the photodiode 29, the interference of the image sensor can be suppressed to improve reliability.

In particular, the photodiode 29 has a quadrangular shape having four sides, wherein the dummy gate electrode 24a is formed to surround three sides of the photodiode 29. Preferably, on one surface of the photodiode 29 where the dummy gate electrode 24a is not formed, a gate electrode 24b for a transfer transistor for transporting charges accumulated in the photodiode 29, for example, electrons, is formed.

In this case, the dummy gate electrodes 24a are connected to one another so as to surround three surfaces of the photodiode 29, and overlap the active regions A and the field regions, respectively. The active region A and the field region are defined by the device isolation film 21.

At this time, the dummy gate electrode 24a and the transfer transistor gate electrode 24b are provided with spacers 33 on both side walls thereof, and are electrically separated from the substrate 20 through the gate oxide film 22. The same applies to the reset transistor gate electrode 24c, the drive transistor gate electrode 24d, and the select transistor gate electrode 24e constituting the pixel.

In the substrate 20 exposed by the transfer transistor gate electrode 24b, the reset transistor gate electrode 24c, the drive transistor gate electrode 24d, and the select transistor gate electrode 24e, LDD (Lightly) A source / drain region (not shown) having a Doped Darin structure is formed. As an example, only the floating diffusion region 37 formed in one substrate 20 of the gate electrode 24b for the transfer transistor is shown. That is, the floating diffusion region 37 has an LDD structure composed of the low concentration junction region 32 and the high concentration junction region 36.

Hereinafter, a method of manufacturing a CMOS image sensor according to an exemplary embodiment of the present invention shown in FIG. 5 will be described with reference to FIGS. 6A to 6G. In addition, only the gate electrode 24b for a transfer transistor, the photodiode 29, and the floating diffusion region 37 are shown as a part which comprises a unit pixel of a CMOS image sensor here.

First, as shown in FIG. 6A, a device isolation film 21 is formed in the substrate 20 by applying a known shallow trench isolation (STI) technique. As a result, the substrate 20 is defined as an active region and a field region.

For example, the substrate 20 may be a P-type substrate doped with a P-type, and an epitaxial layer (not shown) may be epitaxially grown by doping the same P-type impurities on the substrate 20.

Subsequently, an oxide process is performed to form a gate oxide film 22 on the substrate 20 including the device isolation film 21. The oxidation process is performed by a wet oxidation method in which the silicon substrate 20 is heated at a temperature of approximately 900 to 1000 ° C. in an oxidizing gas such as water vapor or a dry type that is heated at a temperature of about 1200 ° C. using pure oxygen as an oxidizing gas. It is carried out by oxidation method.

Subsequently, the threshold voltage control ion implantation step 23 using the gate oxide film 22 as a screen oxide film is performed to implant impurity ions for controlling the threshold voltage of the transistor into the substrate 20.

6B, a polysilicon film 24 is deposited on the gate oxide film 22 as a gate conductive film. The polysilicon film 24 is formed of a doped or undoped silicon film. For example, in the case of an undoped silicon film, it is deposited by a low pressure chemical vapor deposition (LPCVD) method using SiH ₄ . On the other hand, in the case of the doped silicon film is deposited by LPCVD method using a gas mixed with PH ₃ , PCl ₅ , BCl ₃ or B ₂ H ₆ in SiH ₄ .

Subsequently, as illustrated in FIG. 6C, a photoresist film (not shown) is applied onto the polysilicon film 24 (see FIG. 6B), and then an exposure and development process using a photomask (not shown) is performed to form a photoresist pattern ( 25). Here, the photosensitive film pattern 25 is for defining a plurality of gate electrodes.

Next, an etching process using the photosensitive film pattern 25 as a mask is performed to etch the polysilicon film 24. As a result, a plurality of transistor gate electrodes including the dummy gate electrode 24a are formed on the gate oxide film 22. For example, as shown in FIG. 4, the plurality of transistor gate electrodes include a transfer transistor gate electrode 24b, a reset transistor gate electrode 24c, a drive transistor gate electrode 24d, and a select transistor gate electrode 24e. Include.

In particular, the dummy gate electrode 24a may be formed to overlap the active region and the field region, respectively.

Preferably, the dummy gate electrode 24a formed adjacent to the gate electrode 24b for the transfer transistor is formed in a 'c' shape. This is because the photodiode to be formed through the subsequent process is formed in a quadrangular shape having four surfaces, to cover three surfaces except for one surface on which the gate electrode 24b for the transfer transistor is formed.

Next, as shown in FIG. 6D, a predetermined photoresist pattern 27 is disposed on the substrate 20 to cover the plurality of transistor gate electrodes including the dummy gate electrode 24a and the transfer transistor gate electrode 24b. Form.

Here, the photoresist pattern 27 is used to define a photodiode and has a structure in which the photodiode region PD on which the photodiode is to be opened is opened. For example, a portion of the substrate 20 between the dummy gate electrode 24a and the transfer transistor gate electrode 24b is exposed. Preferably, the photosensitive film pattern 27 is formed to be aligned with one side of the gate electrode 24b for the transfer transistor.

Subsequently, an ion implantation process 28 using the photosensitive film pattern 27 as a mask is performed to form the photodiode 29 in the substrate 20 of the photodiode region PD. For example, the ion implantation process 28 implants an N-type dopant, that is, phosphorus (P) or arsenic (As), which is a Group 5 material, and then performs a thermal process to diffuse the photodiode 29 to form the photodiode 29. do.

Subsequently, as shown in FIG. 6E, a strip process is performed to remove the photoresist patterns 27 and 25 (see FIG. 6D).

Subsequently, in order to protect the photodiode region PD by using a known photolithography technique, the photoresist layer pattern 30 having a structure covering the region between the dummy gate electrode 24a and the transfer transistor gate electrode 24b is applied. Form separately.

Subsequently, an LDD ion implantation process 31 using the photosensitive film pattern 30 as a mask is performed to expose the substrate 20 in the active region exposed to both sides of the plurality of transistor gate electrodes including the transfer transistor gate electrode 24b. Each of the low concentration junction regions 32 is formed.

Subsequently, as illustrated in FIG. 6F, a strip process is performed to remove the photoresist pattern 30 (see FIG. 6E).

Subsequently, spacers 33 are formed on both side walls of the plurality of transistor gate electrodes including the dummy gate electrode 24a and the transfer transistor gate electrode 24b. For example, after depositing a spacer insulating film along a step of an upper portion of the entire structure where the dummy gate electrode 24a and the transfer transistor gate electrode 24b are formed, the spacer 33 is dry-etched to form spacers 33 on both sidewalls of each gate electrode. Form.

Subsequently, in order to protect the photodiode region PD by using a known photolithography technique, a photosensitive film pattern 34 having a structure covering the region between the dummy gate electrode 24a and the transfer transistor gate electrode 24b is separately provided. Form.

Subsequently, a source / drain ion implantation process 35 using the photoresist pattern 34 as a mask is performed to form high concentration junction regions 32 in the active regions substrate 20 exposed on both sides of the spacer 33. . As a result, source / drain regions (not shown) constituting the plurality of transistors are formed. Here, only the floating diffusion region 37 constituting the transfer transistor is shown.

Subsequently, as shown in FIG. 6G, a strip process is performed to remove the photoresist pattern 34 (see FIG. 6F).

Next, although not shown in the drawing, a contact process and a wiring process for connecting the dummy gate electrode 24a with the power supply voltage terminal V _DD are performed.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, a dummy gate electrode is formed on the substrate to surround the photodiode in order to prevent the charge generated in the periphery of the pixel from flowing into the photodiode, and the dummy gate electrode is connected to the power supply voltage terminal. By connecting, the power supply voltage is applied to the dummy gate electrode and at the same time, electrons generated around the pixel can be obtained at the bottom of the dummy gate electrode.

Accordingly, since the charge generated in the periphery of the pixel can be prevented from flowing into the photodiode, thereby improving the reliability by suppressing the crosstalk of the image sensor. In addition, malfunction of the image sensor chip can be prevented.

Claims (13)

An image sensor having a pixel including a photodiode, And a dummy gate electrode formed on a substrate to surround the photodiode to prevent charge generated in the periphery of the pixel from flowing into the photodiode. The method of claim 1, The dummy gate electrode is an image sensor connected to the power supply voltage terminal. The method of claim 2, The photodiode has an image sensor having a quadrangular shape having four sides. The method of claim 3, wherein The dummy gate electrode is formed to surround three sides of the photodiode. The method of claim 4, wherein The dummy gate electrode is formed to overlap each of the active area and the field area. The method according to claim 4 or 5, And a gate electrode for a transfer transistor configured to transfer charges accumulated in the photodiode on one surface of the photodiode in which the dummy gate electrode is not formed. Providing a substrate defined by an active region and a field region; Forming a plurality of transistor gate electrodes including a dummy gate electrode on the substrate; And Forming a photodiode in the substrate of the active region exposed to one side of the dummy gate electrode Image sensor manufacturing method comprising a. The method of claim 7, wherein The photodiode has a quadrangular shape having a four-sided image sensor manufacturing method. The method of claim 8, The dummy gate electrode is formed to surround three surfaces of the photodiode. The method of claim 9, Forming the photodiode, Forming a photoresist pattern exposing a portion of the substrate between the dummy gate electrode and a gate electrode for a transfer transistor that carries charges accumulated in the photodiode; And Performing an ion implantation process using the photoresist pattern Image sensor manufacturing method comprising a. The method of claim 10, And the photosensitive film pattern is aligned to one side of the gate electrode for the transfer transistor. The method of claim 11, And the dummy gate electrode overlaps the active region and the field region, respectively. The method according to any one of claims 7 to 12, And forming a photodiode, and performing a contact process and a wiring process for connecting the dummy gate electrode to a power supply voltage terminal.

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