KR100769137B1 - method for manufacturing CMOS image sensor - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a CMOS image sensor that increases the transmission of light incident on a photodiode to improve the characteristics of an image sensor. Forming a gate electrode through a gate insulating film, forming a first conductivity type first impurity region in a transistor region on one side of the gate electrode, and forming a first conductivity type agent in a photodiode region on the other side of the gate electrode Forming a second impurity region, forming first and second sidewall insulating films on both sides of the gate electrode, and forming a first conductivity type third impurity region in the transistor region in which the first impurity region is formed And a second conductivity type fourth impurity region in the photodiode region in which the second impurity region is formed. It characterized by forming, including the steps of forming and the step of selectively removing the second side wall insulating film formed on the side above the photodiode region.

Image Sensor, Photodiode, Sidewall Insulation

Description

Method for manufacturing CMOS image sensor

1 is an equivalent circuit diagram of a typical 4T CMOS image sensor

2 is a layout diagram showing unit pixels of a general 4T CMOS image sensor;

3 is a cross-sectional view illustrating a photodiode and a transfer gate on the line II ′ of FIG. 2.

4A to 4I are cross-sectional views illustrating a method of manufacturing the CMOS image sensor according to the related art.

5 is a cross-sectional view showing a CMOS image sensor according to the present invention

6A to 6J are cross-sectional views illustrating a method of manufacturing the CMOS image sensor according to the present invention.

Explanation of symbols for the main parts of the drawings

111 epitaxial layer 112 gate insulating film

113: gate electrode 114: thermal oxide film

115: first photosensitive film 116: n ^- type diffusion region

117: second photosensitive film 118: n ^- type diffusion region

119: first sidewall insulating film 120: second sidewall insulating film

121: third photosensitive film 122: n ⁺ type diffusion region

123: fourth photosensitive film 124: p ⁰ type diffusion region

The present invention relates to a CMOS image sensor, and more particularly, to a method for manufacturing a CMOS image sensor to increase the amount of light incident on the photodiode to improve the characteristics of the image sensor.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal, and is generally a charge coupled device (CCD) and CMOS metal (Complementary Metal Oxide Semiconductor) image. It is divided into Image Sensor.

In the charge coupled device (CCD), a plurality of photo diodes (PDs) for converting a signal of light into an electrical signal are arranged in a matrix form, and the photo diodes in each vertical direction arranged in the matrix form. A plurality of vertical charge coupled device (VCCD) formed between the plurality of vertical charge coupled devices (VCCD) for vertically transferring charges generated in each photodiode, and horizontally transferring charges transferred by the respective vertical charge transfer regions; A horizontal charge coupled device (HCCD) for transmitting to the sensor and a sense amplifier (Sense Amp) for outputting an electrical signal by sensing the charge transmitted in the horizontal direction.

However, such a CCD has a disadvantage in that the manufacturing method is complicated because the driving method is complicated, the power consumption is large, and the multi-step photo process is required.

In addition, the charge coupling device has a disadvantage in that it is difficult to integrate a control circuit, a signal processing circuit, an analog / digital converter (A / D converter), and the like into a charge coupling device chip, which makes it difficult to miniaturize a product.

Recently, CMOS image sensors have attracted attention as next generation image sensors for overcoming the disadvantages of the charge coupled device.

The CMOS image sensor uses CMOS technology that uses a control circuit, a signal processing circuit, and the like as peripheral circuits to form MOS transistors corresponding to the number of unit pixels on a semiconductor substrate, thereby forming the MOS transistors of each unit pixel. The device adopts a switching method that sequentially detects output.

That is, the CMOS image sensor implements an image by sequentially detecting an electrical signal of each unit pixel by a switching method by forming a photodiode and a MOS transistor in the unit pixel.

The CMOS image sensor has advantages, such as a low power consumption, a simple manufacturing process according to a few photoprocess steps, by using CMOS manufacturing technology.

In addition, since the CMOS image sensor can integrate a control circuit, a signal processing circuit, an analog / digital conversion circuit, and the like into the CMOS image sensor chip, the CMOS image sensor has an advantage of easy miniaturization.

Therefore, the CMOS image sensor is currently widely used in various application parts such as a digital still camera, a digital video camera, and the like.

On the other hand, CMOS image sensors are classified into 3T type, 4T type, and 5T type according to the number of transistors. The 3T type consists of one photodiode and three transistors, and the 4T type consists of one photodiode and four transistors.

Herein, the layout of the unit pixels of the 4T-type CMOS image sensor will be described.

1 is an equivalent circuit diagram of a general 4T CMOS image sensor, and FIG. 2 is a layout showing unit pixels of a typical 4T CMOS image sensor. 3 is a cross-sectional view illustrating a photodiode and a transfer gate on the line II ′ of FIG. 2.

As illustrated in FIG. 1, the unit pixel 100 of the CMOS image sensor includes a photo diode 10 as a photoelectric converter and four transistors. Each of the four transistors is a transfer transistor 20, a reset transistor 30, a source floor transistor 40 and a select transistor 50. In addition, the load transistor 60 is electrically connected to the output terminal OUT of each unit pixel 100.

Here, reference numeral FD is a floating diffusion region, Tx is a gate voltage of the select transistor 20, Rx is a gate voltage of the reset transistor 30, Dx is a gate voltage of the source floor transistor 40, Sx Is the gate voltage of the select transistor 50.

In the unit pixel of a typical 4T type CMOS image sensor, as shown in FIG. One photodiode PD is formed in a wide portion of the active region, and gate electrodes 23, 33, 43, and 53 of four transistors are formed in the active region of the remaining portion, respectively.

That is, the transfer transistor 20 is formed by the gate electrode 23, the reset transistor 30 is formed by the gate electrode 33, and the source floor transistor 40 is formed by the gate electrode 43. Is formed, and the select transistor 50 is formed by the gate electrode 53.

Here, impurity ions are implanted into the active region of each transistor except for the lower portion of each gate electrode 23, 33, 43, 53 to form a source / drain region S / D of each transistor.

Referring to the cross-section of the photodiode and the transfer transistor of the conventional CMOS image sensor having the above configuration is as follows.

A, by carrying out the process paeksyeol the P ⁺⁺ type semiconductor substrate P as shown in Figure 3 ^- type epitaxial layer 11 is formed.

A gate insulating film 21 and a gate electrode 23 are formed on a portion of the epitaxial layer 11 for the transfer transistor 20 of FIG. 2, and the first and second sidewalls are formed on both sidewalls of the gate electrode 23. Insulation layers 29 and 30 are formed.

In addition, an n ⁻ type diffusion region 28 and a P ° type diffusion region 35 are formed in the epi layer 11 of the photodiode region PD. The P ° diffusion region 35 is formed on the n ⁻ type diffusion region 35. In addition, the source / drain regions S / D have a high concentration n + type diffusion region (N ⁺ ) 32 and a low concentration n type diffusion region (n ⁻ ) 26.

4A to 4I are cross-sectional views illustrating a method of manufacturing the CMOS image sensor according to the related art.

As shown in FIG. 4A, a low concentration P ⁻ type epitaxial layer 11 is formed on a semiconductor substrate such as high concentration P ⁺⁺ type single crystal silicon by an epitaxial process.

In this case, the epitaxial layer 11 is to increase the ability of the low-voltage photodiode to collect photo charges by forming a large and deep depletion region in the photodiode and further improve the optical sensitivity.

Subsequently, a gate insulating film 21 and a conductive layer (for example, a high concentration polycrystalline silicon layer) are sequentially deposited on the epi layer 11, and the conductive layer is selectively removed through a photo and etching process. 23).

The gate insulating layer 21 may be formed by a thermal oxidation process or a CVD method, and a silicide layer may be further formed on the conductive layer to form a gate electrode.

As shown in FIG. 4B, the gate electrode 23 is thermally oxidized to form a thermal oxide film 24 on the surface of the gate electrode 23.

As shown in FIG. 4C, after the first photosensitive film 25 is coated on the semiconductor substrate, the photodiode region is covered by an exposure and development process and patterned so as to expose the source / drain regions of the transistors.

The low concentration n ⁻ type diffusion region 26 is formed by implanting low concentration n ⁻ type impurity ions into the exposed source / drain regions using the patterned first photoresist layer 25 as a mask.

As shown in FIG. 4D, after removing all of the first photoresist layer 25, the second photoresist layer 27 is applied to the entire surface of the semiconductor substrate, and then patterned to expose the photodiode region in an exposure and development process. do.

In addition, by using the patterned second photoresist layer 27 as a mask, low concentration n ⁻ -type impurity ions are implanted into the epitaxial layer 11 with ion implantation energy of 100 KeV to 500 KeV to low concentration n ⁻ type diffusion region in the photodiode region. (PDN) 28 is formed.

Here, the impurity ion implantation for forming the low concentration n ⁻ type diffusion region 28 of the photodiode region is ion implanted at a higher energy than the low concentration n ⁻ type diffusion region 26 of the source / drain region and deeper. Form.

As shown in FIG. 4E, all of the second photosensitive film 27 is removed, and the oxide film 29a and the nitride film 30a are sequentially turned on the entire surface of the semiconductor substrate by a chemical vapor deposition process (low pressure chemical vapor deposition process) or the like. Form.

As shown in FIG. 4F, an etch back process is performed on the entire surfaces of the nitride film 30a and the oxide film 29a to form first and second sidewall insulating films 29 and 30 on both sides of the gate electrode 123. do.

As shown in FIG. 4G, after the third photosensitive film 31 is applied onto the semiconductor substrate, the third photosensitive film 31 is patterned such that the third photosensitive film 31 remains on the photodiode region in an exposure and development process.

Subsequently, a high concentration n ⁺ impurity ions are implanted into the source / drain region using the patterned third photoresist layer 31 as a mask to form an n ⁺ type diffusion region 32.

As shown in FIG. 4H, all of the third photoresist layer 31 is removed, the fourth photoresist layer 34 is applied to the entire surface of the semiconductor substrate, and then patterned to expose the photodiode region in an exposure and development process. do.

P0 type impurity ions are implanted using the patterned fourth photoresist layer 34 as a mask to form a P0 type diffusion region (PDP) on the epitaxial layer 11 surface of the n ⁻ type diffusion region 28 of the photodiode region. (35).

Here, the photodiode may be formed only by the n ⁻ type diffusion region 28 without forming the p ⁰ type diffusion region 35.

As shown in FIG. 4I, after the fourth photosensitive film 34 is removed, a heat treatment process (for example, a rapid heat treatment process) is performed to form the n ⁻ type diffusion region 26 and the p ⁰ type diffusion region 35. ), the impurity ions in the n ⁻ type diffusion region 28 and the n ⁺ type diffusion region 32 are diffused.

However, there is a problem in the method of manufacturing the CMOS image sensor according to the prior art as described above.

That is, the portion where the sidewall insulating film is formed toward the photodiode region to which light is incident to the photodiode is very poor in light transmittance due to the sidewall insulating film. This decreases the characteristics of the image sensor because the photodiode region becomes smaller.

The present invention has been made to solve the above problems to provide a method of manufacturing a CMOS image sensor to improve the characteristics of the image sensor by preventing the transmittance of light incident on the photodiode by the sidewall insulating film is reduced. Its purpose is.

The method for manufacturing the CMOS image sensor according to the present invention for achieving the above object comprises the steps of: forming a gate electrode on a semiconductor substrate having a photodiode region and an active region defined by a transistor region through a gate insulating film; Forming a first conductivity type first impurity region in the transistor region on one side of the gate electrode, forming a first conductivity type second impurity region in the photodiode region on the other side of the gate electrode, and opposite side surfaces of the gate electrode Forming first and second sidewall insulating films on the first semiconductor layer; forming a first conductivity type third impurity region in the transistor region in which the first impurity region is formed; and forming a photodiode region in the photodiode region in which the second impurity region is formed. Forming a second conductivity type fourth impurity region, and a second sidewall formed toward the photodiode region And selectively removing the insulating film.

delete

Hereinafter, a CMOS image sensor and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

5 is a structural cross-sectional view showing a CMOS image sensor according to the present invention.

As shown in FIG. 5, a low concentration P ⁻ type epitaxial layer 111 formed on a semiconductor substrate such as a high concentration P ⁺⁺ type single crystal silicon having an active region defined by a photodiode region and a transistor region, and an active portion of the semiconductor substrate. A gate electrode 113 formed in the region via the gate insulating layer 112, an n ⁻ type diffusion region 116 formed in the transistor region on one side of the gate electrode 113, and the other side of the gate electrode 113. An n ⁻ type diffusion region 118 formed deeper in the photodiode region than the n ⁻ type diffusion region 116, and first and second sidewall insulating layers 119 and 120 formed in a transistor region on one side of the gate electrode 113. ), A first sidewall insulating layer 119 formed in the photodiode region on the other side of the gate electrode 113, and a transistor region on one side of the gate electrode 113 and the first and second sidewall insulating layers 120 and 121. Being n ^And a p ⁰ type diffusion region 124 formed in the photodiode region on the other side of the gate electrode 113.

6A to 6J are cross-sectional views illustrating a method of manufacturing the CMOS image sensor according to the present invention.

As shown in FIG. 6A, a low concentration P ⁻ type epitaxial layer 111 is formed on a semiconductor substrate such as high concentration P ⁺⁺ type single crystal silicon by an epitaxial process.

In this case, the epitaxial layer 111 is to increase the ability of the low-voltage photodiode to collect photo charges by forming a large and deep depletion region in the photodiode and further improve the optical sensitivity.

Subsequently, a gate insulating layer 112 and a conductive layer (for example, a high concentration polycrystalline silicon layer) are sequentially deposited on the entire epitaxial layer 111, and the conductive layer is selectively removed through a photo and etching process. 113).

The gate insulating layer 112 may be formed by a thermal oxidation process or a CVD method, and a silicide layer may be further formed on the conductive layer to form a gate electrode.

As shown in FIG. 6B, the gate electrode 113 is thermally oxidized to form a thermal oxide film 114 within about 60 kPa on the surface of the gate electrode 113.

As shown in FIG. 6C, after the first photoresist film 115 is applied onto the semiconductor substrate, the photodiode region is covered by an exposure and development process and patterned so that the source / drain regions of each transistor are exposed.

The n ^- type diffusion region 116 is formed by implanting low ^- concentration n ⁻ -type impurity ions into the exposed source / drain regions using the patterned first photoresist film 115 as a mask.

As shown in FIG. 6D, after removing all of the first photoresist film 115, the second photoresist film 117 is applied to the entire surface of the semiconductor substrate, and then patterned to expose the photodiode region in an exposure and development process. do.

Subsequently, low concentration n ⁻ -type impurity ions are implanted into the epitaxial layer 111 using ion implantation energy between 100 KeV and 500 KeV using the patterned second photoresist layer 117 as a mask, thereby forming an n ⁻ type diffusion region in the photodiode region. PDN) 118 is formed.

Here, impurity ion implantation for forming the n ⁻ type diffusion region 118 of the photodiode region is formed deeper by ion implantation with higher energy than the n ⁻ type diffusion region 116 of the source / drain region.

As shown in FIG. 6E, all of the second photoresist film 117 is removed, and the oxide film 119a and the nitride film 120a are sequentially turned on the entire surface of the semiconductor substrate by a chemical vapor deposition process (low pressure chemical vapor deposition process) or the like. Form.

Here, the oxide film 119a is formed to a thickness of about 200 kPa, and the nitride film 120a is formed to a thickness of about 800 kPa.

As illustrated in FIG. 6F, an etch back process is performed on the entire surfaces of the nitride film 120a and the oxide film 119a to form first and second sidewall insulating films 119 and 120 on both sides of the gate electrode 113.

As shown in FIG. 6G, after the third photoresist film 121 is coated on the semiconductor substrate, the third photoresist film 121 is patterned such that the third photoresist film 121 remains on the photodiode region in an exposure and development process.

Subsequently, a high concentration n ⁺ impurity ions are implanted into the source / drain region using the patterned third photoresist layer 121 as a mask to form an n ⁺ type diffusion region 122.

As shown in FIG. 6H, the third photoresist film 121 is removed, the fourth photoresist film 123 is coated on the semiconductor substrate, and the fourth photodiode region is opened by an exposure and development process. The photosensitive film 123 is selectively patterned.

Next, the patterned fourth by using the photosensitive film 123 as a mask, wherein the 2 n ^- type diffusion region 118 diffuse p ⁰ type in a surface of a semiconductor substrate by implanting p ^0-type impurity ions into the photodiode region is formed, Area 124 is formed.

Here, BF ₂ is used as the impurity ions of the p ⁰ type diffusion region 124, and the implantation energy is implanted at 1 × 10 ¹⁶ to 5 × 10 ¹⁷ atoms / cm 2 when the BF ₂ ion is implanted, and the implantation energy is Is carried out at 5 to 20 KeV.

As shown in FIG. 6I, the second sidewall insulating layer 120 is selectively removed using the fourth photosensitive layer 123 as a mask.

Here, the second sidewall insulating layer 120 is removed by wet etching.

As shown in FIG. 6J, after removing the fourth photoresist film 123, the semiconductor substrate is subjected to a heat treatment process (for example, a rapid heat treatment process) at a temperature of 800 to 1200 ° C. to form the n ⁻ type diffusion region. 116, the p ⁰ diffusion region 124, the n ⁻ type diffusion region 118 and the n ⁺ type diffusion region 122 are diffused.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The manufacturing method of the CMOS image sensor according to the present invention as described in detail above has the following effects.

That is, by removing a part of the sidewall insulating film formed on the photodiode region side, it is possible to improve the characteristics of the image sensor by increasing the amount of light incident on the photodiode.

Claims (8)

delete Forming a gate electrode through a gate insulating film on a semiconductor substrate having an active region defined by a photodiode region and a transistor region; Forming a first conductivity type first impurity region in the transistor region on one side of the gate electrode; Forming a first conductivity type second impurity region in the photodiode region on the other side of the gate electrode; Forming first and second sidewall insulating films on both side surfaces of the gate electrode; Forming a first conductivity type third impurity region in the transistor region in which the first impurity region is formed; Forming a second conductivity type fourth impurity region in the photodiode region in which the second impurity region is formed; And selectively removing the second sidewall insulating film formed on the photodiode region. The method of claim 2, wherein the first conductivity type second impurity region is formed deeper than the first conductivity type first impurity region. The method of claim 2, further comprising forming an oxide film within 60 μs on the surface of the gate electrode. The method of claim 2, wherein the first sidewall insulating layer and the second sidewall insulating layer are formed of a material having a different etching selectivity. 3. The method of claim 2, wherein the first sidewall insulating film forms an oxide film. 3. The method of claim 2, wherein the second sidewall insulating film is formed of a nitride film. The method of claim 2, wherein the second sidewall insulating layer is removed by wet etching.

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