KR20070033694A - MOS image sensor manufacturing method - Google Patents

Abstract

The present invention is to provide a method for manufacturing a CMOS image sensor that can prevent the depletion region is generated in the finally formed p ⁰ doped region to prevent the deterioration of device characteristics due to the inflow of dark current, the present invention provides a gate Providing a substrate having an electrode and a first conductivity type first doped region for a photodiode, and a whole structure including a cone defect structure layer formed on the first doped region for the photodiode during the gate electrode forming process Forming a thermal oxide film on the upper surface, performing a thermal oxidation process to form a thermal oxide film on the upper surface of the entire structure including the first doped region, and forming a second conductive type second in the second doped region. Forming a doped region, performing a cleaning process to remove the thermal oxide film to remove the cone defect structure layer, and Forming a spacer on both sidewalls of a bit electrode, and forming a second conductivity type third doped region deeper than the second doped region in the first doped region. .

 CMOS image sensor, cone defect, dark current, thermal oxide film

Description

Manufacturing method of CMOS image sensor {METHOD FOR MANUFACTURING CMOS IMAGE SENSOR}

1 is a circuit diagram illustrating a unit pixel of a general CMOS image sensor.

2A to 2D are cross-sectional views illustrating a manufacturing process of a CMOS image sensor according to the prior art.

3A to 3E are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to a preferred embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

10, 110: semiconductor substrate

11, 111: channel stop layer

12, 112: device isolation film

13, 113: well area

14, 114: gate insulating film

15, 115: polysilicon film

16a, 16b, 116a, 116b: gate electrode

17, 117 n-doped region

18, 24, 120, 127: p ⁰ doped region

19a, 19b, 121a, 121b: Lightly Doped Drain (LDD) Region

20, 123: silicon oxide film

21, 124: silicon nitride film

22a, 22b, 125a, 125b: spacer

23a, 23b, 126a, 126b: source / drain regions

16c, 116c: cone defect structure layer

119: thermal oxide film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a method of manufacturing a complementary metal-oxide-semiconductor (CMOS) image sensor among semiconductor devices.

Recently, the demand of digital cameras is exploding with the development of video communication using the Internet. Moreover, as the popularity of mobile communication terminals such as personal digital assistants (PDAs) equipped with cameras, International Mobile Telecommunications-2000 (IMT-2000), and code division multiple access (CDMA) terminals increases, the demand for small camera modules increases. It is increasing.

As a camera module, an image sensor module using a Charge Coupled Device (CCD) or a Complementary Metal-Oxide-Semiconductor (CMOS) image sensor, which are basic components, is widely used. The image sensor is arranged on the upper part of the light sensing unit for generating and accumulating photocharges from the outside to implement a color image. Such color filter arrays (CFAs) are red (R), green (G) and blue (B), or yellow, magenta, and cyan. It consists of a branch collar. Typically, three colors of red (R), green (G), and blue (B) are frequently used in a color filter array of a CMOS image sensor.

Such an image sensor is a semiconductor device that converts an optical image into an electrical signal. As described above, a CCD and a CMOS image sensor have been developed and widely commercialized. A CCD is a device in which charge carriers are stored and transported in a capacitor while individual metal-oxide-silicon (MOS) capacitors are in close proximity to each other. On the other hand, a CMOS image sensor uses a CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits to make MOS transistors by the number of pixels, and uses the switching to detect an output sequentially. It is a device employing the method.

However, CCD has many disadvantages such as complicated driving method, high power consumption, high number of mask processes, complicated process, and difficult to implement one chip because signal processing circuit cannot be implemented in CCD chip. Recently, researches on the development of CMOS image sensors using sub-micron CMOS manufacturing techniques have been enthusiastically conducted to overcome the disadvantages of the CCD.

The CMOS image sensor forms an image by forming a photo diode and a MOS transistor in a unit pixel and sequentially detects a signal in a switching method. Since the CMOS manufacturing technology is used, the power consumption is low and the number of masks is approximately. The process is very simple compared to CCD process that requires 30 to 40 masks, and it is possible to make various signal processing circuits and one chip.

In general, the CMOS image sensor is composed of a light sensing unit for detecting light and a logic circuit unit for processing the light detected by the light sensing unit into an electrical signal and converting the data into an electric signal. Efforts are underway to increase this fill factor. However, there is a limit to this effort under a limited area since the logic circuit part cannot be removed essentially. Accordingly, in order to increase the light sensitivity, a condensing technology that changes the path of light incident to an area other than the light sensing unit and collects the light sensing unit has emerged. For this purpose, an image sensor forms a microlens on a color filter. I'm using the method.

1 is a circuit diagram illustrating a unit pixel of a general CMOS image sensor.

Referring to FIG. 1, a unit pixel of a CMOS image sensor includes one photo diode (PD) and four MOS transistors, and the four MOS transistors include a transfer transistor (Tx), a reset transistor (Rx), and a drive. It consists of a transistor MD and a selector transistor Sx. A load transistor is formed outside the unit pixel to read an output signal. Unexplained reference 'Cfd' indicates the capacitance of the floating diffusion.

Hereinafter, a method of manufacturing a CMOS image sensor according to the prior art will be described with reference to FIGS. 2A to 2D. 2A to 2D, only one of a plurality of transistors of a photodiode, a transfer transistor, and a logic circuit unit is illustrated for convenience of description.

First, as shown in FIG. 2A, a logic region is defined as a region (hereinafter referred to as a logic region) and a region where a pixel including a light sensing unit is formed (hereinafter referred to as a pixel region). Provides a semiconductor substrate 10 defined as a region where a photodiode is formed (hereinafter referred to as PD) and a region where a transfer transistor is formed (hereinafter referred to as Tx). In this case, the semiconductor substrate 10 has a structure in which a P + region and a P- epi layer are stacked.

Subsequently, a trench isolation (not shown) is formed by performing a shallow trench isolation (STI) process, and a channel stop region 11 is formed by performing a channel stop ion implantation process to form a trench. A device isolation film 12 is formed.

Subsequently, a well ion implantation process is performed to form the well region 13 for the logic element in the logic region, and p-type or n-type impurities are selectively implanted to control the threshold voltage, thereby forming a p-type or n-type region (not shown). To form.

Subsequently, as shown in FIG. 2B, the gate insulating layer 14 and the polysilicon layer 15 are sequentially formed on the substrate 10 and then etched to form the gate electrodes 16a and 16b in the logic region and the Tx region, respectively. To form.

Next, as illustrated in FIG. 2C, an n-ion implantation process using an n-ion implantation mask (not shown) is performed to form an n-doped region 17 constituting a photodiode in the PD region.

Subsequently, a first p ⁰ ion implantation process using a p ⁰ ion implantation mask (not shown) is performed to form a p ⁰ doped region 18 in the n − doped region 17. At this time, the p ⁰ doped region 18 is formed relatively thin.

Subsequently, an LDD ion implantation process using a lightly doped drain (LDD) ion implantation mask (not shown) is performed to form LDD regions 19a and 19b in the substrate 10 exposed to both sides of the gate electrodes 16a and 16b. do.

Subsequently, as shown in FIG. 2D, spacers 22a and 22b are formed on both side walls of the gate electrodes 16a and 16b, respectively. In this case, the spacers 22a and 22b have a stacked structure of the silicon oxide film 20 and the silicon nitride film 21. The manufacturing process is performed by sequentially forming the silicon oxide film 20 and the silicon nitride film 21. It is done by the process.

Meanwhile, spacers 22c are formed on both sidewalls of the cone defect structure layer 16c during the spacer process.

Subsequently, a source / drain ion implantation process using a source / drain ion implantation mask (not shown) is performed to relatively expose the logic region and floating diffusion region (hereinafter referred to as FD) exposed to both sides of the gate electrodes 16a and 16b. High concentration n + source / drain regions 23a and 23b are formed. At this time, the source / drain regions 23a and 23b are formed deeper than the LDD regions 19a and 19b.

Subsequently, a p ⁰ ion implantation process using a second p ⁰ ion implantation mask (not shown) is performed to form a p ^o doped region 24 deeper than the p ⁰ doped region 18 in the n − doped region 17.

Subsequently, a target temperature profile is diffused by performing a rapid temperature process (RTP) or a rapid temperature process (RTA) process to diffuse the p-type or n-type impurity ions implanted during the source / drain ion implantation process and the p ⁰ ion implantation process. which forms a source / drain region and the p-doped region ^0.

However, in the method of manufacturing the CMOS image sensor according to the related art described above, the polysilicon film 15 is etched in the PD region during the dry etching process for forming the gate electrodes 16a and 16b as shown in FIG. 2B. So that a cone defect structure layer 16c is formed. The cone defect structure layer 16c is formed because the polysilicon film 15 is not etched in the PD region due to residues separated from the photoresist film used as an etching mask during the etching process of the polysilicon film 15. It is known.

As shown in FIG. 2B, the initial cone defect structure layer 16c has a small size, but as shown in FIG. 2D, spacers 22a and 22b are formed on both sidewalls of the subsequent gate electrodes 16a and 16b. During the process, spacers 22c are formed on both side walls of the cone defect structure layer 16c, thereby increasing their size. Accordingly, the second p ⁰ during the ion implantation process by the ion implantation act as a barrier layer in the region of the cone structure defect layer (16c) there are no ions are not implanted. Accordingly, the deficient region A in which no ions are implanted is present in the final p ⁰ doped region 24. The deficient region A is a portion that does not form a potential barrier against the dark current flowing from the surface, and is generated at the position where the particles are located, and serves as a passage for the dark current flowing from the surface of the substrate 10.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, the CMOS that can prevent the deterioration of the device characteristics due to the dark current inflow by preventing the deficient region is generated in the finally formed p ⁰ doped region It is an object of the present invention to provide a method for manufacturing an image sensor.

According to an aspect of the present invention, there is provided a substrate on which a gate electrode and a first conductivity type first doping region for a photodiode are formed, and the first doping for the photodiode in the gate electrode forming process. Forming a thermal oxide film on the upper surface of the entire structure including the cone defect structure layer formed on the region, and performing a thermal oxidation process to form the thermal oxide film on the upper surface of the entire structure including the first doped region. Forming a second conductivity type second doped region in the second doped region, performing a cleaning process to remove the thermal oxide layer to remove the cone defect structure layer, and both sides of the gate electrode; Forming a spacer in the wall, and forming a second conductivity type third doped region deeper than said second doped region in said first doped region. A method of manufacturing a MOS image sensor is provided.

Preferably, the thermal oxidation process is performed until all of the cone defect structure layers are converted into oxide films.

Preferably, the thermal oxide film is formed to a thickness of 30 ~ 150Å.

Preferably, the washing step is carried out using a hydrofluoric acid solution.

The method may further include forming an LDD region in the substrate exposed to both sides of the gate electrode after forming the second doped region.

The method may further include forming a source / drain region deeper than the LDD region on the substrate exposed to both sides of the spacer after the cleaning process.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

3A to 3E are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to a preferred embodiment of the present invention. 3A to 3E illustrate only one of a plurality of transistors of a photodiode, a transfer transistor, and a logic circuit unit for convenience of description.

First, as shown in FIG. 3A, a logic region is defined as a region (hereinafter referred to as a logic region) and a region in which a pixel including a light sensing unit is formed (hereinafter referred to as a pixel region). The semiconductor substrate 110 is defined as a region where a photodiode is formed (hereinafter referred to as PD) and a region where a transfer transistor is formed (hereinafter referred to as Tx). In this case, the semiconductor substrate 110 has a structure in which a P + region and a P- epi layer are stacked.

Subsequently, an STI process is performed to form a device isolation trench (not shown), a channel stop ion implantation process is performed to form a channel stop region 111, and a device isolation layer 112 is formed to fill the trench. In this case, the device isolation layer 112 is formed of an HDP (High Density Plasma) oxide film or an epitaxial growth polysilicon film having excellent embedding characteristics.

Subsequently, the well ion implantation process is performed to form the well region 113 for the logic element in the logic region, and to selectively inject p-type or n-type impurities to adjust the threshold voltage, thereby forming a p-type or n-type region (not shown) To form.

Subsequently, gate electrodes 116a and 116b are formed in the logic region and the Tx region, respectively. At this time, the gate electrodes 116a and 116b are formed in a stacked structure of the gate insulating film 114 and the polysilicon film 115. At this time, the cone defect structure layer 116c is formed in the PD region as in the prior art.

Subsequently, as shown in FIG. 3B, the n-doped region 117 constituting the photodiode relatively deeply in the substrate 110 of the PD region by performing an n-ion implantation process using an n-ion implantation mask (not shown). ).

Subsequently, a thermal oxidation process 118 is performed to form a thermal oxide film 119 on the upper surface of the substrate 110 including the gate electrodes 116a and 116b. At this time, the surface of the gate electrodes 116a and 116b is oxidized to a predetermined thickness by the thermal oxidation process 118, and the cone defect structure layer 116c is also oxidized to form a thermal oxide film 119 over the entire surface. In this process, the cone defect structure layer 116c having a small thickness is converted into an oxide film. On the other hand, the thermal oxide film 119 is formed to a thickness of 30 ~ 150Å so that the cone defect structure layer 116c is all converted into an oxide film. Hereinafter, the cone defect structure layer converted to the oxide film is denoted as '116d'.

Subsequently, as illustrated in FIG. 3C, a first p ⁰ ion implantation process using a p ⁰ ion implantation mask (not shown) is performed to form a p ⁰ doped region 120 in the n − doped region 117. In this case, the thermal oxide film 119 functions as a screen oxide film during the p ⁰ ion implantation process to protect the upper surface of the substrate 110.

Next, an LDD ion implantation process using an LDD ion implantation mask (not shown) is performed to form LDD regions 121a and 121b in the substrate 110 exposed to both sides of the gate electrodes 116a and 116b.

Subsequently, as illustrated in FIG. 3D, a cleaning process 122 is performed to remove the thermal oxide film 119 (see FIG. 3C). At this time, the washing step 122 is carried out using a hydrofluoric acid solution. The cone defect structure layer 116d oxidized by this cleaning step 122 is also etched and removed.

Subsequently, as illustrated in FIG. 3E, spacers 125a and 125b are formed on both sidewalls of the gate electrodes 116a and 116b, respectively. In this case, the spacers 125a and 125b have a stacked structure of the low pressure silicon oxide film 123 and the silicon nitride film 124. The silicon oxide film 123 and the silicon nitride film 124 are sequentially formed and then etched back. Or it is formed through an etching process such as a blanket (blanket).

Next, a source / drain ion implantation process using a source / drain ion implantation mask (not shown) is performed to relatively high concentrations in the logic region and floating diffusion region (hereinafter referred to as FD) exposed to both sides of the gate electrodes 116a and 116b. Phosphorus n + source / drain regions 126a and 126b are formed. At this time, the source / drain regions 126a and 126b are formed deeper than the LDD regions 121a and 121b.

Meanwhile, n-type impurities are also doped into the gate electrodes 116a and 116b during the source / drain ion implantation process.

Subsequently, a second p ⁰ ion implantation process using a p ⁰ ion implantation mask (not shown) is performed to form a p ^o doped region 127 deeper than the p ⁰ doped region 120 in the n − doped region 117.

Subsequently, after removing the p ⁰ ion implantation mask through a strip process, RTP or RTA processes are performed to diffuse the p-type or n-type impurity ions implanted during the source / drain ion implantation process and the p ⁰ ion implantation process to obtain a target profile ( source and drain regions having a profile) and a p ⁰ doped region.

Subsequently, the CMOS image sensor is completed by sequentially performing subsequent processes such as a metal wiring process, a color filter forming process, and a microlens forming process through a known technique.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the cone defect structure layer formed in the PD region during the gate electrode forming process is oxidized and removed before the spacer process, thereby preventing the existence of the deficient region in the p ⁰ doped region. By blocking the inflow of dark current through the deficient region, it is possible to improve the dark current characteristics, thereby improving the characteristics of the device.

Claims (6)

Providing a substrate having a gate electrode and a first conductivity type first doped region for a photodiode; Forming a thermal oxide film on an upper surface of the entire structure including a cone defect structure layer formed on the first doped region for the photodiode in the gate electrode forming process; Performing a thermal oxidation process to form a thermal oxide film on an upper surface of the entire structure including the first doped region; Forming a second conductivity type second doped region in the second doped region; Performing a cleaning process to remove the thermal oxide film to remove the cone defect structure layer; Forming spacers on both sidewalls of the gate electrode; And Forming a second conductivity type third doped region deeper in the first doped region than the second doped region Method of manufacturing a CMOS image sensor comprising a. The method of claim 1, Wherein the thermal oxidation process is performed until all of the cone defect structure layers are converted into oxide films. The method according to claim 1 or 2, The thermal oxide film is a manufacturing method of the CMOS image sensor to form a thickness of 30 ~ 150Å. The method of claim 3, wherein The cleaning process is a manufacturing method of a CMOS image sensor using a hydrofluoric acid solution. The method of claim 4, wherein And forming an LDD region in the substrate exposed to both sides of the gate electrode after forming the second doped region. The method of claim 5, And forming a source / drain region deeper than the LDD region in the substrate exposed to both sides of the spacer after the cleaning process.

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