KR100718776B1 - Method for manufacturing cmos image sensor - Google Patents

Abstract

The present invention is to provide a method of manufacturing a CMOS image sensor that can improve the Ioff (off current) and Bvdss (breakdown characteristics) of the NMOS transistor and improve the Idsat (saturation current) of the PMOS transistor while simplifying the process. To this end, the present invention provides a substrate having a first conductivity type first diffusion layer and a gate electrode formed thereon, and performing ion implantation with a blanket without an ion implantation mask to expose both sides of the first diffusion layer and the gate electrode. Forming a second diffusion layer of a second conductivity type in the substrate, forming an LDD region in a region exposed to both sides of the gate electrode among the regions where the second diffusion layer is formed, and both side walls of the gate electrode Forming a spacer in the trench, forming a source and drain region deeper than the LDD region in a region corresponding to the LDD region; It provides a method of manufacturing the CMOS image sensor 2, the diffusion layer comprising the step of forming the third diffusion layer of the second conductivity type formed in the region.

CMOS image sensor, Ioff, Idsat, Bvdss,

Description

Manufacturing method of CMOS image sensor {METHOD FOR MANUFACTURING CMOS IMAGE SENSOR}

1 is a circuit diagram illustrating a unit pixel of a general CMOS image sensor.

2 is a cross-sectional view for explaining the manufacturing process of the CMOS image sensor according to the prior art.

3 is a plan view illustrating the ion implantation mask MK used in the first p ⁰ ion implantation process in the manufacturing process of the CMOS image sensor according to the prior art.

4A to 4G are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to an embodiment of the present invention.

5 is a cross-sectional view illustrating an NMOS transistor manufactured in accordance with an embodiment of the present invention.

6 is a cross-sectional view illustrating a PMOS transistor manufactured in accordance with an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

111: p ++ substrate 112: p- epi layer

113 device separator 114 well

115: gate insulating film 116: polysilicon film

117a, 117b, and 117c: gate electrode 118: n-diffusion layer

120: p ⁰ diffusion layer 121: Lightly Doped Drain (LDD) region

122: silicon oxide film 123: silicon nitride film

125: space 126: source and drain regions

127: p ⁰ diffusion layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a method of manufacturing a complementary metal-oxide-semiconductor (CMOS) image sensor among semiconductor devices.

Recently, the demand of digital cameras is exploding with the development of video communication using the Internet. Moreover, as the popularity of mobile communication terminals such as personal digital assistants (PDAs) equipped with cameras, International Mobile Telecommunications-2000 (IMT-2000), and code division multiple access (CDMA) terminals increases, the demand for small camera modules increases. It is increasing.

As a camera module, an image sensor module using a Charge Coupled Device (CCD) or a Complementary Metal-Oxide-Semiconductor (CMOS) image sensor, which are basic components, is widely used. The image sensor is arranged on the upper part of the light sensing unit for generating and accumulating photocharges from the outside to implement a color image. Such color filter arrays (CFAs) are red (R), green (G) and blue (B), or yellow, magenta, and cyan. It consists of a branch collar. Typically, three colors of red (R), green (G), and blue (B) are frequently used in a color filter array of a CMOS image sensor.

Such an image sensor is a semiconductor device that converts an optical image into an electrical signal. As described above, a CCD and a CMOS image sensor have been developed and widely commercialized. A CCD is a device in which charge carriers are stored and transported in a capacitor while individual metal-oxide-silicon (MOS) capacitors are in close proximity to each other. On the other hand, a CMOS image sensor uses a CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits to make MOS transistors by the number of pixels, and uses the switching to detect an output sequentially. It is a device employing the method.

However, CCD has many disadvantages such as complicated driving method, high power consumption, high number of mask processes, complicated process, and difficult to implement one chip because signal processing circuit cannot be implemented in CCD chip. Recently, researches on the development of CMOS image sensors using sub-micron CMOS manufacturing techniques have been enthusiastically conducted to overcome the disadvantages of the CCD.

The CMOS image sensor forms an image by forming a photo diode and a MOS transistor in a unit pixel and sequentially detects a signal in a switching method. Since the CMOS manufacturing technology is used, the power consumption is low and the number of masks is approximately. The process is very simple compared to CCD process that requires 30 to 40 masks, and it is possible to make various signal processing circuits and one chip.

In general, the CMOS image sensor is composed of a light sensing unit for detecting light and a logic circuit unit for processing the light detected by the light sensing unit into an electrical signal and converting the data into an electric signal. Efforts are underway to increase this fill factor. However, there is a limit to this effort under a limited area since the logic circuit part cannot be removed essentially. Accordingly, in order to increase the light sensitivity, a condensing technology that changes the path of light incident to an area other than the light sensing unit and collects the light sensing unit has emerged. For this purpose, an image sensor forms a microlens on a color filter. I'm using the method.

1 is a circuit diagram illustrating a unit pixel of a general CMOS image sensor.

Referring to FIG. 1, a unit pixel of a CMOS image sensor includes one photo diode (PD) and four NMOS transistors (Tx, Rx, Dx, and Sx). Specifically, a photodiode PD for receiving incident light to generate photocharges, a transfer transistor Tx for transferring the photocharges collected from the photodiode PD to the floating diffusion region FD, and a desired value. The voltage of the floating diffusion region FD and the reset transistor Rx for setting the potential of the floating diffusion region FD and discharging the electric charges to reset the floating diffusion region FD are applied to the gate to supply a source follower buffer. A drive transistor (Dx) serving as an amplifier (source follower buffer amplifier) and a select transistor (Sx) that performs an addressing role by switching (switching). A load transistor Vb is formed outside the unit pixel to read an output signal.

FIG. 2 is a schematic cross-sectional view of a unit pixel of the CMOS image sensor illustrated in FIG. 1.

Referring to Figure 2 describes a manufacturing method of a CMOS image sensor according to the prior art.

First, a p-epitaxial layer 12 doped with a low concentration p-type impurity is grown on a p ++ substrate 11 doped with a high concentration of p-type impurity. A field insulating layer 13 for forming isolation between unit pixels is formed by an oxide of silicon process. Recently, an isolation layer is formed through a shallow trench isolation (STI) process instead of the LOCOS process.

Subsequently, the p-well 14 is formed in a predetermined region of the p-epi layer 12 so as to contain the drive transistor Dx and the select transistor Sx through lateral diffusion by a subsequent thermal process.

Subsequently, the gate electrodes 15a and 15b of the drive transistor Dx and the select transistor Sx are formed on the p-well 14, and the transfer transistor Tx and the reset transistor are formed on the p-epi layer 12. Gate electrodes 15c and 15d of (Rx) are formed. At this time, the gate electrodes 15a, 15b, 15c, and 15d of the four transistors are made of a polysilicon film and a tungsten silicide film.

Subsequently, an n-ion implantation process using an n-ion implantation mask (not shown) is performed to p-epi of one side of the gate electrode 15c of the transfer transistor Tx among the gate electrodes 15a, 15b, 15c, and 15d. The n-diffusion layer 16 is formed by ion implanting low concentration n-type impurities into the layer 12 with high ion implantation energy.

Subsequently, a first p ⁰ ion implantation process using a p ⁰ ion implantation mask (not shown) is performed to form a p ⁰ diffusion layer (not shown) in the n− diffusion layer 16. At this time, the p ⁰ diffusion layer is formed relatively thin.

Subsequently, an LDD ion implantation process using a lightly doped drain (LDD) ion implantation mask (not shown) is performed to form the LDD region 17 in regions exposed to both sides of the gate electrodes 15a to 15d.

Subsequently, spacers 18 are formed on both side walls of the gate electrodes 15a to 15d, respectively.

Subsequently, a source / drain ion implantation process using a source / drain ion implantation mask (not shown) is performed to form a relatively high concentration of n + source / drain region 20 in regions exposed to both sides of the gate electrodes 15a to 15d. do. At this time, the floating diffusion region 20a is also formed.

Subsequently, a p ⁰ ion implantation process using a second p ⁰ ion implantation mask (not shown) is performed to form a p ^o diffusion layer 19 in the n− diffusion layer 16.

Subsequently, a target temperature profile is diffused by performing a rapid temperature process (RTP) or a rapid temperature process (RTA) process to diffuse the p-type or n-type impurity ions implanted during the source / drain ion implantation process and the p ⁰ ion implantation process. which forms a source / drain region and the p-doped region ^0.

Subsequently, a TEOS (Tetra Ethyl Ortho Silicate) film and a BPSG (Boron Phosphorus Silicate Glass) film are formed on the entire structure including the source and drain regions 20 and the floating diffusion region 20a as a PMD (Pre Metal Dielectric) 21. After sequentially depositing, the substrate was reflowed and planarized in an N ₂ atmosphere.

Subsequently, after forming the metal contact (not shown) and the first metal wiring 22, an IMD (Inter Metal Dielectric) 23 is formed on the first metal wiring 22, and then a plurality of second metal wirings ( 24). In this case, the first and second metal wires 22 and 24 are formed not to overlap the photodiode PD for light transmission to the photodiode PD, and the number thereof is not limited.

Subsequently, a protective film 25 is formed on the entire surface including the second metal wiring 24 to complete a general CMOS logic process.

Subsequently, three kinds of color filters 26 are formed on the passivation layer 25 to realize a color image, and then an over coating layer (OCL) layer 27 is formed as a planarization layer for planarization. A micro lens 28 is formed to improve the quality.

However, in the CMOS image sensor manufacturing process according to the related art described above, the photo process and the strip process have to be performed during the first p ⁰ ion implantation process performed before the LDD ion implantation process. A problem arises. That is, a photo process for forming the ion implantation mask (MK) having an opening as shown in Figure 3 to form a p ⁰ diffusion layer, and a strip process for removing the ion implantation mask (MK) after the ion implantation process The process is complicated by that.

Accordingly, the present invention has been made to solve the above problems, and can simplify the process and improve the Ioff (off current) and Bvdss (breakdown characteristic) of the NMOS transistor, and improve the Idsat (saturation current) of the PMOS transistor. It is an object of the present invention to provide a method for manufacturing a CMOS image sensor.

According to an aspect of the present invention, there is provided a substrate in which a first diffusion layer of a first conductivity type and a gate electrode are formed, and an ion implantation process is performed on a blanket without an ion implantation mask. Forming a second diffusion layer of a second conductivity type in the diffusion layer and the substrate exposed to both sides of the gate electrode, and forming an LDD region in an area exposed to both sides of the gate electrode among the regions where the second diffusion layer is formed Forming a spacer on both sidewalls of the gate electrode, forming a source and drain region deeper than the LDD region in a region corresponding to the LDD region, and forming a spacer in the region where the second diffusion layer is formed. It provides a method of manufacturing a CMOS image sensor comprising the step of forming a third diffusion layer of the second conductivity type.

The second diffusion layer is formed at a lower concentration than the third diffusion layer.

The ion implantation step is performed using a dose of 1.0E12 to 4.0E12 atoms / cm ² using BF ₂ .

The ion implantation process is carried out at 10 ~ 50 KeV ion implantation energy.

The spacer is formed by an etch back process.

The etch back process is performed so that the second diffusion layer is excessively etched to a predetermined depth.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

4A to 4G are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to an exemplary embodiment of the present invention. For convenience of description, only the photodiode PD, the transfer transistor Tx, the reset transistor Rx, and the drive transistor Dx are shown.

First, as shown in FIG. 4A, a p- epi layer 112 doped with a relatively low concentration of p-type impurities is formed on a p ++ substrate 111 doped with a high concentration of p-type impurities.

 Subsequently, an STI process is performed to form a device isolation trench (not shown), and a channel stop ion implantation process is performed to form a channel stop region (not shown) to form a device isolation film 113 having a trench embedded therein. . In this case, the device isolation layer 113 is formed of an HDP (High Density Plasma) oxide film or an epitaxially grown polysilicon film having excellent buried characteristics.

Subsequently, a well ion implantation process is performed to form the well region 114, and p-type or n-type impurities are selectively implanted to control the threshold voltage to form a p-type or n-type region (not shown).

Subsequently, gate electrodes 117a, 117b, and 117c of the transistors Tx, Rx, and Dx are formed. In this case, the gate electrodes 117a, 117b, and 117c are formed in a stacked structure of the gate insulating film 115 and the polysilicon film 116. In addition, a tungsten silicide layer may be further formed on the polysilicon layer 116.

Subsequently, as shown in FIG. 4B, an n-ion implantation process using an n-ion implantation mask (not shown) is performed to deep n- in the p-epi layer 112 exposed to one side of the transfer transistor Tx. The diffusion layer 118 is formed.

Subsequently, in order to compensate for the surface of the substrate 111 damaged by the plasma during the n-ion implantation process, a curing process is performed to grow an oxide film (not shown) on the surface of the substrate 111.

Then, an ion implantation p ⁰ diffusion layer 120 in the region exposed to both sides of the gate electrode (117a, 117b, 117c) to conduct the first p ⁰ ion implantation process 119, the wafer front side in block raengket (blanket) without a mask Form. At this time, the first p ⁰ ion implantation step 119 is performed at ion implantation energy of 10 to 50 KeV with a dose of 1.0E12 to 4.0E12 atoms / cm ² using BF ₂ .

Next, as shown in FIG. 4C, the LDD ion implantation process using an LDD ion implantation mask (not shown) is performed to place the LDD region 121 in the region exposed to both sides of the gate electrodes 117a, 117b, and 117c. Form.

Subsequently, as illustrated in FIG. 4D, the silicon oxide film 122 and the silicon nitride film 123 are sequentially deposited along the steps of the entire structure including the gate electrodes 117a, 117b, and 117c.

Subsequently, as shown in FIG. 4E, an etch back process 124 is performed to etch the silicon nitride film 123 and the silicon oxide film 122 to form both sidewalls of the gate electrodes 117a, 117b, and 117c. The spacer 125 is formed in the groove. At this time, the p ⁰ diffusion layer 120 and the LDD region 121 exposed during the etch back process 124 are excessively etched to a predetermined depth to form a profile similar to that of the same drawing. Here, the loss thickness T due to the excessive etching is 400 to 600 kPa, preferably 500 kPa.

Next, as shown in FIG. 4F, a source / drain ion implantation process is performed to form n + source / drain regions 126 at high concentration in regions exposed to both sides of the gate electrodes 117a, 117b, and 117c. In this case, the source / drain region 126 is deeper than the LDD region 121.

Subsequently, as illustrated in FIG. 4G, a p ⁰ ion implantation process using a second p ⁰ ion implantation mask (not shown) is performed to deeper the p ^o diffusion layer 126 in the n− diffusion layer 18 than the p ⁰ diffusion layer 120. ). At this time, the p ^o diffusion layer 126 is formed at a higher concentration than the p ^o diffusion layer 120.

Subsequently, a target temperature profile is diffused by performing a rapid temperature process (RTP) or a rapid temperature process (RTA) process to diffuse the p-type or n-type impurity ions implanted during the source / drain ion implantation process and the p ⁰ ion implantation process. which forms a source / drain region and the p-doped region ^0.

Subsequently, a general process is performed to complete the manufacturing process of the CMOS image sensor.

As described above, according to the present invention, the first p ⁰ ion implantation process 119 is carried out in a blanket without an ion implantation mask, so that not only the n-diffusion layer 118 but also both sides of the gate electrodes 117a, 117b, and 117c. By forming the p ⁰ diffusion layer 120 having a relatively low doping concentration in the exposed region, the parameters of the transistor may be improved as follows.

First, in the case of an NMOS transistor (NMOS TR), as shown in FIG. 5, the LDD region 121 is formed in the p− diffusion layer 120 with n− dose so that the region is [n −] + [p−]. Becomes As a result, a counter doping effect on n-LDD doses can be obtained, and Idsat is slightly degraded in parameters, but Ioff is reduced and Bvdss is greatly improved to improve punch through characteristics. have. In particular, the effect is greater in native transistors formed in the p-epi layer than normal transistors formed in the p-well.

On the other hand, in the case of the PMOS transistor PMOS TR, as shown in FIG. 6, the LDD region 121 is formed in the p-diffusion layer 120 with p-dose, thereby forming [p-] + [p-]. Becomes Accordingly, the p-LDD region may be strengthened and Idsat (or current driving characteristics) among parameters may be improved, but there is a possibility of deterioration of Ioff or Bvdss characteristics. However, since no PMOS transistor is formed in the unit pixel region, there is no adverse effect on optical characteristics.

In addition, according to the present invention, since the first p ⁰ ion implantation process 119 is performed with a blanket without an ion implantation mask, a separate photo process and a strip process may be skipped, thereby simplifying the process.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the first p ⁰ ion implantation process before the LDD ion implantation process is performed with a blanket without an ion implantation mask to improve the Ioff and Bvdss characteristics of the normal NMOS transistor or the native NMOS transistor, Idsat (or current drive characteristics) of the transistor can be improved. In addition, the photo process and the strip process can be skipped, thereby simplifying the process and reducing the cost.

Claims (7)

Providing a substrate on which a first diffusion layer of a first conductivity type and a gate electrode are formed; Performing an ion implantation process with a blanket without an ion implantation mask to form a second diffusion layer of a second conductivity type in the substrate exposed to both sides of the first diffusion layer and the gate electrode; Forming a lightly doped drain (LDD) region in the region in which the second diffusion layer is formed and exposed to both sides of the gate electrode; Forming spacers on both sidewalls of the gate electrode; Forming a source and drain region deeper than the LDD region in a region corresponding to the LDD region; And Forming a third diffusion layer of the second conductivity type in a region where the first diffusion layer is formed at a higher concentration than the second diffusion layer; Method of manufacturing a CMOS image sensor comprising a. delete The method of claim 1, The ion implantation process is a method of manufacturing a CMOS image sensor is carried out using a dose of 1.0E12 ~ 4.0E12 atoms / cm ² using BF ₂ . The method of claim 3, wherein The ion implantation process of the CMOS image sensor is carried out at 10 ~ 50 KeV ion implantation energy. The method of claim 3, wherein The spacer is a method of manufacturing a CMOS image sensor formed by an etch back process. delete The method of claim 5, The second diffusion layer is a method of manufacturing a CMOS image sensor is over-etched so as to be lost to a thickness of 400 ~ 600Å by the etch back process.

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