KR20030057710A - CMOS Image sensor for sensitivity improvement and method for fabricating the same - Google Patents

Abstract

PURPOSE: A CMOS image sensor and a method for manufacturing the same are provided to be capable of reducing parasitic capacitance of a floating diffusion region and improving sensitivity and saturation level. CONSTITUTION: An n- diffusion layer(36) is formed in a p- epitaxial layer(32). A gate electrode(34) is formed on the p- epitaxial layer(32) while aligning one edge thereof to one edge of the n- diffusion layer(36). A spacer(38) is formed at both sidewalls of the gate electrode. A p0 diffusion layer(39) is formed in the n- diffusion layer(36) to align one edge of the spacer(38). An n- VLDD(Very Lightly Doped Drain)(37) having the same depth to the n- diffusion layer(36) is formed in the epitaxial layer to align the other edge of the gate electrode. An n+ source/drain(40) having a relatively deep depth compared to the n- VLDD is formed in the epitaxial layer to contact the n- VLDD(37). Charge transfers from the n- diffusion layer(36) to the source/drain(40) via the n- VLDD(37).

Description

CMOS image sensor for sensitivity improvement and method for fabricating the same

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a CMOS image sensor.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal, and a charge coupled device (CCD) is located at a position where individual metal-oxide-silicon (MOS) capacitors are very close to each other. Charge carriers are stored and transported in capacitors, and CMOS image sensors use CMOS technology that uses control circuits and signal processing circuits as peripheral circuits. It is a device that adopts a switching method that makes transistors and sequentially detects output using them.

The image sensor has a color filter arranged on the upper part of the light sensing portion that receives and receives the light from the outside to generate and accumulate photocharges. The color filter array (CFA) is red, green, and It consists of three colors of Blue, or three colors of Yellow, Magenta, and Cyan.

In addition, the image sensor is composed of a light sensing part for detecting light and a logic circuit part for processing the detected light as an electrical signal to make data. The ratio of the area of the light sensing part to the overall image sensor element is increased to increase the light sensitivity. Efforts are being made to increase the fill factor, but these efforts are limited in a limited area because the logic circuit part cannot be removed.

Therefore, in order to increase the light sensitivity, a light converging technology has emerged that changes the path of light incident to the area other than the light sensing part and collects the light into the light sensing part. For this purpose, the image sensor uses a microlens on the color filter. The method of forming is used.

1 is an equivalent circuit diagram illustrating a unit pixel of a conventional CMOS image sensor.

Referring to FIG. 1, one photodiode (PD) and four NMOSs (Tx, Rx, Sx, and Dx) are configured, and four NMOSs (Tx, Rx, Sx, and Dx) are photodiodes (PD). Transfer transistor (Tx) for transporting the photo-generated charge to Floating Diffusion (FD), set the potential of the node to the desired value and charge (C _pd ) A reset transistor (Rx), a drive transistor (Dx) serving as a source follower buffer amplifier (Source transistor) to reset the floating diffusion region (FD) by discharge. It consists of a select transistor (Sx) that allows addressing (Addressing).

Here, the transfer transistor (Tx) and the reset transistor (Rx) use a native transistor (Native NMOS), the drive transistor (Dx) and the select transistor (Sx) use a common transistor (Normal NMOS), and the reset transistor (Rx) A transistor for correlated double sampling (CDS).

The unit pixel of the CMOS image sensor flows the detected photogenerated charge after detecting the light of the visible wavelength band in the photodiode region PD using a native transistor. The amount transferred to the TD diffusion region FD, that is, the gate of the drive transistor Dx, is output as an electrical signal at the output terminal Vout.

2 is a device cross-sectional view of a CMOS image sensor manufactured according to the prior art.

2, a method of manufacturing an image sensor will be briefly described. First, a p- epi layer 12 doped with a low concentration p-type impurity is grown on a p ⁺ -substrate 11 doped with a high concentration of p-type impurity. After that, a field oxide film 13 for inter-unit pixel isolation is formed in a predetermined portion of the p-epi layer 12 by LOCOS (Local oxidation of silicon) method.

Next, the p-well 14 is formed in a predetermined region of the p-epi layer 12 so as to contain the drive gate Dx and the select gate Sx through lateral diffusion by a subsequent thermal process.

Next, the gate electrodes 15a and 15b of the drive transistor Dx and the select transistor Sx are formed on the p-well 14, and the transfer transistor Tx and the reset are formed on the p-epi layer 12. Gate electrodes 15c and 15d of the transistor Rx are formed. At this time, the gate electrodes 15a, 15b, 15c, and 15d of the four transistors are in the form of polyside electrodes made of polysilicon and tungsten silicide films.

Next, ion implantation of low concentration n-type impurity n ^_ at high energy into one p-epi layer 12 of the gate electrode 15c of the transfer transistor Tx among the gate electrodes 15a, 15b, 15c, and 15d is performed. the deep n ^_ - to form a ^{- (diffusion region deep n) (} 16) diffusion layer.

Next, after ion implanting impurities having a dose amount of about 10 ¹⁹ to 10 ²⁰ to form a lightly doped drain (LDD) structure 17 of the drive transistor Dx and the select transistor Sx, the spacer is formed on the front surface of the spacer. After the deposition of the insulating film for deposition, the entire surface of the insulating film is etched to form a spacer 18 in contact with both side walls of the four gate electrodes 15a, 15b, 15c, and 15d.

On top of the diffusion layer (16) p ^o - - Next, a blanket (blanket) by ion implantation to form low-energy p impurity (p ^o) in the ion implantation near the surface of the p- epitaxial layer 12 and n diffusion layers ^_ (19 ). At this time, n ^_ - ^o p which is formed in the diffusion layer 16-diffusion layer 19 is isolated by the thickness of the spacer 17.

Through the implantation of the p-type impurity described above, a shallow pn junction formed of the p ^o -diffusion layer 19 and the n ^_ -diffusion layer 16 is formed, and the p-epi layer 12 / n ^_ -diffusion layer ( A pnp type photodiode consisting of 16) / p ^o -diffusion layer 19 is formed.

Next, a high concentration impurity ion implantation step for forming the source / drain and the floating diffusion regions 20 and 21 is performed. In other words, floating D, which is a common connection terminal of two common NMOS transistors, a source transistor / drain 20 of a drive transistor Dx and a select transistor Sx, and two native NMOS transistors, a transfer transistor Tx and a reset transistor Rx. The fusion region 21 and one source / drain 20 of the reset transistor are formed.

Referring to FIG. 2 described above, the conventional transfer transistor Tx prevents deterioration of sensitivity and saturation characteristics of the image sensor due to an increase in charge transfer characteristics and capacitance of the floating diffusion region 21. Unlike the drive transistor Dx and the select transistor Sx, a source / drain 20 having a single n ⁺ -diffusion layer structure that does not basically adopt a lightly doped drain (LDD) structure is provided.

However, since the single n ⁺ -diffusion layer structure does not generate overlap between the gate electrode 15c and the floating diffusion region 21 of the transfer transistor, the parasitic capacitance is reduced and the charge-voltage conversion factor of the floating diffusion region 21 is reduced. ) May be sufficiently large, but the transmission characteristics from the photodiode PD to the floating diffusion region 21 are deteriorated.

On the other hand, in the case of the floating diffusion region of the LDD structure, the parasitic capacitance between the gate and the floating diffusion region of the transfer transistor is large, so that the charge-voltage change factor of the floating diffusion region is small and thus the sensitivity is inferior.

In particular, the sensitivity loss of an image sensor is becoming more and more deteriorated in recent years when the size of unit pixels is reduced, and a method for overcoming this is required.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and an object thereof is to provide an image sensor suitable for reducing the capacitance between the transfer gate and the floating diffusion region, and improving the sensitivity and the saturation level.

1 is an equivalent circuit diagram of a general CMOS image sensor;

2 is a device cross-sectional view showing a CMOS image sensor according to the prior art;

3 is a device cross-sectional view showing a CMOS image sensor according to an embodiment of the present invention;

4A to 4C are cross-sectional views illustrating a method of manufacturing the CMOS image sensor shown in FIG. 3.

* Explanation of symbols for the main parts of the drawings

31: p ⁺ -substrate 32: p- epi layer

33: field oxide film 34: gate electrode

35: ion implantation mask 36: n ^_ -diffusion layer

37: n ^- VLDD 38 spacer

39: p ^o -Diffusion layer 40: n ⁺ -Source / drain

The CMOS image sensor of the present invention for achieving the above object is the first conductive semiconductor layer, the second conductive type first diffusion layer formed inside the semiconductor layer, while one side edge is aligned with one side edge of the first diffusion layer A gate electrode formed on the semiconductor layer, a spacer formed on both side walls of the gate electrode, a first conductive type second diffusion layer formed in the first diffusion layer near the surface of the semiconductor layer by a width of the spacer, and the other side of the gate electrode A third conductive type diffusion layer formed in the semiconductor layer at the same depth as the first diffusion layer while being aligned at an edge, and in contact with the third diffusion layer and aligned with the spacer and having a depth deeper than the third diffusion layer in the semiconductor layer. Including the formed second conductive diffusion layer, a complete depletion in the first diffusion layer, the first diffusion layer from the 3 through the diffusion layer is characterized in that the charge is transferred to said fourth diffusion layer.

The present invention provides a method of manufacturing a CMOS image sensor, comprising: forming a gate electrode on a first conductive semiconductor layer, a second conductive first diffusion layer aligned with one edge of the gate electrode in the semiconductor layer, and the gate Simultaneously forming a second conductive diffusion layer aligned with the other edge of the electrode; forming a spacer in contact with both sidewalls of the gate electrode; and forming a first conductive layer in the first diffusion layer at a distance equal to the width of the spacer. Forming a third type diffusion layer, and forming a second conductive type fourth diffusion layer in contact with the second diffusion layer while being aligned with the spacer on the second diffusion layer in the semiconductor layer.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3 is a device cross-sectional view of a CMOS image sensor according to an exemplary embodiment of the present invention.

As shown in Fig. 3, p ⁺ - in the interior of the p- epitaxial layer 32 is grown on the semiconductor substrate (31) n ^{- -} diffusion layer 36 is formed, p- epi layer 32 near the surface A p ^o -diffusion layer 39 is formed in the n ^-- diffusion layer 36.

Here, the p-epitaxial layer 32, the n ⁻ -diffusion layer 36, and the p ^o -diffusion layer 39 form a photodiode PD having a pnp structure.

Then, the gate electrode 34 is formed on the p-epitaxial layer 32 while the one edge is aligned with one edge of the n ⁻ − diffusion layer 36, and spacers 38 are formed on both sidewalls of the gate electrode.

Here, the gate electrode 34 is a gate electrode of the transfer transistor.

Then, n ⁻ -VLDD 37 is formed in the p- epi layer 32 having the same depth and concentration as the n ⁻ − diffusion layer 36 while being aligned with the other edge of the gate electrode 34, and the spacer 38. N ⁺ -source / drain 40 is formed in p-epitaxial layer 32 in contact with n ⁻ -VLDD 37 while being aligned with.

Here, n ⁺ - depth of the source / drain 40 is n ^- - diffusion layer 36 and the n ^- more than -VLDD (37) deep, the concentration of the impurities also higher.

On the other hand, n ⁺ -source / drain 40 in contact with n ^-- VLDD 37 forms a floating diffusion region FD.

4A to 4C are cross-sectional views illustrating a method of manufacturing the CMOS image sensor shown in FIG. 3.

As shown in FIG. 4A, a p- epi layer 32 doped with a low concentration p-type impurity is grown on a p ⁺ -substrate 31 doped with a high concentration of p-type impurity, followed by a p- epi layer 32. A field oxide film 33 for inter-unit pixel isolation is formed in a predetermined portion of the?

Next, the gate electrode 34 (hereinafter, abbreviated as 'gate electrode 34') of the transfer transistor Tx and the reset transistor Rx is formed on the p-epitaxial layer 32. At this time, although not shown in the drawings, the gate electrodes of the drive transistors Dx and the select transistor Sx are also formed at the same time, and the gate electrodes of these transistors have a polyside electrode type made of polysilicon and a tungsten silicide film.

Next, impurities are implanted with impurities having a dose amount of about 10 ¹⁹ to 10 ²⁰ for forming LDD (not shown) of the drive transistor Dx and the select transistor Sx.

Next, an ion implantation mask is applied to the entire surface including the gate electrode 34 and patterned by exposure and development to cover the entire region of the semiconductor substrate 31 except for the photodiode PD and the floating diffusion region FD. (35) is formed.

At this time, the ion implantation mask 35 is conventionally achieved a photodiode n ^- - by modifying an ion implantation mask for forming a diffusion layer (revision) are formed with no additional masking process.

Next, a photodiode PD aligned with one side of the gate electrode 24 by ion implanting a low concentration n-type impurity n ^_ at a high energy into the p-epi layer 22 exposed by the ion implantation mask 25. ) to achieve n ^_ - forms a -VLDD (Very Low Doped Drain) (37) at the same ^{time-diffusion} layer 36 and the gate electrode 34, the floating diffusion region (FD) n fulfill is aligned with the other side of.

At this time, when the low concentration n-type impurity (n ⁻ ) is ion-implanted, the impurity concentration is 10 ¹⁵ to 10 ^{17 or} less, which is lower than the ion implantation concentration of the n-type impurity for forming the LDD region which is commonly performed.

As shown in FIG. 4B, after the ion implantation mask 35 is removed, a spacer insulating film is deposited on the entire surface, and then the insulating film is etched entirely to form spacers 38 contacting both sidewalls of the gate electrode 34. .

Subsequently, a blanket ion implantation to the p-type impurity in a low energy (p ^o), the ion implantation to p- epitaxial layer 32 near the surface of the n ^_ - forming a diffusion layer (39) - p ^o on the upper portion of the diffusion layer 36 do. At this time, the p ^o -diffusion layer 39 formed in the n ^_ -diffusion layer 36 is separated by the thickness of the spacer 37.

Through the ion implantation of p-type impurities, the above-described ^o p - diffusion layers 39 and n ^_ - form a shallow pn junction formed of a diffusion layer 36, p- epitaxial layer (32) / ^_ n - diffusion layer 36 / A pnp type photodiode consisting of a p ^o -diffusion layer 39 is formed.

As shown in FIG. 4C, an ion implantation process is performed to form n ⁺ -source / drain 40 to form the floating diffusion region FD. That is, an ion implantation mask (not shown) covering the photodiode is formed by applying a photoresist film to the entire surface on which the photodiode is formed and patterning by exposure and development, and then exposing it to the other side of the gate electrode 34 exposed by the ion implantation mask. to form a source / drain (40), - the ion-implanted at a high concentration n ⁺ impurities in the p- epitaxial layer 32 and n ⁺ is aligned with the spacer 37.

As a result, the floating diffusion region FD is composed of n ⁻ -VLDD 37 and n ⁺ − source / drain 40.

According to the embodiment described above, since the floating diffusion region has n ⁻ -VLDD 37, the transmission efficiency is improved, and the overlap capacitance between the gate electrode 34 and the floating diffusion region FD of the transfer transistor is reduced. The parasitic capacitance of the floating diffusion region FD is reduced.

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

The present invention as described above has the effect of improving the transfer efficiency from the photodiode to the floating diffusion region by forming the VLDD structure by ion implantation on the floating diffusion region side.

In addition, since the parasitic capacitance is reduced by generating an overlap between the gate electrode and the floating diffusion region of the transfer transistor, the charge-voltage conversion factor of the floating diffusion region can be increased, thereby improving sensitivity.

Claims (9)

A first conductive semiconductor layer; A second conductive type first diffusion layer formed in the semiconductor layer; A gate electrode formed on the semiconductor layer with one edge aligned with one edge of the first diffusion layer; Spacers formed on both sidewalls of the gate electrode; A first conductive type diffusion layer spaced apart by a width of the spacer and formed in the first diffusion layer near the surface of the semiconductor layer; A second conductive type diffusion layer aligned in the other edge of the gate electrode and formed in the semiconductor layer to the same depth as the first diffusion layer; And A second conductive type diffusion layer formed in the semiconductor layer while being aligned with the spacer and in contact with the third diffusion layer and having a depth deeper than that of the third diffusion layer, Complete depletion is performed in the first diffusion layer, and charge is transferred from the first diffusion layer to the fourth diffusion layer through the third diffusion layer. The method of claim 1, And the first diffusion layer and the third diffusion layer have the same concentration. The method of claim 1, And the fourth diffusion layer has a higher concentration than the first diffusion layer and the third diffusion layer. Forming a gate electrode on the first conductive semiconductor layer; Simultaneously forming a second conductive diffusion layer aligned with one edge of the gate electrode and a second conductive diffusion layer aligned with the other edge of the gate electrode in the semiconductor layer; Forming a spacer in contact with both sidewalls of the gate electrode; Forming a first conductive type third diffusion layer in the first diffusion layer at a distance of the spacer; And Forming a second conductive fourth diffusion layer in the semiconductor layer in contact with the second diffusion layer while being aligned with the spacer on the second diffusion layer Manufacturing method of the CMOS image sensor characterized in that comprises a. The method of claim 4, wherein In the step of forming the first diffusion layer and the second diffusion layer at the same time, The first diffusion layer and the second diffusion layer is a manufacturing method of the CMOS image sensor, characterized in that formed in the same depth. The method of claim 4, wherein And the fourth diffusion layer is formed deeper than the first diffusion layer and the second diffusion layer. The method of claim 4, wherein Simultaneously forming the first diffusion layer and the second diffusion layer, Forming a first mask exposing the gate electrode and a surface of the semiconductor layer on both sides of the gate electrode; And Implanting a second conductive impurity onto the surface of the semiconductor layer using the first mask and the gate electrode as an ion implantation mask Manufacturing method of the CMOS image sensor characterized in that comprises a. The method of claim 4, wherein Forming the fourth diffusion layer, Forming a second mask covering the first diffusion layer and the gate electrode and exposing a surface of the second diffusion layer; And Implanting a second conductive impurity into the exposed second diffusion layer surface using the second mask as an ion implantation mask Manufacturing method of the CMOS image sensor characterized in that comprises a. The method of claim 4, wherein The impurity concentration of the fourth diffusion layer is a manufacturing method of the CMOS image sensor, characterized in that the relatively higher than the first diffusion layer and the second diffusion layer.