KR20030056099A - A fabricating method of image sensor with improved high intergation - Google Patents
A fabricating method of image sensor with improved high intergation Download PDFInfo
- Publication number
- KR20030056099A KR20030056099A KR1020010086260A KR20010086260A KR20030056099A KR 20030056099 A KR20030056099 A KR 20030056099A KR 1020010086260 A KR1020010086260 A KR 1020010086260A KR 20010086260 A KR20010086260 A KR 20010086260A KR 20030056099 A KR20030056099 A KR 20030056099A
- Authority
- KR
- South Korea
- Prior art keywords
- region
- image sensor
- semiconductor layer
- forming
- device isolation
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 239000012535 impurity Substances 0.000 claims abstract description 21
- 238000002955 isolation Methods 0.000 claims abstract description 19
- 230000002093 peripheral effect Effects 0.000 claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 230000000452 restraining effect Effects 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241000293849 Cordylanthus Species 0.000 description 1
- 206010034960 Photophobia Diseases 0.000 description 1
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 208000013469 light sensitivity Diseases 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
본 발명은 반도체 소자에 관한 것으로 특히, 이미지센서 제조 방법에 관한 것으로, 더욱 상세하게는 고집적이 용이하고 색재현성이 향상된 이미지센서 제조 방법에 관한 것이다.The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing an image sensor, and more particularly, to a method of manufacturing an image sensor having high integration and improved color reproducibility.
일반적으로, 이미지센서라 함은 광학 영상(Optical image)을 전기 신호로 변환시키는 반도체소자로서, 이중 전하결합소자(CCD : Charge Coupled Device)는 개개의 MOS(Metal-Oxide-Silicon) 커패시터가 서로 매우 근접한 위치에 있으면서 전하 캐리어가 커패시터에 저장되고 이송되는 소자이며, CMOS(Complementary MOS; 이하 CMOS) 이미지센서는 제어회로(Control circuit) 및 신호처리회로(Signal processing circuit)를 주변회로로 사용하는 CMOS 기술을 이용하여 화소수만큼 MOS트랜지스터를 만들고 이것을 이용하여 차례차례 출력(Output)을 검출하는 스위칭 방식을 채용하는 소자이다.In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal. In a double charge coupled device (CCD), individual metal-oxide-silicon (MOS) capacitors are very different from each other. A device in which charge carriers are stored and transported in a capacitor while being located in close proximity, and CMOS (Complementary MOS) image sensor is a CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits. Is a device that employs a switching method that creates MOS transistors by the number of pixels and sequentially detects the output using them.
이러한 다양한 이미지센서를 제조함에 있어서, 이미지센서의 감광도(Photo sensitivity)를 증가시키기 위한 노력들이 진행되고 있는 바, 그 중 하나가 집광기술이다. 예컨대, CMOS 이미지센서는 빛을 감지하는 포토다이오드와 감지된 빛을 전기적 신호로 처리하여 데이터화하는 CMOS 로직회로부분으로 구성되어 있는 바, 광감도를 높이기 위해서는 전체 이미지센서 면적에서 포토다이오드의 면적이 차지하는 비율(이를 통상 Fill Factor"라 한다)을 크게 하려는 노력이 진행되고 있다.In the manufacture of such various image sensors, efforts are being made to increase the photo sensitivity of the image sensor, one of which is a condensing technology. For example, a CMOS image sensor is composed of a photodiode for detecting light and a portion of a CMOS logic circuit for processing the detected light into an electrical signal to make data. To increase light sensitivity, the ratio of the photodiode to the total image sensor area is increased. Efforts have been made to increase (usually referred to as Fill Factor).
도 1은 통상적인 트렌치(Trench)형 필드 절연막을 갖는 이미지센서의 개략도를 도시하는 바, 여기서 A-A'은 화소어레이영역을 도시하며, B-B'은 주변회로영역을 도시한다.Fig. 1 shows a schematic view of an image sensor having a conventional trench type field insulating film, where A-A 'shows a pixel array region and B-B' shows a peripheral circuit region.
도 1을 참조하면, 통상적인 이미지센서에서 고농도인 P++ 층(10) 및 P-Epi층(11)이 적층된 반도체층을 이용하는 바, 이하 P++ 층(10) 및 P-Epi층(11)을 반도체층으로 칭한다.Referring to FIG. 1, a semiconductor layer in which a high concentration of P ++ layer 10 and P-Epi layer 11 are stacked in a conventional image sensor is described below. P ++ layer 10 and P-Epi layer 11 It is called a semiconductor layer.
반도체층에 국부적으로 트렌치형 필드절연막(12, Fox)이 형성되어 있으며, 필드절연막(12)과 떨어진 영역에 게이트절연막(13)과 게이트전극용 전도막(14) 및 스페이서(15)로 이루어진 게이트전극 예컨대, 화소어레이영역(A-A')에서는 트랜스퍼 게이트(Transfer gate, 이하 Tx라 함), 주변회로영역(B-B')에서는 P웰(21, P-Well)과 N웰(22, N-Well) 상에 각각 엔모스 트랜지스터(NMOS, 이하 NMOS라 함)와 피모스 트랜지스터(PMOS, 이하 PMOS라 함)가 형성되어 있다.Trench type field insulating films 12 and Fox are formed locally in the semiconductor layer, and the gate insulating film 13 and the gate electrode conductive film 14 and the spacer 15 are located in a region away from the field insulating film 12. In the pixel array region A-A ', for example, a transfer gate (hereinafter referred to as Tx) and a peripheral circuit region B-B', the P wells 21 (P-Well) and the N wells 22, NMOS transistors (NMOS, hereinafter referred to as NMOS) and PMOS transistors (PMOS, hereinafter referred to as PMOS) are formed on the N-Well, respectively.
Tx와 필드절연막(12)에 접하면서 반도체층 내부에 소정의 깊이로 형성된 포토다이오드용 N형 불순물 영역(이하 n-영역이라 함, 16)과 n-영역(16) 상부의 반도체층과 접하는 계면에 얕은 포토다이오드용 P형 불순물 영역(이하 P0영역이라 함, 17)이 배치되어 있으며, 고농도 N형 불순물 영역인 센싱확산영역(이하 FD라 함, 18)이 배치되어 있으며, NMOS와 PMOS는 각각 n+(19)와 P+(20)의 소스/드레인 불순물 영역을 구비하고 있다.An interface between the N-type impurity region for photodiode (hereinafter referred to as n-region 16) formed in the semiconductor layer at a predetermined depth in contact with Tx and the field insulating film 12 and the semiconductor layer over the n-region 16 P-type impurity regions (hereinafter referred to as P0 regions, 17) for shallow photodiodes are arranged on the substrate, and a sensing diffusion region (hereinafter referred to as FD, 18), which is a highly concentrated N-type impurity region, is disposed. Source / drain impurity regions of n + (19) and P + (20) are provided.
한편, 전술한 종래의 이미지센서는 필드절연막(12)이 단순 트렌치 형으로 되어 있어 LOCOS(LOCal Oxidation of Silicon) 방법에서의 버즈비크(Bird's beak) 부분만 확장하는 포토다이오드 형태를 취하고 있으며, 고집적화를 위해 종래의 LOCOS 방법보다는 STI로 필트절연막(12)을 형성하고 있다.On the other hand, the conventional image sensor described above takes the form of a photodiode in which the field insulating film 12 is a simple trench type and extends only a Bird's beak portion in the LOCOS method. For this reason, the filter insulating film 12 is formed of STI rather than the conventional LOCOS method.
그러나, STI의 경우 트렌치의 깊이가 0.5㎛ 이하로 얕고, 종래의 LOCOS 방식보다 STI 계면에서의 트렌치 식각에 의해 실리콘 격자가 많은 데미지를 받는 공정 상의 특징으로 인해, 데미지를 받은 실리콘 격자의 결함으로부터 잉여 전자가 포획(Trap)되어 이미지센서의 특성 열화의 대표적인 암신호를 발생시키게 된다.However, in the case of STI, the depth of the trench is shallow to 0.5 μm or less, and due to a process characteristic in which the silicon lattice is damaged by the trench etching at the STI interface more than the conventional LOCOS method, surplus from the defect of the damaged silicon lattice The electrons are trapped to generate a representative dark signal of deterioration of the characteristics of the image sensor.
상기와 같은 종래 기술의 문제점을 해결하기 위해 제안된 본 발명은, 필드절연막 형성에 따른 실리콘 격자 디스로케이션(Dislocation)에 따른 암신호 발생을 억제하기에 적합한 이미지센서 제조 방법을 제공하는데 그 목적이 있다.The present invention proposed to solve the problems of the prior art as described above, an object of the present invention is to provide a method for manufacturing an image sensor suitable for suppressing the generation of a dark signal due to silicon lattice dislocation (Dislocation) due to the formation of the field insulating film. .
도 1은 통상적인 트렌치형 필드절연막을 갖는 이미지센서의 개략도,1 is a schematic diagram of an image sensor having a conventional trench type field insulating film,
도 2a 내지 도 2c는 본 발명의 일실시예에 따른 이미지센서 제조 공정을 도시한 단면도.2A to 2C are cross-sectional views illustrating an image sensor manufacturing process according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
30 : 반도체층31 : 필드절연막30 semiconductor layer 31 field insulating film
33 : 소자분리영역34a : P웰33: device isolation region 34a: P well
34b : N웰35 : 게이트절연막34b: N well 35: gate insulating film
36 : 게이트전극용 전도막37 : 포토다이오드용 n-영역36 conductive film for gate electrode 37 n-region for photodiode
38 : 스페이서39 : 포토다이오드용 P0영역38: spacer 39: P0 area for photodiode
40 : 센싱확산영역41, 42 : 소스/드레인40: sensing diffusion area 41, 42: source / drain
상기 목적을 달성하기 위하여 본 발명은, 화소어레이영역과 주변회로영역을 구비하는 이미지센서 제조 방법에 있어서, P형 불순물 이온주입을 통해 상기 화소어레이영역의 반도체층 하부에 국부적으로 소자분리영역을 형성하는 단계; 상기 반도체층 상에 게이트전극을 형성하는 단계; 및 상기 게이트전극과 상기 필드절연막 사이의 상기 반도체층에 포토다이오드를 형성하는 단계를 포함하는 이미지센서 제조 방법을 제공한다.In order to achieve the above object, the present invention provides a method for fabricating an image sensor having a pixel array region and a peripheral circuit region, wherein a device isolation region is locally formed under a semiconductor layer of the pixel array region through p-type impurity ion implantation. Doing; Forming a gate electrode on the semiconductor layer; And forming a photodiode in the semiconductor layer between the gate electrode and the field insulating layer.
본 발명은, 전술한 바와 같이 원하지 않는 전자들이 STI 계면의 실리콘 격자의 결함부분에 포획되는 것을 원천적으로 방지하기 위해 주변회로영역은 필드절연막 형성은 종래와 동일하게 하고, 화소어레이영역은 세단계에 의한 고에너지 이온주입을 통해 종래의 필드절연막 구조보다 깊고 실리콘 격자의 디스로케이션이 최소로 발생하도록 고농도 P형 불순물에 의한 필드절연막을 형성하여 암신호 발생을 억제하는 것을 기술적 특징으로 한다.As described above, in order to prevent unwanted electrons from being trapped in the defect portion of the silicon lattice at the STI interface, the peripheral circuit area is made the same as the conventional field insulating film formation, and the pixel array area is formed in three steps. It is a technical feature to suppress the generation of a dark signal by forming a field insulating film with a high concentration of P-type impurities so that deeper than a conventional field insulating film structure through the high-energy ion implantation by the silicon oxide, and the dislocation of the silicon lattice is minimized.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부한 도면을 참조하여 설명하는 바, 도 2a 내지 도 2c는 본 발명의 일실시예에 따른 이미지센서 제조 공정을 도시한 단면도이다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. 2A to 2C are cross-sectional views illustrating an image sensor manufacturing process according to an embodiment of the present invention.
먼저 도 2a에 도시된 바와 같이, 화소어레이영역(A-A')과 주변회로영역(B-B')으로 구분되는 반도체층(30)의 주변회로영역(B-B')에 필드절연막(31)을 형성하는 바, 도면에 도시된 바와 같이 STI 구조 또는 LOCOS 구조로 형성한다.First, as shown in FIG. 2A, the field insulating layer (B-B ') is formed in the peripheral circuit region B-B' of the semiconductor layer 30 divided into the pixel array region A-A 'and the peripheral circuit region B-B'. 31) is formed in the STI structure or LOCOS structure as shown in the figure.
다음으로, 도 2b에 도시된 바와 같이 화소어레이영역(A-A')에서의 소자분리를 위한 이온주입마스크(32)를 형성한 다음, 이온주입 마스크(32)에 얼라인되도록 반도체층(30) 내부에 P형 예컨대, 붕소(B) 등의 불순불을 이온주입하여 국부적으로 소자분리영역(33)을 형성한다.Next, as shown in FIG. 2B, the ion implantation mask 32 for device isolation in the pixel array region A-A 'is formed, and then the semiconductor layer 30 is aligned with the ion implantation mask 32. The ion isolation region 33 is locally formed by ion implantation of impurity such as P type, for example, boron (B).
여기서, 상부에서의 반도체층(30)과의 접촉 계면을 줄이기 위해 좁고 깊은 소자분리영역(33)을 형성하기 위해 세번의 이온주입 단계를 거쳐 실시하는 바, 이 때 각각의 도즈량과 이온주입 에너지를 달리한다.Here, three doses of ion implantation are performed to form a narrow and deep device isolation region 33 in order to reduce the contact interface with the semiconductor layer 30 in the upper portion. To be different.
구체적으로, 먼저 1.0E11/㎠ ∼ 3.0E13/㎠의 비교적 고농도의 불순물을500KeV ∼ 1MeV의 고에너지를 이용하여 깊게 형성하는 바, 이 때 2.0㎛ ∼ 4.0㎛ 정도의 깊이까지 P형의 고농도 불순물영역이 형성된다.Specifically, first, a relatively high concentration of impurities of 1.0E11 / cm2 to 3.0E13 / cm2 is formed deep by using a high energy of 500 KeV to 1MeV. Is formed.
이어서, 1.0E10/㎠ ∼ 1.0E12/㎠의 불순물을 150KeV ∼ 250KeV의 에너지를 이용하여 이온주입한 다음, 1.0E10/㎠ ∼ 1.0E12/㎠의 불순물을 20KeV ∼ 80KeV의 비교적 저에너지를 이용하여 이온주입하는 바, 좁고 깊으면서도 세번의 이온주입에 따라 그 내부의 농도분포가 비교적 균일한 P+의 소자분리영역(33)을 형성한다.Subsequently, ion implantation of impurities of 1.0E10 / cm 2 to 1.0E12 / cm 2 was carried out using energy of 150KeV to 250KeV, and then ion implantation of impurities of 1.0E10 / cm 2 to 1.0E12 / cm 2 using relatively low energy of 20KeV to 80KeV. As a result, a narrow, deep and three ion implantation forms a P + device isolation region 33 having a relatively uniform concentration distribution therein.
여기서, P형 불순물을 화소어레이영역에서의 소자분리영역(33)에 사용한 것은 화소어레이영역의 트렌지스터는 모두 엔모스 트랜지스터이기 때문이다.The P-type impurity is used for the element isolation region 33 in the pixel array region because all transistors in the pixel array region are NMOS transistors.
한편, 본 발명에서는 세번의 이온주입을 실시하였으나, 한번 내지 두번 또는 그 이상의 횟수로도 가능하다.On the other hand, in the present invention, three ion implantation was performed, but may be performed once or twice or more times.
따라서, 화소어레이영역에서의 소자분리영역을 이온주입을 통해 형성함으로써 더 좁고 깊게 형성할 수 있어, 전술한 암신호 발생을 억제할 수 있으며, 고직접화에 부응할 수 있음과 동시에 크로스토크(Crosstalk) 방지 및 저조도 특성을 향상시킬 수 있다.Therefore, by forming the device isolation region in the pixel array region through ion implantation, it is possible to form a narrower and deeper, thereby suppressing the above-described dark signal generation, can meet the high direct and crosstalk (Crosstalk) A) Prevention and low light characteristics can be improved.
이어서, 일련의 포토다이오드(PD)와 주변회로영역에서의 엔모스 트랜지스터(NMOS) 등의 형성 공정을 실시하는 바, 이는 통상적인 공정을 통해 형성한다.Subsequently, a process of forming a series of photodiodes PD and an NMOS transistor (NMOS) in the peripheral circuit region is performed, which is formed through a conventional process.
따라서, 2c에 도시된 바와 같은 이미지센서가 형성되는바, 도 2c를 참조하면, 주변회로영역의 반도체층(30)에 국부적으로 트렌치형 필드절연막(31)이 형성되어 있으며, 화소어레이영역에는 이온주입에 위한 P형의 소자분리영역(33)이 국부적으로 형성되어 있으며, 소자분리영역(33)과 떨어진 영역에 게이트절연막(35)과 게이트전극용 전도막(36) 및 스페이서(38)로 이루어진 게이트전극 예컨대, 화소어레이영역(A-A')에서는 트랜스퍼 게이트(Tx), 주변회로영역(B-B')에서는 P웰(34a, P-Well)과 N웰(234b, N-Well) 상에 각각 엔모스 트랜지스터(NMOS)와 피모스 트랜지스터(PMOS)가 형성되어 있다.Therefore, as shown in FIG. 2C, an image sensor is formed. Referring to FIG. 2C, a trench type field insulating layer 31 is locally formed in the semiconductor layer 30 of the peripheral circuit region, and ions are formed in the pixel array region. A P-type device isolation region 33 for implantation is locally formed, and is formed of a gate insulating film 35, a gate electrode conductive film 36, and a spacer 38 in a region away from the device isolation region 33. In the gate electrode, for example, the transfer gate Tx in the pixel array region A-A 'and the P wells 34a and P-Well and the N wells 234b and N-Well in the peripheral circuit region B-B'. NMOS transistors and PMOS transistors PMOS are formed in the transistors.
Tx와 소자분리영역(33)에 접하면서 반도체층(30) 내부에 소정의 깊이로 형성된 포토다이오드용 N형 불순물 영역(n-영역, 137)과 n-영역(37) 상부의 반도체층(30)과 접하는 계면에 얕은 포토다이오드용 P형 불순물 영역(P0영역, 39)이 배치되어 있으며, 고농도 N형 불순물 영역인 센싱확산영역(FD, 40)이 배치되어 있으며, NMOS와 PMOS는 각각 n+(41)와 P+(42)의 소스/드레인 불순물 영역을 구비하고 있다.N-type impurity regions (n-regions) 137 and n-regions 37 for photodiodes formed in a predetermined depth inside the semiconductor layer 30 while being in contact with the Tx and the device isolation region 33. P-type impurity regions (P0 regions, 39) for shallow photodiodes are disposed at the interface with each other, and sensing diffusion regions (FD, 40), which are highly-concentrated N-type impurity regions, are disposed. 41) and a source / drain impurity region of P + 42.
전술한 본 발명은, 화소어레이영역에서의 소자분리영역을 P형 불순물 이온주입을 통해 형성함으로써 LOCOS 또는 STI에 의한 필드절연막에 비해 더 좁고 깊게 형성할 수 있어, 암신호 발생을 억제할 수 있으며, 고직접화에 부응할 수 있음과 동시에 크로스토크 방지 및 저조도 특성을 향상시킬 수 있음을 실시예를 통해 알아 보았다.According to the present invention, the device isolation region in the pixel array region is formed through P-type impurity ion implantation, so that it is possible to form a narrower and deeper than the field insulating film formed by LOCOS or STI, thereby suppressing dark signal generation. It has been found through the examples that it can meet the high directing and at the same time improve the crosstalk prevention and low light characteristics.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 본 발명은, 암신호 발생을 억제할 수 있으며, 고직접화에 부응할 수 있음과 동시에 크로스토크 방지 및 저조도 특성을 향상시킬 수 있어, 궁극적으로 이미지센서의 성능 및 수율을 향상시킬 수 있는 탁월한 효과를 기대할 수 있다.The present invention described above can suppress the generation of dark signals, can cope with high directing, and can improve crosstalk prevention and low light characteristics, and can ultimately improve the performance and yield of an image sensor. Excellent effect can be expected.
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020010086260A KR100838466B1 (en) | 2001-12-27 | 2001-12-27 | A fabricating method of image sensor with improved high intergation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020010086260A KR100838466B1 (en) | 2001-12-27 | 2001-12-27 | A fabricating method of image sensor with improved high intergation |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20030056099A true KR20030056099A (en) | 2003-07-04 |
KR100838466B1 KR100838466B1 (en) | 2008-06-16 |
Family
ID=32214320
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020010086260A KR100838466B1 (en) | 2001-12-27 | 2001-12-27 | A fabricating method of image sensor with improved high intergation |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100838466B1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100644523B1 (en) * | 2004-07-30 | 2006-11-10 | 매그나칩 반도체 유한회사 | Method for fabricating image sensor with decreased dark signal |
US7556990B2 (en) | 2004-12-30 | 2009-07-07 | Dongbu Electronics Co., Ltd. | CMOS image sensor having improved signal efficiency and method for manufacturing the same |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11186377A (en) * | 1997-12-19 | 1999-07-09 | Toshiba Corp | Manufacture of semiconductor device |
US5877521A (en) * | 1998-01-08 | 1999-03-02 | International Business Machines Corporation | SOI active pixel cell design with grounded body contact |
JP4604296B2 (en) * | 1999-02-09 | 2011-01-05 | ソニー株式会社 | Solid-state imaging device and manufacturing method thereof |
-
2001
- 2001-12-27 KR KR1020010086260A patent/KR100838466B1/en not_active IP Right Cessation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100644523B1 (en) * | 2004-07-30 | 2006-11-10 | 매그나칩 반도체 유한회사 | Method for fabricating image sensor with decreased dark signal |
US7556990B2 (en) | 2004-12-30 | 2009-07-07 | Dongbu Electronics Co., Ltd. | CMOS image sensor having improved signal efficiency and method for manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
KR100838466B1 (en) | 2008-06-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100494030B1 (en) | Image sensor and method for fabricating the same | |
US7595210B2 (en) | Method of manufacturing complementary metal oxide semiconductor image sensor | |
US8268662B2 (en) | Fabricating method of complementary metal-oxide-semiconductor (CMOS) image sensor | |
KR100562668B1 (en) | A fabricating method of image sensor with decreased dark signal | |
KR100776151B1 (en) | A fabricating method of image sensor with improved high intergation | |
KR100748323B1 (en) | A fabricating method of image sensor | |
KR100838466B1 (en) | A fabricating method of image sensor with improved high intergation | |
KR100748324B1 (en) | fabricating method Image sensor | |
KR100873288B1 (en) | Imase sensor and method for fabricating of the same | |
KR20040003981A (en) | Imase sensor with improved capability of protection against crosstalk and method for fabricating thereof | |
KR20030058291A (en) | Image sensor and method for fabricating the same | |
KR100766675B1 (en) | A fabricating method of image sensor with decreased dark signal | |
KR100790287B1 (en) | Fabricating method of Image sensor | |
KR100870823B1 (en) | Imase sensor and method for fabricating of the same | |
KR100748314B1 (en) | Image sensor and fabricating method of the same | |
KR100730470B1 (en) | Method for manufacturing image sensor | |
KR100748317B1 (en) | Method for fabricating image sensor | |
KR100790286B1 (en) | Fabricating method of image sensor | |
KR100644523B1 (en) | Method for fabricating image sensor with decreased dark signal | |
KR20050093061A (en) | Cmos image sensor and method for fabricating the same | |
KR100776150B1 (en) | A fabricating method of image sensor | |
KR100841208B1 (en) | A fabricating method of image sensor with decreased dark signal | |
KR20030000653A (en) | Fabricating method of Image sensor | |
KR20030057613A (en) | Method for fabricating image sensor | |
KR20030001128A (en) | Image sensor and fabricating method of the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
N231 | Notification of change of applicant | ||
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20110530 Year of fee payment: 4 |
|
LAPS | Lapse due to unpaid annual fee |