KR20030001128A - Image sensor and fabricating method of the same - Google Patents

Abstract

PURPOSE: An image sensor and a method for manufacturing the same are provided to achieve a wide photodiode region and to prevent a cross-talk by deeply implanting p+ ions after forming a field insulating layer. CONSTITUTION: A field insulating layer(13) is formed at a desired portion of a semiconductor layer(10) of the first conductive type. A channel stop region(P+) of the first conductive type is formed at lower portion of the field insulating layer(13) while having a same width to the field insulating layer(13) and a desired depth('C'). A gate electrode(15) is formed on the semiconductor layer(10). The first doping region(n-) for a photodiode is formed to contact with the channel stop region(P+) while having a same depth to the channel stop region(P+). The second doping region(P0) for the photodiode is formed on the first doping region.

Description

Image sensor and fabrication method {Image sensor and fabricating method of the same}

The present invention relates to a semiconductor device, and more particularly, to an image sensor, and more particularly, to an image sensor capable of securing a photodiode area and minimizing cross talk between pixels.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal. In a double charge coupled device (CCD), individual metal-oxide-silicon (MOS) capacitors are very different from each other. A device in which charge carriers are stored and transported in a capacitor while being located in close proximity, and CMOS (Complementary MOS) image sensor is a CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits. Is a device that employs a switching method that creates MOS transistors by the number of pixels and sequentially detects the output using them.

In manufacturing such various image sensors, efforts are being made to increase the photo sensitivity of the image sensor, and one of them is a light condensing technology. For example, a CMOS image sensor is composed of a photodiode for detecting light and a portion of a CMOS logic circuit for processing the detected light into an electrical signal to make data. To increase light sensitivity, the ratio of the photodiode to the total image sensor area is increased. Efforts have been made to increase (usually referred to as Fill Factor).

FIG. 1 is a unit pixel circuit diagram of a conventional CMOS image sensor, and a submicron CMOS Epi process is applied to increase sensitivity and reduce cross talk effects between unit pixels.

The unit pixel is composed of one low voltage buried photodiode and four NMOS transistors. Unlike the conventional photo gate structure, the low voltage buried photodiode has a polysilicon with a light sensing region. Not only is it covered, it has excellent light sensitivity for short wavelength blue light as well as increase the depth of depletion in the light sensing area, so the light sensitivity for long wavelength red or infrared light is also excellent. On the other hand, the low-voltage buried photodiode structure allows photogenerated charges in the photosensitive area to be completely transported to the Floating Sensing Node, which significantly increases the charge transfer efficiency. There are advantages to it.

In addition, the transfer gate (Tx), that is, the gate electrode and the reset gate (Rx), which transfer photocharges among the four transistors, is caused by a voltage drop due to a positive threshold voltage. In order to prevent the loss of charge transport efficiency, the NMOS transistor has a negative threshold voltage. In this case, the N-LDD ion implantation is omitted so that the overlap capacitance between the gate electrode and the reset gate and the floating sensing node is reduced. (Overlap Capacitance) can be lowered, so that the potential change of the floating sensing node can be amplified according to the amount of charge carried. (△ V-ΔQ / C)

Meanwhile, the drive gate (Sx) serving as a source follower is composed of a general submicron NMOS transistor. This structure was constructed with minimal changes to the submicron CMOS Epi process, and the thermal cycle was designed to be completely unchanged. On the other hand, a color filter array composed of red, green, blue, or yellow, magenta, cyan, and the like on a unit pixel array for implementing a color image. (Color Filter Array) The process of forming.

The operation principle of obtaining an output from such a unit pixel is as follows.

end. Turn off Tx, Rx, Sx. The low voltage buried photodiode is then fully depletion.

I. Photogenerated charge is collected in a low voltage buried photo diode.

All. After a proper integration time, the Rx is turned on to reset the floating sensing node first.

la. The unit pixel is turned on by turning on Sx.

hemp. Measure the output voltage (V1) of the source follower buffer. This value simply means the CD level shift of the Floating Sensing Node.

bar. Turn on Tx.

four. All photogenerated charges are transported to a FloatingSensing Node.

Ah. Turn off Tx.

character. Measure the output voltage (V2) of the source follower buffer.

car. The output signals V1-V2 are the result of the photocharge transport resulting from the difference between V1 and V2 and are pure signal values without noise. This method is called CDS (Corelated Double Sampling).

Ka. Repeat the process of 'a' to 'tea'. However, the low voltage buried photodiode is fully depleted during the 'dead' process.

2A to 2C are cross-sectional views illustrating an image sensor manufacturing process according to the prior art.

First of all, the drive gate (Dx) serving as a source follower and the switching gate (addressing) can be addressed by switching. A step of forming a P-well (not shown) is carried out so as to contain (Select Gate, Sx).

Subsequently, as shown in FIG. 2A, a pad oxide film 11 / buffer polysilicon film (not shown) is used to distinguish a field oxide region from an active region. / Nitride (Nitride, 12), etc. are continuously applied, and then the photoresist film (PR) is coated, exposure and development are performed using an element isolation (ISO) mask to etch the portion to be the field insulating film region through dry etching.

Next, as shown in FIG. 2B, P + ion implantation is performed for the N channel field stop, and then the field insulating layer 13 is formed through a thermal process, and then the pad oxide layer 11 on the active region is formed. ) And the nitride film 12 are removed by etching.

Next, as shown in FIG. 2C, a polysilicon film and a tungsten silicide film are successively coated to form the gate electrodes of the four NMOS transistors in the unit pixel, and a photoresist film (not shown) is applied, followed by a mask for forming a gate electrode. Exposure and development are carried out using. At this time, since the doping profile of the low voltage buried photodiode on one side of the formed transfer gate (Tx) determines the charge transfer efficiency, the thickness of the gate electrode is sufficiently increased. By thickening, high energy N-type ion implantation and low energy P-type ion implantation to form a low voltage buried photodiode can be self-aligned on one side of the gate electrode (Thick Polycide process).

If the thickness of the gate electrode is not thick enough, dopant phosphorus (P31) penetrates through the gate electrode during high-energy N-type ion implantation, and high-energy P-type ion implantation and low-energy P-type ion implantation are performed on one side of the gate electrode. Self alignment is not possible at, resulting in low charge transfer efficiency.

Subsequently, a polyetch layer of portions other than the gate electrode is removed by dry etching to form the gate electrodes 14 and 15, and then a photoresist (not shown) is applied to form a low voltage buried photodiode. Energy N-type ion implantation is performed, wherein one side of the high energy N-type ion implantation mask is aligned at the center of the gate electrode and the other side is aligned at the interface between the field oxide film and the active region. Part of it must enter the active area. That is, the low voltage buried photodiode must include a region in which low energy P-type ion implantation is to be performed and high energy N-type ion implantation is not performed (Connection Window structure).

This is because the region formed by the low energy P-type ion implantation should not be electrically separated from the P-Epi layer by the region formed by the high energy N-type ion implantation. If the low-energy P-type region is not electrically connected to the P-epi layer, the voltage buried photodiode will not function normally and will act like a simple PN junction. Through this process, the first deep buried PN junction is formed on the low concentration P-epi layer, and then the photoresist film is removed.

Subsequently, after forming a photosensitive film (not shown) to form a low voltage buried photodiode, low energy P-type ion implantation is performed using a low energy P-type ion implantation mask. One side of the mask is aligned at the center of the gate electrode, and the other side is aligned at the interface between the field oxide film and the active region, and no part enters the active region. Therefore, the low-energy P-type ion implantation region is electrically connected to the low-concentration P-epi layer at the interface between the field insulating layer 13 and the active region where the high-energy N-type ion implantation is not performed, so that the low voltage buried photodiode is operated. It always has an equipotential. This process removes the photoresist (not shown) after forming a high energy N-type ion implantation layer and a second shallow PN junction.

On the other hand, the conventional photodiode as described above has the following problems.

That is, the channel field stop (P +) invades the photodiode region by 'A' as shown in FIG. This causes cross talk of electrons between pixels, causing malfunction of the image sensor.

The present invention proposed to solve the problems of the prior art as described above, secures and crosses a wide photodiode region by deeply implanting P + ions after forming a field insulating film for device isolation and a field insulating film during channel field stop ion implantation. An object of the present invention is to provide an image sensor capable of preventing torque and a method of manufacturing the same.

1 is a unit pixel circuit diagram of a conventional CMOS image sensor;

2a to 2c is a cross-sectional view showing the image sensor uplifting process according to the prior art,

3A to 3D are cross-sectional views illustrating an image sensor manufacturing process according to an embodiment of the present invention;

4A to 4D are cross-sectional views illustrating an image sensor manufacturing process according to another exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10: semiconductor layer

13: field insulating film

14, 15, and 16 gate electrodes

P +: Channel Stop Area

In order to achieve the above object, the present invention, the first conductive semiconductor layer; A field insulating film disposed locally on the semiconductor layer; A channel stop region of a first conductivity type disposed in the semiconductor layer at a first depth with a width of the field insulating layer below the field insulating layer; A gate electrode disposed on the semiconductor layer; A first impurity region of a second conductivity type for a photodiode disposed in the semiconductor layer at a second depth substantially the same as the channel stop region and in contact with the gate electrode and the channel stop region; And a second impurity region of the first conductivity type for photodiode disposed on the first impurity region and in contact with the surface of the semiconductor layer.

In addition, the present invention to achieve the above object, the first step of forming a field insulating film on the semiconductor layer of the first conductivity type; A second step of forming a channel stop region of a first conductivity type in a first depth under the field insulating layer through ion implantation; Forming a gate electrode on the semiconductor layer; Forming a second conductive impurity region of the second conductivity type in contact with the channel stop region and the gate electrode at a second depth substantially equal to the channel stop region through ion implantation; And a fifth step of forming a second impurity region of a first conductivity type at an interface in contact with the semiconductor layer in the first impurity region.

In addition, the present invention to achieve the above object, the first step of forming a channel stop region to the first depth inside the semiconductor layer of the first conductivity type; Forming a field insulating film on the semiconductor layer on which the channel stop region is formed; Forming a gate electrode on the semiconductor layer; A fourth step of forming a first impurity region of a second conductivity type in contact with the channel stop region and the gate electrode through ion implantation to a second depth; A fifth step of forming a second impurity region of a first conductivity type at an interface in contact with the semiconductor layer in the first impurity region; And a sixth step of making the depth of the channel stop region substantially the same as the second depth through ion implantation using a field insulating film open mask.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3D is a cross-sectional view of the image sensor of the present invention.

Referring to FIG. 3D, the image sensor of the present invention includes a P-type semiconductor layer 10, a field insulating film 13 disposed locally on the semiconductor layer 10, and a field insulating film 13 under the field insulating film 13. P-type channel stop region P + disposed inside semiconductor layer 10 at a depth of " C '", gate electrodes 14, 15, 16 disposed on semiconductor layer 10, N-type impurities for photodiodes disposed in the semiconductor layer 10 to a depth substantially the same as the channel stop region P + and in contact with the gate electrodes 14, 15, and 16 and the channel stop region P +. A region n- and an impurity region P-type photodiode disposed over the impurity region n- and in contact with the surface of the semiconductor layer 10 are provided.

Hereinafter, an image sensor manufacturing process of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3D are cross-sectional views illustrating a manufacturing process of an image sensor according to an exemplary embodiment of the present invention.

First, as shown in FIG. 3A, a pad oxide film 11, a buffer polysilicon film (not shown), a nitride film 12, and the like are successively applied to distinguish the field insulating film region from the active region. And exposure using a device isolation (ISO) mask to perform exposure and development, and dry etching to etch the portion to be the field insulating film region.

Next, as shown in FIG. 3B, the field insulating layer 13 is formed through a thermal process, and then the pad oxide layer 11 and the nitride layer 12 on the active region are removed by etching.

Next, as shown in FIG. 3C, after the open mask 13 is formed, the channel insulating layer 13 is formed by performing P + ion implantation to form a deep channel stop region P + such as 'C'. As a result, the width thereof is substantially the same as the width of the field insulating film 13 to prevent the invasion into the photodiode region as much as possible, and to be deeply formed using large energy during ion implantation.

Next, as shown in FIG. 3D, a polysilicon film and a tungsten silicide film are successively applied to form the gate electrodes of the four NMOS transistors in the unit pixel, and then a photoresist film (not shown) is applied, followed by a mask for forming a gate electrode. Exposure and development are carried out using. At this time, since the doping profile of the low voltage buried photodiode on one side of the gate electrode formed later determines the charge transfer efficiency, the low voltage buried photodiode is made thick enough to make the gate electrode thick. High-energy N-type ion implantation and low-energy P-type ion implantation to form a self-alignment can be performed on one side of the gate electrode (Thick Polycide process).

If the thickness of the gate electrode is not thick enough, dopant phosphorus (P31) penetrates through the gate electrode during high-energy N-type ion implantation, and high-energy P-type ion implantation and low-energy P-type ion implantation are performed on one side of the gate electrode. Self alignment is not possible at, resulting in low charge transfer efficiency.

Subsequently, the polyelectrode layers other than the gate electrodes 14 and 15 are removed by dry etching to form the gate electrodes 14 and 15, and then a photoresist film (not shown) is used to form a low voltage buried photodiode. After applying the high energy N-type ion implantation, one side of the high energy N-type ion implantation mask is aligned at the center of the gate electrode and the other side of the field oxide film and the active region Align at the interface, part of which must be brought into the active area. That is, the low voltage buried photodiode must include a region in which low energy P-type ion implantation is to be performed and high energy N-type ion implantation is not performed (Connection Window structure).

This is because the region formed by the low energy P-type ion implantation should not be electrically separated from the P-Epi layer by the region formed by the high energy N-type ion implantation. If the low-energy P-type region is not electrically connected to the P-epi layer, the voltage buried photodiode will not function normally and will act like a simple PN junction. Through this process, the first deep buried PN junction is formed on the low concentration P-epi layer, and then the photoresist film is removed.

Subsequently, after forming a photosensitive film (not shown) to form a low voltage buried photodiode, low energy P-type ion implantation is performed using a low energy P-type ion implantation mask. One side of the mask is aligned at the center of the gate electrode, and the other side is aligned at the interface between the field oxide film and the active region, and no part enters the active region. Therefore, the low-energy P-type ion implantation region is electrically connected to the low-concentration P-epi layer at the interface between the field insulating layer 13 and the active region where the high-energy N-type ion implantation is not performed, so that the low voltage buried photodiode is operated. It always has an equipotential. Through this process, a high energy N-type ion implantation layer and a second shallow PN junction are formed, and then the photoresist film (not shown) is removed.

4A through 4D are cross-sectional views illustrating an image sensor manufacturing process according to another exemplary embodiment of the present invention.

First, as shown in FIG. 4A, a pad oxide film 11, a buffer polysilicon film (not shown), a nitride film 12, and the like are successively applied to distinguish the field insulating film region from the active region. And the exposure and development using the device isolation mask and the dry etching to etch the portion to be the field insulating film region.

Next, as shown in FIG. 4B, after performing P + ion implantation for the N-channel field stop, the field insulating layer 13 is formed through a thermal process, and then the pad oxide layer 11 and the nitride layer (on the active region) are formed. 12) The back is removed by etching.

Next, the process of FIG. 4C is performed. This is the same as the process of FIG. 2C, and thus will be omitted.

Next, additional ion implantation is performed using the field insulating film 13 open mask (not shown), whereby the channel stop region P + can be formed at a depth 'C' substantially equal to the n− region. At this time, the ion implantation is maintained in a 'Y' shape, and the dislocation generation region of the silicon lattice at the edge of the field insulating layer 13 is excluded from the photodiode region, so that dark current is hardly generated.

According to the present invention as described above, the width of the channel stop region can be minimized to ensure the maximum photodiode region, and the depth thereof is substantially the same as the impurity region of the photodiode forming region, thereby reducing cross talk and dark current. It can be seen through the embodiment that it can be minimized to improve the operating characteristics of the image sensor.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The above-described present invention can maximize the photodiode area to improve the light sensitivity, and by minimizing the cross talk and dark current of the inter-pixel data, it can be expected to have an excellent effect that can ultimately greatly improve the performance of the image sensor.

Claims (5)

CMOS image sensor, A first conductive semiconductor layer; A field insulating film disposed locally on the semiconductor layer; A channel stop region of a first conductivity type disposed in the semiconductor layer at a first depth with a width of the field insulating layer below the field insulating layer; A gate electrode disposed on the semiconductor layer; A first impurity region of a second conductive type for photodiode disposed in the semiconductor layer at a second depth substantially the same as the channel stop region and in contact with the gate electrode and the channel stop region; And A second impurity region of a first conductivity type for a photodiode disposed on the first impurity region and in contact with the surface of the semiconductor layer Image sensor comprising a. The method of claim 1, The first conductive type is a P-type, the second conductive type is an image sensor, characterized in that the N-type. In the image sensor manufacturing method, A first step of forming a field insulating film on the first conductive semiconductor layer; A second step of forming a channel stop region of a first conductivity type in a first depth under the field insulating layer through ion implantation; Forming a gate electrode on the semiconductor layer; Forming a second conductive impurity region of the second conductivity type in contact with the channel stop region and the gate electrode at a second depth substantially equal to the channel stop region through ion implantation; And A fifth step of forming a second impurity region of a first conductivity type at an interface in contact with the semiconductor layer in the first impurity region Image sensor manufacturing method comprising a. In the image sensor manufacturing method, A first step of forming a channel stop region in the first conductive semiconductor layer at a first depth; Forming a field insulating film on the semiconductor layer on which the channel stop region is formed; Forming a gate electrode on the semiconductor layer; A fourth step of forming a first impurity region of a second conductivity type in contact with the channel stop region and the gate electrode through ion implantation to a second depth; A fifth step of forming a second impurity region of a first conductivity type at an interface in contact with the semiconductor layer in the first impurity region; And A sixth step of making the depth of the channel stop region substantially the same as the second depth through ion implantation using a field insulating film open mask; Image sensor manufacturing method comprising a. The method according to claim 3 or 4, The first conductive type is a P-type, the second conductive type is an image sensor manufacturing method, characterized in that the N-type.