KR20070034885A - MOS image sensor manufacturing method - Google Patents

Abstract

The present invention relates to a method for manufacturing a CMOS image sensor that can prevent the depletion region is generated in the finally formed p ⁰ doped region to prevent deterioration of device characteristics due to the inflow of dark current, the present invention relates to a gate electrode and Providing a substrate having a first conductivity type first doped region for a photodiode, forming a second conductivity type second doped region in the first doped region, and forming spacers on both sidewalls of the gate electrode And forming a second conductivity type third doped region deeper than the second doped region in the first doped region by performing an ion implantation process having a tilt. .

CMOS image sensor, particles, dark current, tilt, rotation

Description

Manufacturing method of CMOS image sensor {METHOD FOR MANUFACTURING CMOS IMAGE SENSOR}

1 is a circuit diagram illustrating a unit pixel of a general CMOS image sensor.

2A to 2C are cross-sectional views illustrating a manufacturing process of a CMOS image sensor according to the prior art.

3A and 3B are cross-sectional views illustrating a mechanism in which overlap regions are formed in a p ⁰ doped region.

4A to 4D are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to a preferred embodiment of the present invention.

5 is a cross-sectional view illustrating a mechanism in which a depletion region is not formed in a p0 doped region.

FIG. 6 is a schematic diagram for explaining in detail the p ⁰ ion implantation step 27 performed in FIG. 4C. FIG.

<Description of the symbols for the main parts of the drawings>

10, 110: semiconductor substrate

11, 111: channel stop layer

12, 112: device isolation film

13, 113: well area

14, 114: gate insulating film

15, 115: polysilicon film

16a, 16b, 116a, 116b: gate electrode

17, 117 n-doped region

18, 24, 118, 128: p ⁰ doped region

19a, 19b, 119a, 119b: Lightly Doped Drain (LDD) Region

20, 120: silicon oxide film

21, 121: silicon nitride film

22a, 22b, 122a, 112b: spacer

23a, 23b, 125a, 125b: source / drain regions

30: Particle

40: deficient area

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a method of manufacturing a complementary metal-oxide-semiconductor (CMOS) image sensor among semiconductor devices.

Recently, the demand of digital cameras is exploding with the development of video communication using the Internet. Moreover, the demand for small camera modules increases as the popularity of mobile communication terminals such as PDAs equipped with cameras, International Mobile Telecommunications-2000 (IMT-2000), Code Division Multiple Access (CDMA) terminals, etc. increases. Doing.

As a camera module, an image sensor module using a Charge Coupled Device (CCD) or a Complementary Metal-Oxide-Semiconductor (CMOS) image sensor, which are basic components, is widely used. The image sensor is arranged on the upper part of the light sensing unit for generating and accumulating photocharges from the outside to implement a color image. Such color filter arrays (CFAs) are red (R), green (G) and blue (B), or yellow, magenta, and cyan. It consists of a branch collar. Typically, three colors of red (R), green (G), and blue (B) are frequently used in a color filter array of a CMOS image sensor.

Such an image sensor is a semiconductor device that converts an optical image into an electrical signal. As described above, CCD and CMOS image sensors have been developed and widely commercialized. A CCD is a device in which charge carriers are stored and transported in a capacitor while individual metal-oxide-silicon (MOS) capacitors are in close proximity to each other. On the other hand, a CMOS image sensor uses a CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits to make MOS transistors by the number of pixels, and uses the switching to detect an output sequentially. It is a device employing the method.

However, CCD has many disadvantages such as complicated driving method, high power consumption, high number of mask processes, complicated process, and difficult to implement one chip because signal processing circuit cannot be implemented in CCD chip. Recently, researches on the development of CMOS image sensors using sub-micron CMOS manufacturing techniques have been enthusiastically conducted to overcome the disadvantages of the CCD.

The CMOS image sensor forms an image by forming a photo diode and a MOS transistor in a unit pixel and sequentially detects a signal in a switching method. Since the CMOS manufacturing technology is used, the power consumption is low and the number of masks is approximately. The process is very simple compared to CCD process that requires 30 to 40 masks, and it is possible to make various signal processing circuits and one chip.

In general, the CMOS image sensor is composed of a light sensing unit for detecting light and a logic circuit unit for processing the light detected by the light sensing unit into an electrical signal and converting the data into light. Efforts are underway to increase the fill fraction. However, there is a limit to this effort under a limited area since the logic circuit part cannot be removed essentially. Accordingly, in order to increase the light sensitivity, a condensing technology that changes the path of light incident to an area other than the light sensing unit and collects the light sensing unit has emerged. For this purpose, an image sensor forms a microlens on a color filter. I'm using the method.

1 is a circuit diagram illustrating a unit pixel of a general CMOS image sensor.

Referring to FIG. 1, a unit pixel of a CMOS image sensor includes one photo diode (PD) and four MOS transistors, and the four MOS transistors include a transfer transistor (Tx), a reset transistor (Rx), and a drive. It consists of a transistor Dx and a selector transistor Sx. A load transistor is formed outside the unit pixel to read an output signal. Unexplained reference 'Cfd' indicates the capacitance of the floating diffusion.

Hereinafter, a method of manufacturing a CMOS image sensor according to the prior art will be described with reference to FIGS. 2A to 2C. 2A to 2C, only one of a plurality of transistors of a photodiode, a transfer transistor, and a logic circuit is illustrated for convenience of description.

First, as illustrated in FIG. 2A, a logic region is defined as a region (hereinafter referred to as a logic region) and a region where a pixel including a light sensing unit is formed (hereinafter referred to as a pixel region). Provides a semiconductor substrate 10 defined as a region where a photodiode is formed (hereinafter referred to as PD) and a region where a transfer transistor is formed (hereinafter referred to as Tx). In this case, the semiconductor substrate 10 has a structure in which a P + region and a P- epi layer are stacked.

Subsequently, a trench isolation (not shown) is formed by performing a shallow trench isolation (STI) process, and a channel stop region 11 is formed by performing a channel stop ion implantation process to form a trench. The device isolation layer 12 to be embedded is formed.

Subsequently, a well ion implantation process is performed to form the well region 13 for the logic element in the logic region, and p-type or n-type impurities are selectively implanted to control the threshold voltage, thereby forming a p-type or n-type region (not shown). To form.

Subsequently, gate electrodes 16a and 16b are formed in the logic region and the Tx region, respectively. At this time, the gate electrodes 16a and 16b are formed in a stacked structure of the gate insulating film 14 and the polysilicon film 15.

Subsequently, as shown in FIG. 2B, an n-ion implantation process using an n-ion implantation mask (not shown) is performed to form an n-doped region 17 constituting a photodiode in the PD region.

Subsequently, a p ⁰ ion implantation process using a p ⁰ ion implantation mask (not shown) is performed to form a p ⁰ doped region 18 in the n − doped region 17. At this time, the p ⁰ doped region 18 is formed relatively thin.

Subsequently, an LDD ion implantation process using a lightly doped drain (LDD) ion implantation mask (not shown) is performed to form LDD regions 19a and 19b in the substrate 10 exposed to both sides of the gate electrodes 16a and 16b. do.

Subsequently, as shown in FIG. 2C, spacers 22a and 22b are formed on both side walls of the gate electrodes 16a and 16b, respectively. In this case, the spacers 22a and 22b have a stacked structure of the silicon oxide film 20 and the silicon nitride film 21. The manufacturing process is performed by sequentially forming the silicon oxide film 20 and the silicon nitride film 21. It is done by the process.

Subsequently, a source / drain ion implantation process using a source / drain ion implantation mask (not shown) is performed to relatively expose the logic region and floating diffusion region (hereinafter referred to as FD) exposed to both sides of the gate electrodes 16a and 16b. High concentration n + source / drain regions 23a and 23b are formed. At this time, the source / drain regions 23a and 23b are formed deeper than the LDD regions 19a and 19b.

Subsequently, a p ⁰ ion implantation process using a p ⁰ ion implantation mask (not shown) is performed once again to form a p ^o doped region 24 deeper than the p ⁰ doped region 18 in the n − doped region 17. .

Subsequently, a target temperature profile is diffused by performing a rapid temperature process (RTP) or a rapid temperature process (RTA) process to diffuse the p-type or n-type impurity ions implanted during the source / drain ion implantation process and the p ⁰ ion implantation process. which forms a source / drain region and the p-doped region ^0.

However, in the method of manufacturing the CMOS image sensor according to the related art described above, as shown in FIG. 3A, particles (or particles) are formed in the PD region during the etching process for forming the gate electrode 16b of the transfer transistor or the etching process for forming the spacer 22b. particles, 30) (eg cone defects) are produced. These large pie 30 has such an etching process is generated in addition to the PD region in the manufacturing process which is performed before the second p ⁰ ion implantation process proceeds.

The particle 30 acts as an ion implantation barrier layer in a subsequent second p ⁰ ion implantation process so that ions are not implanted in the region where the particle 30 exists as shown in FIG. 3B. Accordingly, the deficient region 40 into which the ions are not implanted is present in the final p ⁰ doped region 24. The deficient region 40 is a portion that does not form a potential barrier against the dark current flowing from the surface, and is generated at the location where the particles are located, and serves as a passage for the dark current flowing from the surface of the substrate 10.

Accordingly, the present invention has been made to solve the above-described problems of the prior art, a CMOS image that can prevent the depletion region is generated in the finally formed p ⁰ doped region to prevent deterioration of device characteristics due to dark current inflow Its purpose is to provide a method of manufacturing a sensor.

According to an aspect of the present invention, there is provided a substrate including a gate electrode and a first conductive first doped region for a photodiode, and a second conductive second doped region in the first doped region. Forming a spacer; forming a spacer on both sidewalls of the gate electrode; and performing an ion implantation process having a tilt, wherein the second conductive doped region is deeper than the second doped region in the first doped region. It provides a method of manufacturing a CMOS image sensor comprising the step of forming a.

The ion implantation process may be performed by rotating the substrate.

Preferably, the tilt is characterized in that 1 ~ 10 °.

Preferably, the ion implantation process is carried out in a four-rotation process of implanting ions after positioning the substrate at 0 °, 90 °, 180 °, 270 °.

The method may further include forming a source / drain region on the substrate exposed to both sides of the gate electrode after forming the spacer.

Preferably, the second doped region is formed at 5 ~ 30keV ion implantation energy.

The method may further include performing an RTP or RTA process after forming the third doped region.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

4A to 4D are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to a preferred embodiment of the present invention. 4A to 4D illustrate only one of a plurality of transistors of a photodiode, a transfer transistor, and a logic circuit unit for convenience of description.

First, as shown in FIG. 4A, a logic region is defined as a region (hereinafter referred to as a logic region) and a region where a pixel including a light sensing unit is formed (hereinafter referred to as a pixel region). The semiconductor substrate 110 is defined as a region where a photodiode is formed (hereinafter referred to as PD) and a region where a transfer transistor is formed (hereinafter referred to as Tx). In this case, the semiconductor substrate 110 has a structure in which a P + region and a P- epi layer are stacked.

Subsequently, an STI process is performed to form a device isolation trench (not shown), a channel stop ion implantation process is performed to form a channel stop region 111, and a device isolation layer 112 is formed to fill the trench. In this case, the device isolation layer 112 is formed of an HDP (High Density Plasma) oxide film or an epitaxial growth polysilicon film having excellent embedding characteristics.

Subsequently, the well ion implantation process is performed to form the well region 113 for the logic element in the logic region, and to selectively inject p-type or n-type impurities to adjust the threshold voltage, thereby forming a p-type or n-type region (not shown) To form.

Subsequently, gate electrodes 116a and 116b are formed in the logic region and the Tx region, respectively. At this time, the gate electrodes 116a and 116b are formed in a stacked structure of the gate insulating film 114 and the polysilicon film 115.

Subsequently, an n− ion implantation process using an n− ion implantation mask (not shown) is performed to form an n− doped region 117 constituting a photodiode relatively deeply in the substrate 110 of the PD region.

Subsequently, in order to compensate for the surface of the substrate 110 damaged by the plasma during the n-ion implantation process, a curing process is performed to grow an oxide film (not shown) on the surface of the substrate 110.

Subsequently, a p ⁰ ion implantation process using a p ⁰ ion implantation mask (not shown) is performed to form a p ⁰ doped region 118 in the n − doped region 117. At this time, the p ⁰ doped region 118 is preferably formed relatively thin using ion implantation energy of about 5 ~ 30keV.

Next, an LDD ion implantation process using an LDD ion implantation mask (not shown) is performed to form LDD regions 119a and 119b in the substrate 110 exposed to both sides of the gate electrodes 116a and 116b.

Subsequently, spacers 122a and 122b are formed on both side walls of the gate electrodes 116a and 116b, respectively. In this case, the spacers 122a and 122b have a stacked structure of the silicon oxide film 120 and the silicon nitride film 121, and are formed by sequentially etching the silicon oxide film 120 and the silicon nitride film 121.

Subsequently, as shown in FIG. 4B, a mask process is performed to form a source / drain ion implantation mask 123. In this case, the mask process is performed through a photolithography process.

Subsequently, a source / drain ion implantation process 124 using the source / drain ion implantation mask 123 is performed to expose a logic region and a floating diffusion region (hereinafter referred to as FD) exposed to both sides of the gate electrodes 116a and 116b. Relatively high concentrations of n + source / drain regions 125a and 125b are formed. In this case, the source / drain regions 125a and 25b are formed deeper than the LDD regions 119a and 119b.

Meanwhile, n-type impurities are also doped into the gate electrodes 116a and 116b during the source / drain ion implantation process.

Subsequently, as illustrated in FIG. 4C, the source / drain ion implantation mask 123 is removed through a strip process and then a mask process is performed to form a p ⁰ ion implantation mask 127. Here, the p ⁰ ion implantation mask 127 may not be formed, and the p ⁰ ion implantation process 128 may be performed.

Then, to form a p ⁰ ion implantation mask 127, a p ⁰ ion implantation process 128 performed by the n- doped region 117 in the p-doped region ⁰ 118 p ^o deeper doped regions 128 using . At this time, the p ⁰ ion implantation process 128 is performed by rotating the wafer W completed to the p ⁰ ion implantation mask 127 as shown in FIG. 6 with a tilt of 1 to 10 °. do.

Herein, the process of rotating the wafer W by 4 is performed by placing the wafer W seated on the wafer chuck at 0 °, 90 °, 180 °, and 270 °, respectively, and then performing a p ⁰ ion implantation process. Means. That is, the four rotation step is subjected to p ⁰ ion implantation after performing a step by rotating the back wafer (W) again p ⁰ ion implantation process in a state positioned at 90 ° in a state in which the position of the wafer (W) to O ° , in addition to, re-rotating the wafer (W), position to the 180 ° state as a way to carry out an ion implantation process 270 ° p ⁰ is performed sequentially.

Subsequently, after removing the p ⁰ ion implantation mask 127 through a strip process, RTP or RTA processes are performed to diffuse the p-type or n-type impurity ions implanted during the source / drain ion implantation process and the p ⁰ ion implantation process. Source and drain regions having a target profile are formed and the p ⁰ doped region.

Subsequently, as illustrated in FIG. 4D, an insulating film 129 is formed to perform subsequent processes such as a subsequent metallization process, a color filter formation process, and a microlens formation process.

In the method of manufacturing a CMOS image sensor according to the preferred embodiment of the present invention described above, as shown in FIG. 5, the ion implantation process is performed by placing a tilt of about 1 to 10 ° during the p ⁰ ion implantation process 127. Even when the particle 130 is present in the PD region due to various causes before the ^zero ion implantation process 127, the overlap region is not formed in the p ⁰ doped region 128.

Meanwhile, in the first p ⁰ ion implantation process performed in FIG. 4A, the ion implantation process may be performed by putting a tilt. In this case, boron penetrates into the lower portion of the spacer 122b to form a potential barrier. The potential barrier prevents the charges formed in the photodiode from being transferred to the floating diffusion region. As a result, a problem may occur in which an image lag exists in the CMOS image sensor.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the In accordance with the present invention, p ⁰ second to form the doped region p ⁰ ion implantation process when depletion region by ensuring that there is no depletion region in subjected to an ion implantation process by placing a tilt by p ⁰ doped region By blocking the inflow of dark current through the source can improve the dark current characteristics, thereby improving the characteristics of the device.

Claims (7)

Providing a substrate having a gate electrode and a first conductivity type first doped region for a photodiode; Forming a second conductivity type second doped region in the first doped region; Forming spacers on both sidewalls of the gate electrode; And Performing a ion implantation process having a tilt to form a second conductivity type third doped region deeper than the second doped region in the first doped region Method of manufacturing a CMOS image sensor comprising a. The method of claim 1, And the ion implantation step is performed by rotating the substrate. The method according to claim 1 or 2, The tilt is 1 ~ 10 ° CMOS image sensor manufacturing method. The method of claim 3, wherein The ion implantation process is a CMOS image sensor manufacturing method of performing a four-rotation process of implanting ions after positioning the substrate at 0 °, 90 °, 180 °, 270 °. The method of claim 4, wherein And forming source / drain regions on the substrate exposed to both sides of the gate electrode after forming the spacers. The method of claim 5, The second doped region is a manufacturing method of the CMOS image sensor is formed from 5 ~ 30keV ion implantation energy. The method of claim 6, And forming an RTP or RTA process after forming the third doped region.

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