KR20070064856A - Method for manufacturing image sensor - Google Patents

Abstract

A method for fabricating an image sensor is provided to reduce contamination of a substrate by controlling defects of a substrate and a potential barrier layer in forming a spacer while preventing the surface of the substrate from being exposed. A gate conductive layer is deposited on a substrate(110) of first conductivity type. A part of the gate conductive layer is etched to form a gate electrode(115a,115b) on the substrate. A first doping region for a photodiode of second conductivity type is formed in the substrate exposed to one side of the gate electrode. A spacer insulation layer is deposited along the step of the upper part of the resultant structure, made of a stack layer of a silicon oxide layer(120) and a silicon nitride layer(121). The spacer insulation layer is etched to leave a predetermined thickness of the spacer insulation layer on the substrate so that spacers(123) are formed on both sidewalls of the gate electrode. A wet etch process is performed by using a hydrofluoric acid solution to remove the spacer insulation layer remaining on the substrate. A second doping region of first conductivity type is formed as a potential barrier on the first doping region exposed to one side of the spacer.

Description

Image sensor manufacturing method {METHOD FOR MANUFACTURING IMAGE SENSOR}

1A to 1D are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to the prior art.

2A through 2D are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to Embodiment 1 of the present invention.

3A to 3D are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to Embodiment 2 of the present invention.

<Description of the symbols for the main parts of the drawings>

10, 110, 210: semiconductor substrate

11, 111, 211: device isolation film

12, 112, 212: Channel stop area

13, 113, 213: well area

14, 114, 214: gate insulating film

15, 115, 215: polysilicon film

15a, 15b, 115a, 115b, 215a, 215b: gate electrode

17, 117, 217: N ^- doped region

18, 25, 118, 126, 218, 226: P ⁰ doping area

19, 119, 219: low concentration junction region

20, 120, 220: silicon oxide film

21, 121, 221: silicon nitride film

22, 123, 222: spacer

23, 124, 224: source / drain regions

223: thermal oxide film 223a: nitride oxide film

The present invention relates to a method for manufacturing an image sensor, and more particularly, to a method for manufacturing a complementary metal-oxide-semiconductor (CMOS) image sensor.

Recently, the demand of digital cameras is exploding with the development of video communication using the Internet. Moreover, the demand for small camera modules increases as the popularity of mobile communication terminals such as PDAs equipped with cameras, International Mobile Telecommunications-2000 (IMT-2000), Code Division Multiple Access (CDMA) terminals, etc. increases. Doing.

As a camera module, an image sensor module using a Charge Coupled Device (CCD) or a Complementary Metal-Oxide-Semiconductor (CMOS) image sensor, which are basic components, is widely used. The image sensor is arranged on the upper part of the light sensing unit for generating and accumulating photocharges from the outside to implement a color image. Such color filter arrays (CFAs) are red (R), green (G) and blue (B), or yellow, magenta, and cyan. It consists of a branch collar. Typically, three colors of red (R), green (G), and blue (B) are frequently used in a color filter array of a CMOS image sensor.

Such an image sensor is a semiconductor device that converts an optical image into an electrical signal. As described above, a CCD and a CMOS image sensor have been developed and widely commercialized. A CCD is a device in which charge carriers are stored and transported in a capacitor while individual metal-oxide-silicon (MOS) capacitors are in close proximity to each other. On the other hand, a CMOS image sensor uses a CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits to make MOS transistors by the number of pixels, and uses the switching to detect an output sequentially. It is a device employing the method.

However, CCD has many disadvantages such as complicated driving method, high power consumption, high number of mask processes, complicated process, and difficult to implement one chip because signal processing circuit cannot be implemented in CCD chip. Recently, researches on the development of CMOS image sensors using sub-micron CMOS manufacturing techniques have been enthusiastically conducted to overcome the disadvantages of the CCD.

The CMOS image sensor forms an image by forming a photo diode and a MOS transistor in a unit pixel and sequentially detects a signal in a switching method. Since the CMOS manufacturing technology is used, the power consumption is low and the number of masks is approximately. The process is very simple compared to CCD process that requires 30 to 40 masks, and it is possible to make various signal processing circuits and one chip.

In general, the CMOS image sensor is composed of a light sensing unit for detecting light and a logic circuit unit for processing the light detected by the light sensing unit into an electrical signal and converting the data into an electric signal. Efforts are underway to increase this fill factor. However, there is a limit to this effort under a limited area since the logic circuit part cannot be removed essentially.

Hereinafter, a method of manufacturing a CMOS image sensor according to the prior art will be described with reference to FIGS. 1A to 1C. 1A to 1C, only one of a plurality of transistors of the photodiode PD, the transfer transistor Tx, and the logic circuit unit is illustrated for convenience of description.

First, as shown in FIG. 1A, a region in which a logic circuit is formed (hereinafter referred to as a logic region) and a region in which a pixel including a light sensing unit is formed (hereinafter referred to as a pixel region) are defined. Provides a semiconductor substrate 10 defined as a region where a photodiode is formed (hereinafter referred to as PD) and a region where a transfer transistor is formed (hereinafter referred to as Tx). At this time, the substrate 10 has a structure in which a P ⁺ region and a P ⁻ epi layer are stacked.

Subsequently, a trench isolation (not shown) is formed by performing a shallow trench isolation (STI) process, and a channel stop region 12 surrounding the isolation layer 11 is performed by performing a mask process and a channel stop ion implantation process. ). For example, the N channel stop region 12 is formed. Then, an isolation layer 11 in which the trench is embedded is formed.

Subsequently, a well ion implantation process is performed to form the well region 13 for the logic element in the logic region, and p-type or n-type impurities are selectively implanted to control the threshold voltage, thereby forming a p-type or n-type region (not shown). To form.

Subsequently, the gate insulating film 14 and the polysilicon film 15 to be used as the gate electrode are sequentially formed on the substrate 10.

Subsequently, as shown in FIG. 1B, the polysilicon layer 15 is etched through a dry etching process to form gate electrodes 15a and 15b in the logic region and the Tx region, respectively. The reason why the gate insulating layer 14 is left when forming the gate electrodes 15a and 15b is to prevent the PD from being directly exposed and causing damage during subsequent processes.

Subsequently, a mask process and a deep N ion implantation process are performed to form an N ⁻ doped region 17 constituting a photodiode in the substrate 10 of the PD.

Subsequently, a first p ⁰ ion implantation process using a p ⁰ ion implantation mask (not shown) is performed to form a p ⁰ doped region 18 in the N ⁻ doped region 17. At this time, the p ⁰ doped region 18 is formed relatively thin.

Subsequently, an LDD ion implantation process using a lightly doped drain (LDD) ion implantation mask (not shown) is performed to form a low concentration junction region 19 in the substrate 10 exposed to both sides of the gate electrodes 15a and 15b. .

Subsequently, as shown in FIG. 1C, a cleaning process is performed to remove the gate insulating layer 14 exposed to both sides of the gate electrodes 15a and 15.

Subsequently, the silicon oxide film 20 and the silicon nitride film 21 are sequentially deposited with an insulating film for spacers along the steps of the entire structure including the gate electrodes 15a and 15b. For example, the silicon oxide film 20 is deposited to a thickness of 100 ~ 200Å, the silicon nitride film 21 is deposited to a thickness of 700 ~ 900Å so that the final length (L) of the spacer to be formed subsequently to 0.1㎛.

Subsequently, a dry etching process is performed to sequentially etch the silicon nitride film 21 and the silicon oxide film 20 to form spacers 22 on both sidewalls of the gate electrodes 15a and 15b, respectively.

Subsequently, as shown in FIG. 1D, a source / drain ion implantation process using a source / drain ion implantation mask (not shown) is performed to expose the logic region and the floating diffusion region (eg, exposed to both sides of the gate electrodes 16a and 16b). A relatively high concentration of N ⁺ source / drain regions 23 is formed in the following. At this time, the source / drain region 23 is formed deeper than the LDD region 19.

Subsequently, a p ⁰ ion implantation process using a second p ⁰ ion implantation mask (not shown) is performed to form a p ^o doped region 25 deeper than the p ⁰ doped region 18 in the N ⁻ doped region 17.

Subsequently, a target temperature profile is diffused by performing a rapid temperature process (RTP) or a rapid temperature process (RTA) process to diffuse the p-type or n-type impurity ions implanted during the source / drain ion implantation process and the p ⁰ ion implantation process. which forms a source / drain region and the p-doped region ^0.

However, during the dry etching process as shown in FIG. 1C, the etching selectivity between the silicon nitride film 21 and the silicon oxide film 20 is low, so that the surface of the substrate 10 is etched by about 200 μs (see 'h' region). As a result, the surface of the substrate 10 has a defect. The defect of the substrate 10 is a major cause of dark current, and the surface of the first P ⁰ doped region 18 also has a defect, thereby ensuring sufficient potential barrier layer for dark current. There will be no.

In particular, such dark current generation is a major cause of deterioration of the characteristics of the image sensor.

Accordingly, an object of the present invention is to provide a method for manufacturing an image sensor capable of preventing deterioration of device characteristics by suppressing generation of dark current, which is devised to solve the above problems of the prior art.

According to an aspect of the present invention, there is provided a method including: depositing a gate conductive layer on a substrate of a first conductivity type, forming a gate electrode on the substrate by etching a portion of the gate conductive layer; Forming a first doped region for a photoconductive diode of a second conductivity type in the substrate exposed to one side of the gate electrode, depositing an insulating film for a spacer along a step of an upper portion of the entire structure including the gate electrode; Etching the spacer insulating film to form a spacer on both sidewalls of the gate electrode such that the spacer insulating film remains on the substrate at a predetermined thickness, and performing a wet etching process to maintain the insulating film for the spacer. Removing the potential and potential on the first doped region exposed to one side of the spacer; A rieoyong provides a second method of manufacturing an image sensor comprising a step of forming a doped region of the first conductivity type.

In one aspect of the present invention, after forming the spacer, further comprising removing a predetermined thickness of the insulating film for the spacer remaining on the substrate in order to remove the damage of the insulating film for the spacer generated during formation of the spacer. can do.

In addition, the present invention according to another aspect for achieving the above object, the step of depositing a gate conductive film on the substrate of the first conductivity type, and forming a gate electrode on the substrate by etching a portion of the gate conductive film And forming a first doped region for a photoconductor of a second conductivity type in the substrate exposed to one side of the gate electrode, forming a spacer on both sidewalls of the gate electrode, and forming the spacer. Performing a thermal oxidation process to compensate for defects of the formed substrate and forming a thermal oxide film along a step of an upper portion of the entire structure including the gate electrode, and a potential berry on the first doped region exposed to one side of the spacer. It provides a method of manufacturing an image sensor comprising the step of forming a second doped region of the first conductivity type for use.

In another aspect of the present invention, after the thermal oxide film is formed, a plasma nitriding process may be performed to convert the thermal oxide film into a nitride film-based material.

In another aspect of the present invention, after performing the thermal oxidation process, may further comprise the step of performing a heat treatment.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example 1

2A to 2D are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to Embodiment 1 of the present invention. 2A to 2D illustrate only one of a photodiode PD, a transfer transistor Tx, and a plurality of transistors of a logic circuit unit for convenience of description.

First, as shown in FIG. 2A, a logic region is defined as a region (hereinafter referred to as a logic region) and a region where a pixel including a light sensing unit is formed (hereinafter referred to as a pixel region). The semiconductor substrate 110 is defined as a region where a photodiode is formed (hereinafter referred to as PD) and a region where a transfer transistor is formed (hereinafter referred to as Tx). In this case, the substrate 110 has a structure in which a P ⁺ region and a P ⁻ epi layer are stacked.

Subsequently, an STI process is performed to form trenches for device isolation (not shown), and a channel stop region 112 is formed by performing a mask process and a channel stop ion implantation process. Then, an isolation layer 111 in which the trench is embedded is formed. In this case, the device isolation layer 111 is formed of an HDP (High Density Plasma) oxide film or an epitaxially grown polysilicon film having excellent buried characteristics.

Subsequently, the well ion implantation process is performed to form the well region 113 for the logic element in the logic region, and to selectively inject p-type or n-type impurities to adjust the threshold voltage, thereby forming a p-type or n-type region (not shown) To form.

Subsequently, a polysilicon film 115 serving as a gate insulating film 114 and a gate conductive film is sequentially formed on the entire surface of the substrate 110.

Subsequently, as shown in FIG. 2B, a dry etching process is performed to etch the polysilicon film 115 (see FIG. 2A). As a result, gate electrodes 115a and 115b are formed on the logic region and the gate insulating film 114 of Tx, respectively. The reason why the gate insulating layer 114 is left during the formation of the gate electrodes 115a and 115b is to prevent the defect of the substrate 110 during the subsequent N ⁻ ion implantation process.

Subsequently, an N ⁻ ion implantation process using an N ⁻ ion implantation mask (not shown) is performed to form an N ⁻ doped region 117 constituting a photodiode relatively deeply in the substrate 110 of the PD.

Subsequently, although not shown in the drawing, a thermal oxidation process is performed to form a thermal oxide film along the step of the upper portion of the substrate 110 including the gate electrodes 115a and 115b. This is to prevent the defect of the substrate 110 during the subsequent P ⁰ ion implantation process.

Subsequently, a first p ⁰ ion implantation process using a p ⁰ ion implantation mask (not shown) is performed to form a p ⁰ doped region 118 in the N ⁻ doped region 117. At this time, the p ⁰ doped region 118 is formed relatively thin.

Next, an LDD ion implantation process using an LDD ion implantation mask (not shown) is performed to form a low concentration junction region 119 in the substrate 110 exposed to both sides of the gate electrodes 115a and 115b.

Subsequently, as shown in FIG. 2C, a thermal oxide film (not shown) and a gate insulating film 114 that are damaged during the ion implantation process for forming the N ⁻ doped region 117 and the P ⁰ doped region 118 are hydrofluoric acid solution. It is removed by cleaning using.

Subsequently, the silicon oxide film 120 and the silicon nitride film 121 are sequentially deposited with an insulating film for spacers along the steps of the entire structure including the gate electrodes 115a and 115b. For example, the silicon oxide film 120 is deposited to a thickness of 300 to 400Å thicker than the conventional (100 ~ 200Å), and the silicon nitride film 121 is subsequently formed by depositing to a thickness of 500 ~ 700Å thinner than the conventional (700 ~ 900Å). The final length L of the spacer to be made is 0.1 占 퐉.

Next, a dry etching process 122 is performed to sequentially etch the silicon nitride film 121 and the silicon oxide film 120 to form spacers 123 on both sidewalls of the gate electrodes 115a and 115b, respectively. In this case, although the etching selectivity of the silicon nitride film 121 and the silicon oxide film 120 is low, the time of the dry etching process 122 is adjusted to stop the etching in the silicon oxide film 120.

In particular, it is important to prevent the substrate 110 from being etched to a certain depth by performing the dry etching process 122 until the silicon oxide film 120 remains a certain thickness. For example, the dry etching process 122 is performed such that the remaining silicon oxide film 120a has a thickness of 150 to 210 kPa.

Subsequently, a cleaning process using a hydrofluoric acid solution is performed to make the final thickness of the remaining silicon oxide film 120a be 80 to 120 kPa. This is to prevent plasma damage generated in the silicon oxide film 120 during the dry etching process 122.

That is, by forming the silicon oxide film 120 at a predetermined thickness when forming the spacer 123, the substrate 110 may be prevented from being etched to a certain depth, thereby preventing defects in the substrate 110. Thus, the dark current flow can be interrupted. In addition, since surface defects of the first P ⁰ doped region 118 are suppressed together, sufficient potential barrier layer for dark current can be secured.

Subsequently, as illustrated in FIG. 2D, a source / drain ion implantation process using a source / drain ion implantation mask (not shown) is performed to expose the logic region and the floating diffusion region (eg, exposed to both sides of the gate electrodes 115a and 115b). A relatively high concentration of N ⁺ source / drain regions 124 is formed in the following). In this case, the source / drain region 124 is formed deeper than the low concentration junction region 119.

Subsequently, a p ⁰ ion implantation process using a second p ⁰ ion implantation mask (not shown) is performed to form a p ^o doped region 126 deeper than the p ⁰ doped region 118 in the N ⁻ doped region 117.

Subsequently, a target temperature profile is diffused by performing a rapid temperature process (RTP) or a rapid temperature process (RTA) process to diffuse the p-type or n-type impurity ions implanted during the source / drain ion implantation process and the p ⁰ ion implantation process. which forms a source / drain region and the p-doped region ^0.

Subsequently, the CMOS image sensor is completed by sequentially performing subsequent processes such as a metal wiring process, a color filter forming process, and a microlens forming process through a known technique.

Example 2

3A to 3D are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to Embodiment 2 of the present invention. 3A to 3D illustrate only one of the photodiode PD, the transfer transistor Tx, and a plurality of transistors of the logic circuit unit for convenience of description.

First, as shown in FIG. 3A, a logic region is defined as a region (hereinafter referred to as a logic region) and a region in which a pixel including a light sensing unit is formed (hereinafter referred to as a pixel region). Provides a semiconductor substrate 210 defined as a region where a photodiode is formed (hereinafter referred to as PD) and a region where a transfer transistor is formed (hereinafter referred to as Tx). At this time, the substrate 210 has a structure in which a P ⁺ region and a P ⁻ epi layer are stacked.

Subsequently, an STI process is performed to form trenches (not shown) for device isolation, and a channel stop region 212 is formed by performing a mask process and a channel stop ion implantation process. Then, an isolation layer 211 in which the trench is embedded is formed. In this case, the device isolation layer 211 is formed of an HDP (High Density Plasma) oxide film or an epitaxially grown polysilicon film having excellent buried characteristics.

Subsequently, a well ion implantation process is performed to form a logic region well region 213 in the logic region, and a p-type or n-type impurity is selectively injected to control a threshold voltage, thereby forming a p-type or n-type region (not shown). To form.

Subsequently, a polysilicon film (not shown) that functions as a gate insulating film 214 and a gate conductive film is sequentially formed on the entire surface of the substrate 210.

Next, a dry etching process is performed to etch the polysilicon film. As a result, gate electrodes 215a and 215b are formed on the logic region and the gate insulating film 214 of Tx, respectively. The reason why the gate insulating film 214 is left during the formation of the gate electrodes 215a and 215b is to prevent the defect of the substrate 210 in the subsequent N ⁻ ion implantation process.

Next, as shown in FIG. 3B, an N ⁻ ion implantation process using an N ⁻ ion implantation mask (not shown) is performed to form the N ⁻ doped region 217 relatively deeply in the substrate 210 of the PD. To form.

Subsequently, although not shown in the drawing, a thermal oxidation process is performed to form a thermal oxide film along a step of the upper portion of the substrate 210 including the gate electrodes 215a and 215b. This is to prevent the defect of the substrate 210 in the subsequent P ⁰ ion implantation process.

Subsequently, a first p ⁰ ion implantation process using a p ⁰ ion implantation mask (not shown) is performed to form a p ⁰ doped region 218 in the N ⁻ doped region 217. At this time, the p ⁰ doped region 218 is formed relatively thin.

Subsequently, an LDD ion implantation process using an LDD ion implantation mask (not shown) is performed to form a low concentration junction region 219 in the substrate 210 exposed to both sides of the gate electrodes 215a and 215b.

Subsequently, during the ion implantation process to form the N ⁻ doped region 217 and the P ⁰ doped region 218, a thermal oxidation film (not shown) and a gate insulating film 214 that are damaged are cleaned using a hydrofluoric acid solution. To remove it. For example, the gate insulating film 214 removes the gate insulating film 214 exposed to both sides of the gate electrodes 215a and 215b.

Subsequently, the silicon oxide film 220 and the silicon nitride film 221 are sequentially deposited as an insulating film for spacers along the steps of the entire structure including the gate electrodes 215a and 215b.

Subsequently, a dry etching process is performed to sequentially etch the silicon nitride film 221 and the silicon oxide film 220 to form spacers 222 on both sidewalls of the gate electrodes 215a and 215b.

Subsequently, as shown in FIG. 3C, in order to compensate for the defect of the damaged substrate 210 during the dry etching process for forming the spacer 222, a thermal oxidation process is performed to include the gate electrodes 215a and 215b. After the thermal oxide film 223 is formed along the step of the entire structure, a heat treatment process is performed.

For example, the thermal oxidation process uses a rapid thermal process (RTP) method or a diffusion furnace method within a temperature range of 600 to 1000 ° C. to form a thermal oxide film 223 having a thickness of 10 to 200 μs. Subsequent heat treatment process also uses a rapid heat treatment method or a diffusion furnace method within the temperature range of 600 ~ 1000 ℃.

That is, through the thermal oxidation process and the heat treatment process, the defect generated in the substrate 210 during the dry etching process for forming the spacer 222 may be compensated for to suppress the flow of the dark current.

Next, as illustrated in FIG. 3D, a nitriding process using plasma is performed to convert the thermal oxide film 223 (see FIG. 3C) into the nitride oxide film 223a. For example, the nitriding process is carried out using N ₂ or NH ₃ gas in a temperature condition of 200 ~ 600 ℃.

For reference, when the boron ions implanted into the P ⁰ doped region 226 are externally diffused by a subsequent process, the boron concentration is lowered to provide an inflow passage of dark current. Accordingly, in the second embodiment of the present invention, the nitride oxide film 223a is applied to prevent the boron from diffusing to the outside even in a subsequent process to suppress dark current flowing from the surface of the substrate 210.

Subsequently, a source / drain ion implantation process using a source / drain ion implantation mask (not shown) is performed to relatively expose the logic region and floating diffusion region (hereinafter referred to as FD) exposed to both sides of the gate electrodes 215a and 215b. A high concentration of N ⁺ source / drain regions 224 is formed. In this case, the source / drain region 224 is formed deeper than the low concentration junction region 219.

Subsequently, a p ⁰ ion implantation process using a second p ⁰ ion implantation mask (not shown) is performed to form a p ^o doped region 226 deeper than the p ⁰ doped region 218 in the N ⁻ doped region 217.

Subsequently, a target temperature profile is diffused by performing a rapid temperature process (RTP) or a rapid temperature process (RTA) process to diffuse the p-type or n-type impurity ions implanted during the source / drain ion implantation process and the p ⁰ ion implantation process. which forms a source / drain region and the p-doped region ^0.

Subsequently, the CMOS image sensor is completed by sequentially performing subsequent processes such as a metal wiring process, a color filter forming process, and a microlens forming process through a known technique.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the silicon oxide film constituting the spacer remains at a predetermined thickness when forming the spacer of the gate electrode, so that the defect of the substrate and the potential barrier layer during the formation of the spacer can be suppressed and the substrate surface is exposed. As a result, metal contamination can be reduced.

Therefore, dark current generation can be suppressed to improve characteristics of the image sensor.

In addition, by removing a portion of the silicon oxide film remaining a certain thickness damaged during the etching process using a hydrofluoric acid solution, it is possible to reliably block the cause of dark current generation.

In addition, defects in the substrate and defects in the potential barrier layer generated during the dry etching process for forming the spacers may be compensated for by the thermal oxidation process and the heat treatment process.

In addition, a nitride oxide film (or a thermal oxide film) is formed along the level of the upper part of the entire structure including the potential barrier layer, thereby preventing impurity ions injected into the potential barrier layer from diffusing to the outside through a subsequent process, thereby preventing passage of dark current. Can be removed in advance. Therefore, the reliability of the image sensor can be secured.

Claims (17)

Depositing a gate conductive film on the substrate of the first conductivity type; Etching a portion of the gate conductive layer to form a gate electrode on the substrate; Forming a first doped region for a photodiode of a second conductivity type in the substrate exposed to one side of the gate electrode; Depositing an insulating film for a spacer along a step of an entire structure including the gate electrode; Forming spacers on both sidewalls of the gate electrode by etching the spacer insulating film so that the spacer insulating film remains on the substrate at a predetermined thickness; Performing a wet etching process to remove the spacer insulating film remaining on the substrate; And Forming a second doped region of the first conductivity type for a potential barrier on the first doped region exposed to one side of the spacer; Image sensor manufacturing method comprising a. The method of claim 1, The wet etching process is an image sensor manufacturing method using a hydrofluoric acid solution. The method of claim 2, And forming a thickness of the spacer insulating film remaining on the substrate to remove damage of the spacer insulating film generated when the spacer is formed after forming the spacer. The method of claim 3, wherein Removing a predetermined thickness of the insulating film for spacers remaining on the substrate comprises a wet etching process using a hydrofluoric acid solution. The method according to claim 3 or 4, Removing a predetermined thickness of the spacer insulating film remaining on the substrate to perform the wet etching process so that the spacer insulating film remains on the substrate to a thickness of 80 to 120 Å. The method according to any one of claims 1 to 4, And the insulating film for spacers is formed of a laminated film of a silicon oxide film / silicon nitride film. The method of claim 6, The silicon oxide film is formed to a thickness of 200 ~ 300Å, the silicon nitride film is formed to a thickness of 500 ~ 700Å. The method according to any one of claims 1 to 4, After forming the first doped region for the photodiode, forming a third doped region of the first conductivity type for the potential barrier on the first doped region exposed to one side of the gate electrode. Image sensor manufacturing method. The method of claim 8, And forming the third doped region at a depth lower than that of the second doped region. Depositing a gate conductive film on the substrate of the first conductivity type; Etching a portion of the gate conductive layer to form a gate electrode on the substrate; Forming a first doped region for a photodiode of a second conductivity type in the substrate exposed to one side of the gate electrode; Forming spacers on both sidewalls of the gate electrode; Performing a thermal oxidation process to compensate for defects in the substrate generated during the formation of the spacers to form a thermal oxide film along a step of an upper portion of the entire structure including the gate electrode; And Forming a second doped region of the first conductivity type for a potential barrier on the first doped region exposed to one side of the spacer; Image sensor manufacturing method comprising a. The method of claim 10, After the thermal oxide film is formed, performing a plasma nitridation process to convert the thermal oxide film into a nitride film-based material further comprising the step of manufacturing an image sensor. The method of claim 11, The plasma nitriding process is carried out using an N ₂ or NH ₃ gas within a temperature condition of 200 ~ 600 ℃. The method of claim 10 or 11, After performing the thermal oxidation process, further comprising the step of performing a heat treatment. The method of claim 13, The heat treatment is an image sensor manufacturing method performed by a rapid heat treatment method or a diffusion furnace method within a temperature condition of 600 ~ 1000 ℃. The method of claim 10 or 11, The thermal oxidation process is an image sensor manufacturing method that is carried out in a rapid heat treatment method or diffusion furnace method within a temperature condition of 600 ~ 1000 ℃. The method of claim 15, The thermal oxide film is an image sensor manufacturing method to form a thickness of 10 ~ 200Å. The method of claim 10 or 11, After forming the first doped region for the photodiode, forming a third doped region of the first conductivity type for the potential barrier on the first doped region exposed to one side of the gate electrode. Image sensor manufacturing method.

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