KR20070048342A - Method for manufacturing cmos image sensor - Google Patents

Abstract

The present invention provides a CMOS image capable of preventing degradation of device characteristics caused by a layer of cone defect structure formed on a photodiode region after an etching process for forming a gate electrode for controlling charge of the photodiode. To provide a method for manufacturing a sensor, the present invention is to form a gate electrode on a substrate defining a region where the photodiode is to be formed, and forming a mask to open the region where the photodiode is to be formed And performing a cleaning process using the mask to remove the cone defect structure layer formed on the substrate in the region where the photodiode is to be formed during the gate electrode forming process; It provides a method for manufacturing a CMOS image sensor comprising the step of forming a diode.

CMOS image sensor, cone defect, dark current, BOE

Description

Manufacturing method of CMOS image sensor {METHOD FOR MANUFACTURING CMOS IMAGE SENSOR}

1 is a circuit diagram illustrating a unit pixel of a general CMOS image sensor.

2A to 2D are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to the prior art.

3A to 3D are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to an embodiment of the present invention.

4 is a plan view of the view shown in FIG. 3B.

<Description of the symbols for the main parts of the drawings>

10, 110: semiconductor substrate

11, 111: channel stop layer

12, 112: device isolation film

13, 113: well area

14, 114: gate insulating film

15, 115: polysilicon film

16a, 16b, 116a, 116b: gate electrode

17, 119: n-diffusion layer

18, 24, 120, 126: p ⁰ diffusion layer

19a, 19b, 121a, 121b: Lightly Doped Drain (LDD) Region

20, 122: silicon oxide film

21, 123: silicon nitride film

22a, 22b, 124a, 124b: spacer

23a, 23b, 125a, 125b: source / drain regions

16c, 116c: cone defect structure layer

117: mask

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a method of manufacturing a complementary metal-oxide-semiconductor (CMOS) image sensor among semiconductor devices.

Recently, the demand of digital cameras is exploding with the development of video communication using the Internet. Moreover, the demand for small camera modules increases as the popularity of mobile communication terminals such as PDAs equipped with cameras, International Mobile Telecommunications-2000 (IMT-2000), Code Division Multiple Access (CDMA) terminals, etc. increases. Doing.

As a camera module, an image sensor module using a Charge Coupled Device (CCD) or a Complementary Metal-Oxide-Semiconductor (CMOS) image sensor, which are basic components, is widely used. The image sensor is arranged on the upper part of the light sensing unit for generating and accumulating photocharges from the outside to implement a color image. Such color filter arrays (CFAs) are red (R), green (G) and blue (B), or yellow, magenta, and cyan. It consists of a branch collar. Typically, three colors of red (R), green (G), and blue (B) are frequently used in a color filter array of a CMOS image sensor.

Such an image sensor is a semiconductor device that converts an optical image into an electrical signal. As described above, a CCD and a CMOS image sensor have been developed and widely commercialized. A CCD is a device in which charge carriers are stored and transported in a capacitor while individual metal-oxide-silicon (MOS) capacitors are in close proximity to each other. On the other hand, a CMOS image sensor uses a CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits to make MOS transistors by the number of pixels, and uses the switching to detect an output sequentially. It is a device employing the method.

However, CCD has many disadvantages such as complicated driving method, high power consumption, high number of mask processes, complicated process, and difficult to implement one chip because signal processing circuit cannot be implemented in CCD chip. Recently, researches on the development of CMOS image sensors using sub-micron CMOS manufacturing techniques have been enthusiastically conducted to overcome the disadvantages of the CCD.

The CMOS image sensor forms an image by forming a photo diode and a MOS transistor in a unit pixel and sequentially detects a signal in a switching method. Since the CMOS manufacturing technology is used, the power consumption is low and the number of masks is approximately. The process is very simple compared to CCD process that requires 30 to 40 masks, and it is possible to make various signal processing circuits and one chip.

In general, the CMOS image sensor is composed of a light sensing unit for detecting light and a logic circuit unit for processing the light detected by the light sensing unit into an electrical signal and converting the data into an electric signal. Efforts are underway to increase this fill factor. However, there is a limit to this effort under a limited area since the logic circuit part cannot be removed essentially. Accordingly, in order to increase the light sensitivity, a condensing technology that changes the path of light incident to an area other than the light sensing unit and collects the light sensing unit has emerged. For this purpose, an image sensor forms a microlens on a color filter. I'm using the method.

1 is a circuit diagram illustrating a unit pixel of a general CMOS image sensor.

Referring to FIG. 1, a unit pixel of a CMOS image sensor includes one photo diode (PD) and four MOS transistors, and the four MOS transistors include a transfer transistor (Tx), a reset transistor (Rx), and a drive. It consists of a transistor MD and a selector transistor Sx. A load transistor Vb is formed outside the unit pixel to read an output signal. Unexplained reference 'Cfd' indicates the capacitance of the floating diffusion.

Hereinafter, a method of manufacturing a CMOS image sensor according to the prior art will be described with reference to FIGS. 2A to 2D. 2A to 2D, only one of a plurality of transistors of a photodiode, a transfer transistor, and a logic circuit unit is illustrated for convenience of description.

First, as shown in FIG. 2A, a logic region is defined as a region (hereinafter referred to as a logic region) and a region where a pixel including a light sensing unit is formed (hereinafter referred to as a pixel region). Provides a P ++ substrate 10 defined as a region where a photodiode is formed (hereinafter referred to as PD) and a region where a transfer transistor is formed (hereinafter referred to as Tx).

Subsequently, a p-epi layer is grown on the substrate 10.

Subsequently, a trench isolation (not shown) is formed by performing a shallow trench isolation (STI) process, and a channel stop region 11 is formed by performing a channel stop ion implantation process to form a trench. A device isolation film 12 is formed.

Subsequently, a well ion implantation process is performed to form the well region 13 for the logic element in the logic region, and p-type or n-type impurities are selectively implanted to control the threshold voltage, thereby forming a p-type or n-type region (not shown). To form.

Subsequently, as shown in FIG. 2B, the gate insulating layer 14 and the polysilicon layer 15 are sequentially formed on the substrate 10 and then etched to form the gate electrodes 16a and 16b in the logic region and the Tx region, respectively. To form.

Next, as illustrated in FIG. 2C, an n-ion implantation process using an n-ion implantation mask (not shown) is performed to form an n-diffusion layer 17 constituting a photodiode in the PD region.

Subsequently, a first p ⁰ ion implantation process using a p ⁰ ion implantation mask (not shown) is performed to form a p ⁰ diffusion layer 18 in the n− diffusion layer 17. At this time, the p ⁰ diffusion layer 18 is formed relatively thin.

Subsequently, an LDD ion implantation process using a lightly doped drain (LDD) ion implantation mask (not shown) is performed to form LDD regions 19a and 19b in the substrate 10 exposed to both sides of the gate electrodes 16a and 16b. do.

Subsequently, as shown in FIG. 2D, spacers 22a and 22b are formed on both side walls of the gate electrodes 16a and 16b, respectively. In this case, the spacers 22a and 22b have a stacked structure of the silicon oxide film 20 and the silicon nitride film 21. The manufacturing process is performed by sequentially forming the silicon oxide film 20 and the silicon nitride film 21. It is done by the process.

Meanwhile, spacers 22c are formed on both sidewalls of the cone defect structure layer 16c during the spacer process.

Subsequently, a source / drain ion implantation process using a source / drain ion implantation mask (not shown) is performed to relatively expose the logic region and floating diffusion region (hereinafter referred to as FD) exposed to both sides of the gate electrodes 16a and 16b. High concentration n + source / drain regions 23a and 23b are formed. At this time, the source / drain regions 23a and 23b are formed deeper than the LDD regions 19a and 19b.

Subsequently, a p ⁰ ion implantation process using a second p ⁰ ion implantation mask (not shown) is performed to form a p ^o diffusion layer 24 having a doping profile deeper than the p ⁰ diffusion layer 18 in the n − diffusion layer 17. .

Subsequently, a target temperature profile is diffused by performing a rapid temperature process (RTP) or a rapid temperature process (RTA) process to diffuse the p-type or n-type impurity ions implanted during the source / drain ion implantation process and the p ⁰ ion implantation process. which forms a source / drain region and the p-doped region ^0.

However, in the method of manufacturing the CMOS image sensor according to the related art described above, the polysilicon film 15 is not etched in the PD region during the dry etching process for forming the gate electrodes 16a and 16b as shown in FIG. 2B. Thus, a cone defect structure layer 16c is formed. The cone defect structure layer 16c is formed because the polysilicon film 15 is not etched in the PD region due to residues separated from the photoresist film used as an etching mask during the etching process of the polysilicon film 15. It is known.

As shown in FIG. 2B, the initial cone defect structure layer 16c has a small size, but as shown in FIG. 2D, spacers 22a and 22b are formed on both sidewalls of the subsequent gate electrodes 16a and 16b. During the process, spacers 22c are formed on both side walls of the cone defect structure layer 16c, thereby increasing their size. Accordingly, the second p ⁰ during the ion implantation process by the ion implantation act as a barrier layer in the region of the cone structure defect layer (16c) there are no ions are not implanted. Accordingly, the deficient region A in which no ions are implanted is present in the final p ⁰ doped region 24. The deficient region A is a portion that does not form a potential barrier against the dark current flowing from the surface, and is generated at the position where the particles are located, and serves as a passage for the dark current flowing from the surface of the substrate 10.

If such unwanted cone defect structure layer 16c is present with variation within a single chip, it greatly increases the dark bad pixels, and thus one of tens of millions to millions of pixels. Even if it turns out to be a bad pixel, it becomes a fail chip, which greatly affects the yield of the CMOS image sensor.

Accordingly, the present invention has been made to solve the above problems of the prior art, caused by the cone defect structure layer formed on the photodiode region after the etching process for forming the gate electrode for controlling the charge of the photodiode. It is an object of the present invention to provide a method for manufacturing a CMOS image sensor that can prevent deterioration of device characteristics.

According to an aspect of the present invention, there is provided a method of forming a gate electrode on a substrate on which a region in which a photodiode is to be formed is defined, forming a mask in which a region in which the photodiode is to be formed is opened; Performing a cleaning process using the mask to remove the cone defect structure layer formed on the substrate in the region where the photodiode is to be formed during the gate electrode forming process; and removing the photodiode in the region where the photodiode is to be formed. It provides a method for manufacturing a CMOS image sensor comprising the step of forming.

The washing step is carried out using a BOE solution.

The BOE solution uses a solution in which HF and NH ₄ F are mixed at 50: 1 to 300: 1.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

3A to 3D are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to a preferred embodiment of the present invention. 3A to 3E illustrate only a transfer transistor and a photodiode among the plurality of transistors in the pixel region and only one of the plurality of transistors in the logic region.

First, as shown in FIG. 3A, a logic circuit is defined as a region (hereinafter, referred to as a logic region) and a region in which a pixel including a light sensing unit is formed (hereinafter referred to as a pixel region). The region provides a p ++ substrate 110 defined as a region where a photodiode is formed (hereinafter referred to as PD) and a region where a transfer transistor is formed (hereinafter referred to as Tx).

Subsequently, a p-epitaxial layer (not shown) is grown on the p ++ substrate 110.

Subsequently, an STI process is performed to form a device isolation trench (not shown), a channel stop ion implantation process is performed to form a channel stop region 111, and a device isolation layer 112 is formed to fill the trench. In this case, the device isolation layer 112 is formed of an HDP oxide film or epitaxially grown polysilicon film having excellent buried characteristics.

Subsequently, the well ion implantation process is performed to form the well region 113 for the logic element in the logic region, and to selectively inject p-type or n-type impurities to adjust the threshold voltage, thereby forming a p-type or n-type region (not shown) To form.

Subsequently, gate electrodes 116a and 116b are formed in the logic region and the Tx region Tx, respectively. At this time, the gate electrodes 116a and 116b are formed in a stacked structure of the gate insulating film 114 and the polysilicon film 115. At this time, the cone defect structure layer 116c is formed in the PD region PD as in the prior art.

Subsequently, as shown in FIGS. 3B and 4, a photo process is performed to form a mask 117 in which all or part of the PD region PD is opened. 'A' shown represents an open area of the mask 117.

Subsequently, as shown in FIG. 3C, the cleaning process 118 using the mask 117 is performed to remove the exposed cone defect structure layer 116c (see FIG. 3B). In this case, the cleaning process 118 is performed using BOE (Buffered Oxide Etchant; a solution in which HF and NH ₄ F are mixed at 1:20 to 1: 300). For example, LAL (product name) and LL (product name) are used as BOE types.

Subsequently, a strip process is performed to remove the mask 117.

Subsequently, as shown in FIG. 3D, an n-ion implantation process using an n-ion implantation mask (not shown) is performed to form the n-diffusion layer 119 relatively deeply in the substrate 110 in the PD region. To form.

Then subjected to an ion implantation process using the first p ⁰ p ⁰ ion implantation mask (not shown) to form a p ⁰ diffusion layer 120 in the n- diffusion layer 119.

Next, an LDD ion implantation process using an LDD ion implantation mask (not shown) is performed to form LDD regions 121a and 121b in the substrate 110 exposed to both sides of the gate electrodes 116a and 116b.

Subsequently, spacers 124a and 124b are formed on both side walls of the gate electrodes 116a and 116b, respectively. In this case, the spacers 124a and 124b have a low pressure silicon oxide film 122 and a silicon nitride film 123 stacked structure, and the silicon oxide film 122 and the silicon nitride film 123 are sequentially formed and then etched back. Or it is formed through an etching process such as a blanket (blanket).

Next, a source / drain ion implantation process using a source / drain ion implantation mask (not shown) is performed to relatively high concentrations in the logic region and floating diffusion region (hereinafter referred to as FD) exposed to both sides of the gate electrodes 116a and 116b. Phosphorus n + source / drain regions 125a and 125b are formed. In this case, the source / drain regions 125a and 125b are formed deeper than the LDD regions 121a and 121b.

Meanwhile, n-type impurities are also doped into the gate electrodes 116a and 116b during the source / drain ion implantation process.

Subsequently, a second p ⁰ ion implantation process using a p ⁰ ion implantation mask (not shown) is performed to form a p ^o diffusion layer 126 having a doping profile deeper than the p ⁰ diffusion layer 120 in the n − diffusion layer 119. .

Subsequently, after removing the p ⁰ ion implantation mask through a strip process, RTP or RTA processes are performed to diffuse the p-type or n-type impurity ions implanted during the source / drain ion implantation process and the p ⁰ ion implantation process to obtain a target profile ( source and drain regions having a profile) and a p ⁰ doped region.

Subsequently, the CMOS image sensor is completed by sequentially performing subsequent processes such as a metal wiring process, a color filter forming process, and a microlens forming process through a known technique.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the cone defect structure layer formed in the PD region during the gate electrode forming process is oxidized and removed before the spacer process, thereby preventing the existence of the deficient region in the p ⁰ doped region. By blocking the inflow of dark current through the deficient region, it is possible to improve the dark current characteristics, thereby improving the characteristics of the device.

Claims (3)

Forming a gate electrode on the substrate on which a region in which the photodiode is to be formed is defined; Forming a mask in which a region in which the photodiode is to be formed is opened; Performing a cleaning process using the mask to remove the cone defect structure layer formed on the substrate in a region where the photodiode is to be formed during the gate electrode forming process; And Forming a photodiode in a region where the photodiode is to be formed Method of manufacturing a CMOS image sensor comprising a. The method of claim 1, The cleaning step is a method of manufacturing a CMOS image sensor to be carried out using a BOE solution. The method of claim 2, The BOE solution is a method of manufacturing a CMOS image sensor using a mixture of HF and NH ₄ F 1:20 ~ 1: 300.

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