JPH02271673A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02271673A JPH02271673A JP1094102A JP9410289A JPH02271673A JP H02271673 A JPH02271673 A JP H02271673A JP 1094102 A JP1094102 A JP 1094102A JP 9410289 A JP9410289 A JP 9410289A JP H02271673 A JPH02271673 A JP H02271673A
- Authority
- JP
- Japan
- Prior art keywords
- region
- source
- drain
- silicide
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 16
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 16
- 230000005611 electricity Effects 0.000 abstract description 8
- 230000003068 static effect Effects 0.000 abstract description 8
- 239000000463 material Substances 0.000 abstract description 6
- 239000012535 impurity Substances 0.000 description 7
- 239000010410 layer Substances 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 6
- 238000000137 annealing Methods 0.000 description 3
- 229910052736 halogen Inorganic materials 0.000 description 3
- 150000002367 halogens Chemical class 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置、詳しくはサリサイドTrを多数具
備した集積回路の出力部の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a structure of an output section of an integrated circuit including a large number of salicide transistors.
近年、半導体素子の微細化に伴い、ソース・ドレイン領
域を形成する不純物拡散層を極めて浅くつくりこむ必要
が出てきた。ところが不純物拡散層を浅くすることは、
ソース・ドレイン領域の高抵抗化につながり、Trの電
流駆動能力を著しく劣化させる原因となる。このような
問題を解決するために、ソース・ドレイン及びゲート電
極上に選択的にシリサイドを形成し、前述したソース・
ドレイン領域の抵抗を極めて低くした、いわゆるサリサ
イド構造のTrが提案された。In recent years, with the miniaturization of semiconductor devices, it has become necessary to make impurity diffusion layers that form source and drain regions extremely shallow. However, making the impurity diffusion layer shallow is
This leads to an increase in the resistance of the source/drain regions, causing a significant deterioration of the current driving ability of the transistor. In order to solve this problem, silicide is selectively formed on the source/drain and gate electrodes, and the above-mentioned source/drain
A transistor with a so-called salicide structure, which has an extremely low resistance in the drain region, has been proposed.
しかし、前述の従来技術、つまりサリサイドTrは、静
電気に対して極めて弱いという課題を有する。However, the above-mentioned conventional technology, that is, salicide Tr, has a problem of being extremely weak against static electricity.
一般に、集積回路の静電気耐性は、入出力部の静電気に
対する強さで決定される。入力部は保護抵抗等の手段に
より静電保護が行われるが、出力部は通常、静電保護は
行われない。Generally, the static electricity resistance of an integrated circuit is determined by the strength of the input/output parts against static electricity. The input section is protected against electrostatic discharge by means such as a protective resistor, but the output section is usually not protected against electrostatic discharge.
出力Trの静電気に対する強さは、配線材かららソース
、ドレイン端(ゲート電極側)までの抵抗により決定さ
れる。(この抵抗が小さいと、静電破壊を起こし易い。The strength of the output transistor against static electricity is determined by the resistance from the wiring material to the source and drain ends (gate electrode side). (If this resistance is small, electrostatic damage is likely to occur.
)
サリサイドTrはソース・ドレイン抵抗を極端に下げる
ために、静電気には弱くなる。) Since salicide transistors have extremely low source/drain resistance, they are susceptible to static electricity.
本発明は、このような課題を解決するもので、その目的
は、サリサイドTrを具備した集積回路の静電気耐性を
改善し、高品質な集積回路を提供することにある。The present invention solves these problems, and its purpose is to improve the electrostatic resistance of an integrated circuit equipped with a salicide transistor and provide a high-quality integrated circuit.
本発明の半導体装置は、サリサイドTrを多数具備した
集積回路において、前記集積回路の出力Trのドレイン
、ソースの両側にシリサイドを形成しない領域を設ける
ことを特徴とする。The semiconductor device of the present invention is characterized in that, in an integrated circuit including a large number of salicide transistors, regions in which no silicide is formed are provided on both sides of the drain and source of the output transistor of the integrated circuit.
以下図面に基づき、本発明の実施例を詳細に説明する。 Embodiments of the present invention will be described in detail below based on the drawings.
第1図(a)は、本発明による半導体装置を表わす断面
図、第1図(b3は平面図であって、101はP型St
基板、102は素子分離用酸化膜、103はゲート酸化
膜、104は高濃度リンがドープされた多結晶Stから
なるゲート電極、105は低濃度n型不純物拡散層、1
06はサイドウオールスペーサー、107は高濃度不純
物拡散層(ソース・ドレイン)、108はTiシリサイ
ド、109は層間絶縁用酸化膜、110は配線材料用A
jQである。FIG. 1(a) is a sectional view showing a semiconductor device according to the present invention, FIG. 1(b3 is a plan view, 101 is a P-type St
A substrate, 102 an oxide film for element isolation, 103 a gate oxide film, 104 a gate electrode made of polycrystalline St doped with high concentration phosphorus, 105 a low concentration n-type impurity diffusion layer, 1
06 is a side wall spacer, 107 is a high concentration impurity diffusion layer (source/drain), 108 is Ti silicide, 109 is an oxide film for interlayer insulation, 110 is A for wiring material
It is jQ.
尚、第1図は破線で示したように領域(I)と領域(n
)に分離される。領域(■)は内部のTrを表わし、領
域(1)は出力部のTrを表わす。In addition, in FIG. 1, as shown by the broken line, the area (I) and the area (n
). The area (■) represents the internal Tr, and the area (1) represents the output section Tr.
図で明らかなように領域(II)はソース・ドレイン領
域107上はすべてTiシリサイド108によりおおわ
れているが、領域(I)にはソース・ドレイン領域10
7上にTiシリサイド108が設けられていない領域を
有する。As is clear from the figure, in region (II), the source/drain regions 107 are all covered with Ti silicide 108, but in region (I), the source/drain regions 107 are covered with Ti silicide 108.
There is a region on which Ti silicide 108 is not provided.
次に本発明の半導体装置の製造方法について、簡単に示
す。Next, a method for manufacturing a semiconductor device according to the present invention will be briefly described.
1)101〜106は公知の技術を用いて、容易に形成
される。106を形成した後に、全面に100〜300
人の酸化膜を化学的気相成長法で形成する。1) 101 to 106 are easily formed using known techniques. After forming 106, apply 100 to 300 on the entire surface.
A human oxide film is formed using chemical vapor deposition.
2)AsあるいはP等の高濃度N型不純物をイオン注入
し、電気炉あるいはハロゲンランプにてアニールを行い
、ソース・ドレイン領域107を形成する。2) A high concentration N-type impurity such as As or P is ion-implanted, and annealing is performed in an electric furnace or a halogen lamp to form source/drain regions 107.
3)フォトレジストパターンを用い、前記領域(1)の
ソース・ドレイン領域の一部を残して前記100〜30
0Aの酸化膜を希)fFでエツチング除去する。3) Using a photoresist pattern, leave a part of the source/drain region in the region (1) and
Remove the 0A oxide film by etching with diluted FF.
4)全面にTiを400〜600人スパッタ法で形成し
た後に、ハロゲンランプを用い700℃前後でアニール
を行う。この時、ゲート電極104上、及びソース・ド
レイン領域107上にはTiシリサイドが形成されるが
、領域(I)では、ソース・ドレイン領域の一部に10
0〜300への酸化膜を残した部分にはTiシリサイド
は形成されない。4) After forming Ti on the entire surface by sputtering 400 to 600 times, annealing is performed at around 700° C. using a halogen lamp. At this time, Ti silicide is formed on the gate electrode 104 and the source/drain region 107, but in region (I), Ti silicide is formed on a part of the source/drain region.
Ti silicide is not formed in the portion where the oxide film of 0 to 300 is left.
また、前記素子分離用酸化膜102上、サイドウオール
スペーサー106上にもTiシリサイドは形成されない
。Furthermore, Ti silicide is not formed on the element isolation oxide film 102 or on the sidewall spacer 106.
5)過酸化水素・アンモニアの水溶液を用い前記未反応
のTiを選択除去する。5) Selectively remove the unreacted Ti using an aqueous solution of hydrogen peroxide and ammonia.
6)再びハロゲンランプを用い、800℃前後の温度で
アニールを行った後に、化学的気相成長法で層間絶縁用
酸化膜109を形成し、コンタクトホール形成後、配線
材料用1!110をスパッタ法で形成しバターニングを
行うことで本発明の半導体装置は完成する。6) After annealing at a temperature of around 800° C. using a halogen lamp again, an oxide film 109 for interlayer insulation is formed by chemical vapor deposition, and after forming a contact hole, a wiring material 1!110 is sputtered. The semiconductor device of the present invention is completed by forming the semiconductor device by a method and performing patterning.
以上述べたように、本発明によれば、配線材料とソース
・ドレイン端部間に十分な抵抗が得られるため、静電気
に対しては極めて強い構造を提供できるという効果を有
する。As described above, according to the present invention, sufficient resistance can be obtained between the wiring material and the source/drain ends, so that it is possible to provide an extremely strong structure against static electricity.
第1図(a)は本発明の半導体装置の断面図を示し、第
1図(b)は本発明の半導体装置の平面図を示す。
101 ・
102 ・
103 ・
104 ・
105 ・
P型Si基板
素子分離用酸化膜
ゲート酸化膜
ゲート電極
低濃度不純物拡散層
106 ・
107 ・
108・
109 ・
110 ・
サイドウオールスペーサー
高濃度不純物拡散層
Tiシリサイド
層間絶縁用酸化膜
配線材料用Ag
以上
出願人 セイコーエプソン株式会社
代理人 弁理士 鈴 木 喜三部(他1名)(I)
弓(す
算1回FIG. 1(a) shows a cross-sectional view of a semiconductor device of the present invention, and FIG. 1(b) shows a plan view of the semiconductor device of the present invention. 101 ・ 102 ・ 103 ・ 104 ・ 105 ・ P-type Si substrate element isolation oxide film gate oxide film gate electrode low concentration impurity diffusion layer 106 ・ 107 ・ 108 ・ 109 ・ 110 ・ sidewall spacer high concentration impurity diffusion layer between Ti silicide layers Oxide film for insulation Ag for wiring materials Applicant Seiko Epson Co., Ltd. Agent Patent attorney Kizobe Suzuki (1 other person) (I) Yumi (1 time in total)
Claims (1)
イドを形成したTrを多数具備した集積回路において、
前記集積回路の出力Trのドレイン、ソースの両側にシ
リサイドを形成しない領域を設けることを特徴とする半
導体装置。In an integrated circuit including a large number of transistors in which silicide is selectively formed in the gate electrode and source/drain regions,
A semiconductor device characterized in that regions in which no silicide is formed are provided on both sides of the drain and source of the output transistor of the integrated circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1094102A JP2773220B2 (en) | 1989-04-13 | 1989-04-13 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1094102A JP2773220B2 (en) | 1989-04-13 | 1989-04-13 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02271673A true JPH02271673A (en) | 1990-11-06 |
JP2773220B2 JP2773220B2 (en) | 1998-07-09 |
Family
ID=14101079
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1094102A Expired - Lifetime JP2773220B2 (en) | 1989-04-13 | 1989-04-13 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2773220B2 (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07142589A (en) * | 1993-11-22 | 1995-06-02 | Nec Corp | Semiconductor integrated circuit device and manufacture thereof |
US6455897B1 (en) | 2000-05-31 | 2002-09-24 | Seiko Epson Corporation | Semiconductor device having electrostatic discharge protection circuit |
US6459139B2 (en) | 1999-12-03 | 2002-10-01 | Seiko Epson Corporation | Semiconductor device and method of fabricating the same |
US6537884B1 (en) | 1998-09-07 | 2003-03-25 | Denso Corporation | Semiconductor device and method of manufacturing the same including an offset-gate structure |
US6600210B1 (en) | 1999-10-08 | 2003-07-29 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
EP1458033A2 (en) * | 2003-03-12 | 2004-09-15 | NEC Electronics Corporation | Semiconductor protection element, semiconductor device comprising the same and corresponding manufacturing methods |
US6831334B2 (en) | 2000-05-31 | 2004-12-14 | Seiko Epson Corporation | Semiconductor device having electrostatic protection circuit and method of fabricating the same |
US6861705B2 (en) | 2000-03-07 | 2005-03-01 | Seiko Epson Corporation | Driver circuits and methods for manufacturing driver circuits |
US7352031B2 (en) | 2002-05-28 | 2008-04-01 | Oki Electric Industry, Co., Ltd. | Electrostatic-breakdown-preventive and protective circuit for semiconductor-device |
US8035229B2 (en) | 2007-03-01 | 2011-10-11 | Panasonic Corporation | Semiconductor device |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005209792A (en) | 2004-01-21 | 2005-08-04 | Matsushita Electric Ind Co Ltd | Semiconductor device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5565470A (en) * | 1978-11-13 | 1980-05-16 | Toshiba Corp | Mos integrated circuit |
JPS6143464A (en) * | 1984-08-08 | 1986-03-03 | Hitachi Ltd | Semiconductor device |
JPH02273971A (en) * | 1989-03-13 | 1990-11-08 | Philips Gloeilampenfab:Nv | Semiconductor device having protective circuit |
-
1989
- 1989-04-13 JP JP1094102A patent/JP2773220B2/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5565470A (en) * | 1978-11-13 | 1980-05-16 | Toshiba Corp | Mos integrated circuit |
JPS6143464A (en) * | 1984-08-08 | 1986-03-03 | Hitachi Ltd | Semiconductor device |
JPH02273971A (en) * | 1989-03-13 | 1990-11-08 | Philips Gloeilampenfab:Nv | Semiconductor device having protective circuit |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07142589A (en) * | 1993-11-22 | 1995-06-02 | Nec Corp | Semiconductor integrated circuit device and manufacture thereof |
US6537884B1 (en) | 1998-09-07 | 2003-03-25 | Denso Corporation | Semiconductor device and method of manufacturing the same including an offset-gate structure |
US6600210B1 (en) | 1999-10-08 | 2003-07-29 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
US6459139B2 (en) | 1999-12-03 | 2002-10-01 | Seiko Epson Corporation | Semiconductor device and method of fabricating the same |
US6861705B2 (en) | 2000-03-07 | 2005-03-01 | Seiko Epson Corporation | Driver circuits and methods for manufacturing driver circuits |
US6831334B2 (en) | 2000-05-31 | 2004-12-14 | Seiko Epson Corporation | Semiconductor device having electrostatic protection circuit and method of fabricating the same |
US6455897B1 (en) | 2000-05-31 | 2002-09-24 | Seiko Epson Corporation | Semiconductor device having electrostatic discharge protection circuit |
US7352031B2 (en) | 2002-05-28 | 2008-04-01 | Oki Electric Industry, Co., Ltd. | Electrostatic-breakdown-preventive and protective circuit for semiconductor-device |
EP1458033A2 (en) * | 2003-03-12 | 2004-09-15 | NEC Electronics Corporation | Semiconductor protection element, semiconductor device comprising the same and corresponding manufacturing methods |
EP1458033A3 (en) * | 2003-03-12 | 2005-03-30 | NEC Electronics Corporation | Semiconductor protection element, semiconductor device comprising the same and corresponding manufacturing methods |
US7087999B2 (en) | 2003-03-12 | 2006-08-08 | Nec Electronics Corporation | Semiconductor protection element, semiconductor device and method for manufacturing same |
US7271097B2 (en) | 2003-03-12 | 2007-09-18 | Nec Electronics Corporation | Method for manufacturing a semiconductor protection element and a semiconductor device |
US8035229B2 (en) | 2007-03-01 | 2011-10-11 | Panasonic Corporation | Semiconductor device |
US8193608B2 (en) | 2007-03-01 | 2012-06-05 | Panasonic Corporation | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP2773220B2 (en) | 1998-07-09 |
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