KR100264209B1 - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR100264209B1 KR100264209B1 KR1019980020346A KR19980020346A KR100264209B1 KR 100264209 B1 KR100264209 B1 KR 100264209B1 KR 1019980020346 A KR1019980020346 A KR 1019980020346A KR 19980020346 A KR19980020346 A KR 19980020346A KR 100264209 B1 KR100264209 B1 KR 100264209B1
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- Prior art keywords
- gate
- forming
- layer
- insulating film
- salicide
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 20
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 15
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims abstract description 9
- 150000004767 nitrides Chemical class 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- 238000002844 melting Methods 0.000 claims description 6
- 230000008018 melting Effects 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 238000010438 heat treatment Methods 0.000 description 10
- 239000012535 impurity Substances 0.000 description 9
- 238000000151 deposition Methods 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 238000004151 rapid thermal annealing Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체장치의 제조방법에 관한 것으로서, 특히, 시트 저항(sheet resistance) 및 접촉 저항(contact resistance)을 감소시키도록 게이트 측벽에 살리사이드 형성이 가능한 절연막을 형성하거나 또는 콘택홀 등에서의 살리사이드 형성시 콘택홀의 벽을 이루는 절연층 사이에 역시 살리사이드 형성이 가능한 절연층을 개재시키므로서 살리사이드 형성 부위를 확장시킨 반도체장치의 살리사이드층 형성방법에 관한 것이다. 본 발명은 게이트절연막이 형성된 제 1 도전형의 반도체기판 상에 게이트절연막을 개재시켜 게이트를 형성하는 공정과, 게이트를 마스크로 사용하여 반도체기판에 제 2 도전형의 저농도영역을 형성하는 공정과, 게이트 표면을 포함하는 기판 전면에 제 1 절연막과 도전층 그리고 제 2 절연막을 차례로 형성하는 단계와, 제 2 절연막과 도전층과 제 1 절연막 그리고 게이트절연막을 게이트의 측면에 잔류시켜 측벽을 형성하는 단계와, 게이트 및 측벽을 마스크로 사용하여 반도체기판에 제 2 도전형의 고농도영역을 형성하는 단계와, 게이트와 측벽 그리고 고농도영역 상에 금속층을 형성하는 단계와, 금속층을 열처리하여 상기 게이트와 잔류한 도전층/제 1 절연막/게이트절연막의 노출된 표면 그리고 고농도영역 표면에 실리사이드층을 형성하는 단계를 포함하여 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, an insulating film capable of forming a salicide on a sidewall of a gate to reduce sheet resistance and contact resistance or forming a salicide in a contact hole or the like is provided. The present invention relates to a method for forming a salicide layer of a semiconductor device in which a salicide-forming portion is expanded by interposing an insulating layer capable of forming a salicide between insulating layers forming a wall of a contact hole. The present invention provides a process for forming a gate on a first conductive semiconductor substrate having a gate insulating film formed therebetween, forming a low concentration region of a second conductive type on a semiconductor substrate using the gate as a mask; Sequentially forming a first insulating film, a conductive layer, and a second insulating film on the entire surface of the substrate including the gate surface, and forming sidewalls by leaving the second insulating film, the conductive layer, the first insulating film, and the gate insulating film on side surfaces of the gate. And forming a high concentration region of a second conductivity type on the semiconductor substrate using the gate and the sidewall as a mask, forming a metal layer on the gate, the sidewall and the high concentration region, and heat treating the metal layer. Forming a silicide layer on the exposed surface of the conductive layer / first insulating film / gate insulating film and on the surface of the high concentration region. It achieved by also.
Description
본 발명은 반도체장치의 제조방법에 관한 것으로서, 특히, 시트 저항(sheet resistance) 및 접촉 저항(contact resistance)을 감소시키도록 게이트 측벽에 살리사이드 형성이 가능한 절연막을 형성하거나 또는 콘택홀 등에서의 살리사이드 형성시 콘택홀의 벽을 이루는 절연층 사이에 역시 살리사이드 형성이 가능한 절연층을 개재시키므로서 살리사이드 형성 부위를 확장시킨 반도체장치의 살리사이드층 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, an insulating film capable of forming a salicide on a sidewall of a gate to reduce sheet resistance and contact resistance or forming a salicide in a contact hole or the like is provided. The present invention relates to a method for forming a salicide layer of a semiconductor device in which a salicide-forming portion is expanded by interposing an insulating layer capable of forming a salicide between insulating layers forming a wall of a contact hole.
반도체장치가 고집적화됨에 따라 소오스 및 드레인영역으로 이용되는 불순물영역과 게이트의 폭이 감소되고 있다. 이에 따라, 반도체장치는 불순물영역의 접촉 저항 및 게이트의 시트 저항이 증가하여 동작 속도가 저하되는 문제점이 발생되었다.As semiconductor devices are highly integrated, the widths of impurity regions and gates used as source and drain regions are reduced. As a result, the semiconductor device has a problem in that an operating speed decreases due to an increase in contact resistance of an impurity region and sheet resistance of a gate.
그러므로, 반도체장치 내의 소자들의 배선을 알루미늄 합금 및 텅스텐 등의 저저항 물질로 형성하거나, 또는, 게이트와 같이 다결정실리콘으로 형성하는 경우에 실리사이드층을 형성하여 저항을 감소시킨다. 상기에서 다결정실리콘으로 형성된 게이트에 실리사이드층을 형성할 때 불순물영역의 표면에도 실리사이드층을 형성하여 접촉 저항을 감소시킨다.Therefore, when the wirings of the elements in the semiconductor device are formed of low-resistance materials such as aluminum alloy and tungsten, or formed of polycrystalline silicon such as a gate, a silicide layer is formed to reduce the resistance. When the silicide layer is formed on the gate formed of polycrystalline silicon, a silicide layer is also formed on the surface of the impurity region to reduce the contact resistance.
도 1a 내지 도 1d는 종래 기술에 따른 반도체장치의 제조공정도이다.1A to 1D are manufacturing process diagrams of a semiconductor device according to the prior art.
도 1a를 참조하면, P형의 반도체기판(11)의 소정 부분에 LOCOS(Local Oxidation of Silicon) 방법 등의 소자격리방법에 의해 필드산화막(13)을 형성하여 소자의 활성영역과 소자격리영역을 형성한다.Referring to FIG. 1A, a field oxide layer 13 is formed on a predetermined portion of a P-type semiconductor substrate 11 by a device isolation method such as a local oxide of silicon (LOCOS) method to form an active region and a device isolation region of a device. Form.
그리고 반도체기판(11)의 표면을 열산화하여 게이트산화막(15)을 형성한다. 그리고, 필드산화막(13) 및 게이트산화막(15)의 상부에 불순물이 도핑된 다결정실리콘을 증착하고 패터닝하여 게이트(17)를 한정한다. 게이트(17)를 마스크로 사용하여 반도체기판(11)에 아세닉(As) 또는 인(P) 등의 N형 불순물을 저농도로 이온 주입하여 LDD(Lightly Doped Drain) 구조를 형성하기 위한 저농도영역(19)을 형성한다.The surface of the semiconductor substrate 11 is thermally oxidized to form a gate oxide film 15. The gate 17 is defined by depositing and patterning polycrystalline silicon doped with impurities on the field oxide film 13 and the gate oxide film 15. Low concentration region for forming LDD (Lightly Doped Drain) structure by ion implanting N-type impurities such as asic (As) or phosphorus (P) into the semiconductor substrate 11 at low concentration using the gate 17 as a mask ( 19).
도 1b를 참조하면, 게이트(17)의 측면에 측벽(21)을 형성한다. 상기에서 측벽(21)은 반도체기판(11) 상에 게이트(17)를 덮도록 산화실리콘을 증착하고 반응성이온식각(Reactive Ion Etching : 이하, RIE라 칭함) 방법 등으로 에치백(etchback)하므로써 형성된다. 그리고, 게이트(17)와 측벽(21)을 마스크로 사용하여 반도체기판(11)에 아세닉(As) 또는 인(P) 등의 N형 불순물을 고농도로 이온 주입하여 소오스 및 드레인영역으로 이용되는 고농도영역(23)을 저농도영역(19)과 중첩되게 형성한다.Referring to FIG. 1B, the sidewall 21 is formed on the side of the gate 17. The side wall 21 is formed by depositing silicon oxide on the semiconductor substrate 11 to cover the gate 17 and etching back by a reactive ion etching (hereinafter referred to as RIE) method. do. Then, using the gate 17 and the sidewall 21 as a mask, the semiconductor substrate 11 is ion-implanted with a high concentration of N-type impurities such as an asic (As) or phosphorus (P) to serve as a source and a drain region. The high concentration region 23 is formed to overlap the low concentration region 19.
도 1c를 참조하면, 반도체기판(11) 및 필드산화막(13) 상에 게이트(17) 및 측벽(21)를 덮도록 Ti, W, Mo, Co, Ta 또는 Pt 등의 고융점 금속을 증착한 후 RTA(Rapid Thermal Annealing) 방법으로 2번의 열처리하여 게이트(17) 및 고농도영역(23)의 표면에만 자기 정렬된 실리사이드층(25)을 형성한다.Referring to FIG. 1C, a high melting point metal such as Ti, W, Mo, Co, Ta, or Pt is deposited on the semiconductor substrate 11 and the field oxide film 13 to cover the gate 17 and the sidewall 21. Thereafter, heat treatment is performed twice using a rapid thermal annealing (RTA) method to form a silicide layer 25 self-aligned only on the surfaces of the gate 17 and the high concentration region 23.
상기에서, 실리사이드층(25)은 750℃ 이하의 온도에서 1차 열처리하고 게이트(17) 및 고농도영역(23)의 표면에만 잔류하도록 필드산화막(13) 및 측벽(21) 상에 반응하지 않은 고융점금속을 에치 백하여 제거한 후, 다시, 게이트(17) 및 고농도영역(23) 상에 잔류하는 것을 850∼950℃의 온도에서 2차 열처리하므로써 형성된다.In the above, the silicide layer 25 is not thermally reacted on the field oxide film 13 and the sidewall 21 so as to be subjected to the first heat treatment at a temperature of 750 ° C. or lower and remain only on the surfaces of the gate 17 and the high concentration region 23. After the melting point metal is removed by etching back, the residue remaining on the gate 17 and the high concentration region 23 is formed by secondary heat treatment at a temperature of 850 to 950 캜.
상술한 바와 같이 종래 기술에서 실리사이드층은 고융점 금속을 증착한 후 RTA 방법으로 2번의 열처리하여 형성하는 데, 일차 열처리에서 금속들이 살리사이드가 형성 가능한 부위에만 잔류하게 되므로 소자의 크기가 축소됨에 따라 이차 열처리에서 완성되는 게이트 또는 콘택부위 등에서 살리사이드층의 쉬트저항(sheet resistance)이 증가하여 소자의 동작속도가 저하되는 문제점이 있다. 즉, 게이트의 폭이 작으면 1차 열처리된 실리사이드를 2차 열처리할 때 입자가 선폭 보다 크게 성장되지 않으므로 저항이 증가되는 문제점이 있었다.As described above, in the prior art, the silicide layer is formed by depositing a high melting point metal and then performing two heat treatments using an RTA method. As the size of the device is reduced, the metals remain only in the salicide-forming region in the first heat treatment. The sheet resistance of the salicide layer is increased in the gate or contact portion, which is completed by the secondary heat treatment, to reduce the operation speed of the device. That is, when the width of the gate is small, when the second heat treatment of the first heat-treated silicide does not grow larger than the line width, there is a problem that the resistance is increased.
따라서, 본 발명의 목적은 게이트측벽과 게이트 사이에 질화막과 도핑되지 않은 실리콘층을 추가로 형성하므로서 살리사이드의 형성면적을 증가시키거나, 또는 콘택홀 드에서의 벽면을 이루는 절연막 사이에 살리사이드 형성이 가능한 절연막을 형성하므로서 역시 살리사이드 형성 면적을 확장시켜 쉬트저항을 감소시키는 방법을 제공하는데 있다.Therefore, an object of the present invention is to form a nitride layer and an undoped silicon layer between the gate side wall and the gate to increase the formation area of the salicide, or to form the salicide between the insulating film forming the wall surface at the contact hold. The present invention also provides a method for reducing sheet resistance by forming a salicide layer, thereby expanding the salicide forming area.
상기 목적들을 달성하기 위한 본 발명의 일실시예에 따른 반도체장치의 제조방법은 게이트절연막이 형성된 제 1 도전형의 반도체기판 상에 게이트절연막을 개재시켜 게이트를 형성하는 공정과, 게이트를 마스크로 사용하여 반도체기판에 제 2 도전형의 저농도영역을 형성하는 공정과, 게이트 표면을 포함하는 기판 전면에 제 1 절연막과 도전층 그리고 제 2 절연막을 차례로 형성하는 단계와, 제 2 절연막과 도전층과 제 1 절연막 그리고 게이트절연막을 게이트의 측면에 잔류시켜 측벽을 형성하는 단계와, 게이트 및 측벽을 마스크로 사용하여 반도체기판에 제 2 도전형의 고농도영역을 형성하는 단계와, 게이트와 측벽 그리고 고농도영역 상에 금속층을 형성하는 단계와, 금속층을 열처리하여 상기 게이트와 잔류한 도전층/제 1 절연막/게이트절연막의 노출된 표면 그리고 고농도영역 표면에 실리사이드층을 형성하는 단계를 포함하여 이루어진다.A semiconductor device manufacturing method according to an embodiment of the present invention for achieving the above object is a step of forming a gate on the first conductive semiconductor substrate having a gate insulating film formed through the gate insulating film, using the gate as a mask Forming a low concentration region of a second conductivity type on a semiconductor substrate, sequentially forming a first insulating film, a conductive layer, and a second insulating film on the entire surface of the substrate including the gate surface; Forming a sidewall by leaving an insulating film and a gate insulating film on the side of the gate; forming a high concentration region of a second conductivity type on the semiconductor substrate using the gate and the sidewall as a mask; Forming a metal layer on the metal layer; and heat-treating the metal layer to obtain the gate and the remaining conductive layer / first insulating film / gate insulating film. It comprises the step of forming a silicide layer on a surface and submitted heavily doped region surface.
상기 목적들을 달성하기 위한 본 발명의 다른 실시예에 따른 반도체장치의 제조방법은 살리사이드층이 형성될 부위를 노출시키는 제 1 절연층이 형성된 반도체기판 위의 제 1 절연층 위에 제 2 절연층을 형성하는 단계와, 제 2 절연층 위에 제 3 절연층을 형성하는 단계와, 노출된 기판 표면을 포함하는 기판의 전면에 금속층을 형성하는 단계와, 금속층에 열처리를 실시하여 노출된 기판의 표면에 제 1 실리사이드층을 형성하고 동시에 노풀된 제 2 절연층의 측면에 제 2 실리사이드층을 형성하는 단계를 포함하여 이루어진다.A semiconductor device manufacturing method according to another embodiment of the present invention for achieving the above object is to provide a second insulating layer on the first insulating layer on the semiconductor substrate on which the first insulating layer is formed to expose the portion where the salicide layer is to be formed. Forming a third insulating layer on the second insulating layer, forming a metal layer on the front surface of the substrate including the exposed substrate surface, and heat-treating the metal layer on the exposed surface of the substrate. Forming a first silicide layer and simultaneously forming a second silicide layer on a side surface of the second insulated layer.
도 1a 내지 도 1c는 종래 기술에 따른 반도체장치의 제조공정 단면도1A to 1C are cross-sectional views of a manufacturing process of a semiconductor device according to the prior art
도 2a 내지 도 2b는 본 발명의 일 실시예에 따른 반도체장치의 제조공정 단면도2A through 2B are cross-sectional views illustrating a manufacturing process of a semiconductor device in accordance with an embodiment of the present invention.
도 3 은 본 발명의 다른 실시예에 따라 형성된 살리사이드의 단면구조도Figure 3 is a cross-sectional view of the salicide formed in accordance with another embodiment of the present invention
본 발명의 일실시예에서는 질화막과 도핑되지 아니한 실리콘층을 게이트 측벽과 게이트 사이에 추가로 개재시켜 살리사이드의 형성면적을 증가시켜 쉬트저항을 감소시킨다. PMOS 경우에 질화실리콘과 타이타늄이 직접 반응하여 살리사이드를 형성하지만, NMOS의 경우에는 타이타늄과 질화실리콘이 직접 반응하지는 아니하고 질화실리콘의 양면에 각각 형성된 게이트의 폴리실리콘과 도핑되지 않은 실리콘이 타이타늄과 반응하면서 형성되는 살리사이드가 이동하여 질화막상에서 만나며 연결된다.In an embodiment of the present invention, the nitride film and the undoped silicon layer are further interposed between the gate sidewall and the gate to increase the formation area of salicide to reduce the sheet resistance. In the case of PMOS, silicon nitride and titanium react directly to form salicide, but in the case of NMOS, titanium and silicon nitride do not directly react, but polysilicon and undoped silicon of gates formed on both sides of silicon nitride react with titanium. The salicide formed while moving moves to meet and connect on the nitride film.
본 발명의 다른 실시예에서는 살리사이드가 형성되지 아니할 부위에 중간막으로 질화막을 증착한 다음 살리사이드가 형성될 지역을 개방한 후 살리사이드 형성공정을 진행하면 노출된 중간막의 측면 부위에도 살리사이드가 형성된다.In another embodiment of the present invention, if a nitride film is deposited as an intermediate layer on a region where no salicide is to be formed, the salicide is formed on the side surface of the exposed intermediate layer by opening the region where the salicide is to be formed and then proceeding to the salicide formation process. do.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2b 본 발명에 따른 반도체장치의 제조공정도이다.2A to 2B are manufacturing process diagrams of a semiconductor device according to the present invention.
도 2a를 참조하면, P형의 반도체기판(21의 소정 부분에 LOCOS 방법 또는 STI (Shallow Trench Isolation) 등의 소자격리방법에 의해 필드산화막을 형성하여 소자의 활성영역과 소자격리영역을 형성한다.Referring to FIG. 2A, a field oxide film is formed on a predetermined portion of a P-type semiconductor substrate 21 by a device isolation method such as a LOCOS method or a shallow trench isolation (STI) to form an active region and a device isolation region of a device.
반도체기판(21)의 표면을 열산화하여 게이트산화막(22)을 형성한다. 그리고, 필드산화막 및 게이트산화막(22)의 상부에 불순물이 도핑된 다결정실리콘을 증착하고 패터닝하여 게이트(23)를 한정한다. 게이트(23)를 마스크로 사용하여 반도체기판(21)에 아세닉(As) 또는 인(P) 등의 N형 불순물을 저농도로 이온 주입하여 LDD 구조를 형성하기 위한 저농도영역(24)을 형성한다.The surface of the semiconductor substrate 21 is thermally oxidized to form a gate oxide film 22. The gate 23 is defined by depositing and patterning polycrystalline silicon doped with impurities on the field oxide film and the gate oxide film 22. A low concentration region 24 for forming an LDD structure is formed by ion implanting N-type impurities such as an asic (As) or phosphorus (P) into the semiconductor substrate 21 at low concentration using the gate 23 as a mask. .
그리고, 노출된 게이트(23) 표면과 게이트산화막(22) 표면에 질화막(25)을 증착하고 계속해서 도핑되지 아니한 실리콘층(26)을 증착하여 형성한 다음 다시 그(26) 위에 산화막(27)을 증착하여 형성한다.Then, the nitride film 25 is deposited on the exposed gate 23 surface and the gate oxide film 22 surface, and subsequently, an undoped silicon layer 26 is formed, and then the oxide film 27 is formed thereon. It is formed by depositing.
도 2b를 참조하면, 게이트(23)의 측면에 측벽(41)을 형성한다. 상기에서 측벽(41)은 산화막(27), 도핑되지 아니한 실리콘층(26), 질화막(26) 그리고 게이트산화막(22)을 동시에 에치백하여 기판(21) 표면이 노출되도록 한다. 상기에서 실리콘층(26)은 스퍼터링 방법 또는 CVD 방법으로 단결정, 다결정 또는 비정질 상태로 형성될 수 있다. 이때 질화막 대신 순수한 실리콘층을 사용할 수 있다.Referring to FIG. 2B, sidewalls 41 are formed on side surfaces of the gate 23. The side wall 41 is etched back at the same time to the oxide layer 27, the undoped silicon layer 26, the nitride layer 26 and the gate oxide layer 22 to expose the surface of the substrate 21. The silicon layer 26 may be formed in a single crystal, polycrystalline or amorphous state by a sputtering method or a CVD method. In this case, a pure silicon layer may be used instead of the nitride film.
그리고, 게이트(23)와 측벽(27) 등을 마스크로 사용하여 노출된 반도체기판(21)에 아세닉(As) 또는 인(P) 등의 N형 불순물을 고농도로 이온 주입하여 소오스 및 드레인영역으로 이용되는 고농도영역(28)을 저농도영역(24)과 중첩되게 형성한다.In addition, the source and drain regions are ion-implanted with high concentrations of N-type impurities such as an asic or phosphorus (P) to the exposed semiconductor substrate 21 using the gate 23 and the sidewalls 27 as a mask. The high concentration region 28 used as is formed to overlap with the low concentration region 24.
그 다음, 반도체기판(21) 전면에 게이트(23) 및 노출된 질화막(25)과 실리콘층(26) 표면 그리고 측벽(27) 등을 덮도록 스퍼터링 방법 또는 CVD 방법으로 Ti, W, Mo, Co, Ta 또는 Pt 등의 고융점 금속을 증착하여 금속층(도시안함)을 형성한다.Then, Ti, W, Mo, Co is applied by a sputtering method or a CVD method so as to cover the gate 23, the exposed nitride film 25, the silicon layer 26, the sidewalls 27, and the like on the entire surface of the semiconductor substrate 21. A high melting point metal such as Ta or Pt is deposited to form a metal layer (not shown).
그 다음 열처리를 실시하여 노출된 게이트(23) 표면과 그에 연장된 질화막(25)과 실리콘층(26)의 표면에 제 1 살리사이드층(29), 측벽(27) 하단 측면에 노출된 질화막(25)과 실리콘층(26)의 표면에 제 2 살리사이드층(30) 그리고 노출된 고농도영역(28)의 표면에 제 3 살리사이드층(31)을 동시에 형성한다.Then, the nitride film exposed to the lower side surface of the first salicide layer 29 and the sidewall 27 on the surface of the gate 23 exposed through the heat treatment, the nitride film 25 and the silicon layer 26 extended thereto ( A second salicide layer 30 is formed on the surface of the silicon layer 26 and the third salicide layer 31 is simultaneously formed on the exposed high concentration region 28.
상기에서, 실리사이드층(29, 30, 31)은 750℃ 이하의 온도에서 1차 열처리하고 반응하지 않은 고융점금속을 에치 백하여 제거한 후, 다시, 상기 부위상에 잔류하는 것을 850∼950℃의 온도에서 2차 열처리하므로써 형성된다.In the above, the silicide layer (29, 30, 31) is subjected to the first heat treatment at a temperature of 750 ℃ or less and etched back to remove the unreacted high melting point metal, and then to remain on the site of 850 ~ 950 ℃ It is formed by secondary heat treatment at temperature.
도 3 은 본 발명의 다른 실시예에 따라 형성된 살리사이드의 단면구조도이다.Figure 3 is a cross-sectional structural view of the salicide formed in accordance with another embodiment of the present invention.
도 3을 참조하면, 실리콘기판(31)에 살리사이드층이 형성될 부위를 노출시키는 산화막(32)이 형성되어 있고, 다시 그(32) 위에 질화막(33)이 위치하며 계속하여 산화막(34)이 형성되어 있다. 이때 살리사이드층(35, 36) 형성공정을 실시하면, 노출된 질화막(33) 표면과 노출된 기판(31) 표면에 각각 제 1 살리사이드층(36)과 제 2 살리사이드층(35)이 형성된다. 따라서 종래와 비교하여 살리사이드층이 제 1 살리사이드층(36) 만큼 확대되었다. 그리고 이때 질화막 대신 순수한 실리콘층을 사용할 수 있다.Referring to FIG. 3, an oxide film 32 is formed on the silicon substrate 31 to expose a portion where a salicide layer is to be formed, and the nitride film 33 is positioned on the 32, and the oxide film 34 continues. Is formed. In this case, when the salicide layers 35 and 36 are formed, the first salicide layer 36 and the second salicide layer 35 are formed on the exposed nitride film 33 and the exposed substrate 31, respectively. Is formed. Accordingly, the salicide layer is enlarged by the first salicide layer 36 in comparison with the prior art. In this case, a pure silicon layer may be used instead of the nitride film.
따라서, 본 발명은 살리사이드층의 형성면적의 증가로 소자의 크기가 축소되어도 안정적인 쉬트저항을 형성하므로서 소자의 동작속도를 개선시키는 장점이 있다.Therefore, the present invention has the advantage of improving the operation speed of the device by forming a stable sheet resistance even if the size of the device is reduced by increasing the formation area of the salicide layer.
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