JPH10256191A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing method by which a silicide layer having a low layer resistance can be formed without relying upon the line width of electrode wiring by suppressing the increase of the resistance values of silicide layers on a gate electrode, a source electrode, and a drain electrode. SOLUTION: A semiconductor manufacturing method includes a high-melting point metal forming process for depositing a metal having a high melting point on a semiconductor substrate 101, a rapid heat-treating process for forming a high-resistance silicide layer 403 having a desired high resistance value by performing rapid heat treatment on the high-melting point metallic film, a silicide layer forming process for only leaving the silicide layer 403 formed in the first rapid heat-treating process by selectively etching the unreacted or nitrized part of the high-melting point metallic film formed in the first rapid heat-treating process, and a second rapid heat-treating process for reducing the resistance of the silicide layer 403 by executing rapid heat treatment on the layer 403.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a method for manufacturing a semiconductor device,
In particular, for the purpose of reducing the resistance of the gate electrode and the source / drain electrode of a semiconductor device requiring miniaturization, self-alignment is performed on the gate electrode and the source electrode or the drain electrode using a silicide film containing a high melting point metal. Formed with a salicide structure that reduces resistance
The present invention relates to a method for manufacturing a semiconductor device such as an IC, an LSI, and an ASIC having an OS transistor.

[0003]

2. Description of the Related Art As a prior art of this type of semiconductor device manufacturing method, for example, a first prior art as shown in FIG. 8 is disclosed.

FIG. 8 is a sectional view of the device structure of a first prior art MOS FET having a salicide structure. FIG. 9 is a flow chart showing a manufacturing process flow of the salicide structure of the MOS FET shown in FIG.

In a first prior art for reducing the resistance of a source electrode / drain electrode (meaning a source electrode or a drain electrode) by using a salicide structure, a MOS transistor (that is, a MOS FET) shown in FIG. The manufacturing process for forming the salicide structure (see FIG. 9) is as follows.
This is a process for realizing miniaturization of a device size and high-speed operation in a semiconductor device which has been performed recently.

A first prior art is a MOS FE shown in FIG.
LDD (Lightly Doped Dr) for improving hot carrier resistance to ensure reliability of T itself
a), and a gate electrode and a source electrode / drain electrode are formed by silicide (Silici).
de) to reduce the resistance of the source electrode / drain electrode.
LICIDE: Self Aligned Silic
ide).

In the MOS FET of the first prior art, as shown in FIG. 9, a well 1 which functions as a substrate electrode of a MOS FET is formed on a semiconductor substrate formed of a silicon semiconductor single crystal, and then a LOCOS method is performed. The element isolation region 2 is formed by using an element isolation technique such as that described above, and thereafter, ion implantation for controlling the channel concentration of the MOS FET is performed, and thereafter, the gate oxide film 3 and the gate electrode 4 are formed ( Manufacturing process T1).

In the manufacturing process T1, when forming the gate oxide film 3 and the gate electrode 4, the gate electrode 4 is generally made of polycrystalline silicon alone.

In the manufacturing process T1, the gate oxide film 3
After the formation of the gate electrode 4, the impurity diffusion layer 5 having a relatively low concentration is formed by the ion implantation method using the gate electrode 4 as an implantation mask.

Here, in the case of an n-channel transistor, the conductivity type of the low-concentration impurity diffusion layer 5 is set to n-type, and in the case of a p-channel transistor, the conductivity type of the low-concentration impurity diffusion layer 5 is set to p-type. You.

Subsequent to the ion implantation in the manufacturing process T1, the sidewall insulating film 6 of the gate electrode 4 is formed by an insulating film such as a silicon oxide film formed by using a film forming means such as a thermal CVD method.
Is formed, and a high-concentration impurity diffusion layer 7 is formed in a self-aligning manner using a doping technique such as an ion implantation method using the sidewall insulating film 6, the gate electrode 4 and the element isolation region 2 as an implantation mask.

At the time of producing the high concentration impurity diffusion layer 7, the same high concentration impurity is also implanted into the gate electrode 4 in a self-aligned manner. In the case of an n-channel transistor, the conductivity type of the high-concentration impurity diffusion layer 7 is set to n-type, and in the case of a p-channel transistor, the conductivity type of the high-concentration impurity diffusion layer 7 is set to p-type.

Subsequent to the manufacturing process T1, the titanium (element symbol: T
A high melting point metal such as i) is deposited on the entire surface of the semiconductor substrate (manufacturing step T2), and the high melting point metal is reacted with silicon by a first rapid heat treatment step in a nitrogen atmosphere to form silicide (manufacturing step T3). Thereby, a relatively high-resistance silicide layer is formed (manufacturing step T3). The rapid thermal treatment is performed by using Rapid Thermal Anneal (R
TA) Means processing.

Subsequent to the manufacturing step T3, after the formation of a relatively high-resistance silicide layer, unreacted refractory metal and RTA are formed.
The nitride of the refractory metal nitrided during the processing is removed by etching (manufacturing step T4).

Similarly, since the unreacted refractory metal on the sidewall insulating film 6 and the nitride of the refractory metal nitrided during the first rapid heat treatment (the manufacturing step T3) are removed, the gate electrode 4 An insulation process with the source electrode / drain electrode is performed.

Further, a first rapid heat treatment step (manufacturing step T
3) and after the execution of the manufacturing step T4, a second rapid thermal processing step (manufacturing step T5) is performed, and the silicide layer 8 having a relatively low resistance is formed on the source electrode / drain electrode and on the gate electrode 4
Formed on top.

As described above, according to the first prior art, the source electrode / drain electrode and the gate electrode 4 are formed.
It is disclosed that the resistance of the MOS FET can be reduced, and the MOS FET can operate at high speed.

However, recent miniaturized MOS
For the FET structure (especially a thin line of 1 μm or less of the gate electrode and the source electrode / drain electrode), the first conventional technique has a problem that it is difficult to sufficiently perform silicidation. There was a technical problem that it was difficult to avoid the formation.

Hereinafter, such a technical problem of the first prior art will be briefly described by taking a salicide structure using titanium as an example.

In the first prior art, an impurity element for forming an electrode was introduced on the gate electrode 4 and the source / drain electrodes before the deposition of titanium (the manufacturing step T2).

For example, when arsenic is used as an impurity element to be introduced, arsenic having an impurity concentration of 2 × 10 ²⁰ cm ³ or more is contained in a silicon substrate or polycrystalline silicon in a first rapid heat treatment step (manufacturing step T3). When it is included, the silicidation is suppressed, and the C4 of the relatively high-resistance silicide layer (that is, TiSi2) is used.
The formation of nine phases becomes insufficient.

Also, due to the MOS FET fabrication process,
If some oxygen or carbon remains on the silicon surface or the polycrystalline silicon surface before titanium deposition, silicidation is suppressed during the execution of the first rapid heat treatment step (manufacturing step T3), and the relatively high silicidation described above is suppressed. Resistive silicide layer TiSi
2, the formation of the C49 phase becomes insufficient.

Due to the insufficient formation of the C49 phase of the silicide layer TiSi2, the phase of the relatively low-resistance silicide layer TiSi2 to the C54 phase in the second rapid thermal processing step (manufacturing step T5) is performed. Dislocations are also insufficient, and as a result, on the gate electrode and on the source electrode /
There has been a problem that a uniform C54 phase cannot be formed over the entire surface on the drain electrode.

A uniform silicide layer (TiSi 2) C5 over the entire surface of the gate electrode and the source electrode / drain electrode
The problem that the formation of four phases is not performed is particularly remarkable when the gate electrode and the source / drain electrodes are formed in a fine line of 1 μm or less.

The first reason is that the silicide layer (TiSi 2) C49 phase or the silicide layer (TiSi 2
2) It is considered that the particle size of the C54 phase is about 0.3 to 0.5 μm.

When a silicide layer having such a grain size characteristic is formed, if the phase transition to a silicide layer (TiSi 2) C54 phase is not sufficiently performed at a thickness of 1 μm or less, a line of a high-resistance silicide layer is formed. The ratio to the width increases, and as a result, the layer resistance (referred to as sheet resistance) increases.

As a second reason, it is conceivable that the silicide layer is made thinner in response to a demand for miniaturization of a MOS FET.

That is, a MOS of the generation in which the gate electrode and the source electrode / drain electrode are formed by fine lines of 1 μm or less.
In the FET structure, the junction depth of the diffusion layer on the source electrode / drain electrode must be reduced to 0.15 μm or less. The titanium silicide layer formed on such a shallow diffusion layer also needs to be thinned to a thickness of about 0.05 μm.

The titanium thin film deposited for the purpose of forming such a thin silicide layer has a thickness of about 30 nm. As the thinning proceeds, the silicidation becomes more difficult to occur. As a result, the silicide layer (T) in the first rapid heat treatment step (manufacturing step T3) is reduced.
The formation of the iSi2) C49 phase was also insufficient.

Due to the first and second reasons, in the method of manufacturing the salicide structure described in the first prior art, there is a technical problem that the resistance of the silicide layer in a fine wire of 1 μm or less is increased. Had issues.

A second prior art is disclosed as a technique for solving such a technical problem of the first prior art.

Next, a second prior art of a method of manufacturing a semiconductor device is shown in FIG.

A second prior art M disclosed in FIG.
5 is a flowchart of a manufacturing process of a salicide structure of an OS FET.

A second prior art disclosed in FIG. 10 (Japanese Patent Laid-Open No. 6-69156, filed on Aug. 1, 1992)
3rd, title of invention: method of manufacturing semiconductor integrated circuit device), the formation of source / drain electrodes, gate electrodes and sidewall insulating films of MOS FETs (manufacturing process P1)
Thereafter, a high melting point metal (titanium) is deposited on the semiconductor substrate (manufacturing step P2), and then a first rapid heat treatment step (manufacturing step P3) is performed to perform the heat treatment.

At this time, the first rapid heat treatment step (the manufacturing step P
3) is a first heat treatment step (S in manufacturing process P3) performed at a temperature of 600 ° C. to 700 ° C. in a nitriding atmosphere.
TEP1) and a second heat treatment step (S1 in the manufacturing process P3) performed at a temperature of 700 ° C. to 900 ° C. following the first heat treatment process (STEP 1 in the manufacturing process P3).
TEP2) (STEP2 in the manufacturing process P3).

After the first rapid heat treatment step (manufacturing step P3), a step of removing the unreacted high melting point metal and the nitride of the high melting point metal generated by the heat treatment is performed to form the gate electrode and the source electrode / drain. Electrode insulation processing is performed (manufacturing process P4).

Further, following the insulation treatment of the gate electrode and the source electrode / drain electrode (manufacturing step P4), the resistance of the silicide layer formed on the gate electrode and the source electrode / drain electrode is sufficiently reduced. Then, a second rapid heat treatment step (manufacturing step P5) is performed. The second
Is about 800 ° C. in the rapid heat treatment step (manufacturing step P5).

In the method for manufacturing a salicide structure using such a second conventional technique (manufacturing steps P1 to P5), a first heat treatment step (manufacturing step) is performed in a nitriding atmosphere at a temperature of 600 ° C. to 700 ° C. STEP1 in P3)
Then, silicon and titanium on the source / drain electrodes are reacted with each other and polycrystalline silicon and titanium on the gate electrode are reacted with each other to form a relatively high-resistance silicide layer. Is similar to the first prior art.

In the second prior art, further, in the first rapid heat treatment step (manufacturing step P3), a second heat treatment step at a temperature of 700 ° C. to 900 ° C. (ST in the manufacturing step P3) is performed.
EP2) is executed. By performing such a second heat treatment process (STEP 2 in the manufacturing process P3), the thin wires of the gate electrode and the source electrode / drain electrode which are insufficiently silicided in the first heat treatment process (STEP 1 in the manufacturing process P3) Is characterized in that sufficient silicidation is promoted.

In other words, by performing such a second heat treatment step (STEP 2 in the manufacturing step P3), the thin silicide layer of the gate electrode and the source / drain electrode, which is considered difficult in the first prior art, is formed. It is disclosed that high resistance can be suppressed.

In order to solve the technical problem of the first prior art, the second prior art is compared with a heat treatment at 600 ° C. to 700 ° C. in the first rapid heat treatment step (manufacturing step P3). High resistance silicide layer (TiSi
2) First heat treatment step for forming C49 phase (manufacturing step P
3), and following the first heat treatment step (STEP1 in the manufacturing step P3), the thin wires of the gate electrode and the source / drain electrode with insufficient silicidation are heated to 700 ° C. to 900 ° C. Second heat treatment step for performing heat treatment (STEP in manufacturing process P3)
A technique for performing 2) to promote sufficient silicidation is disclosed.

[0042]

However, the second prior art has a relatively high resistance silicide layer (TiSi2).
C49 phase relatively low resistance silicide layer (TiSi2)
It is thought that the phase transition to C54 phase is promoted.
Since the heat treatment is performed only in the temperature range substantially equal to that of the prior art, the formation of the relatively high-resistance silicide layer (TiSi2) C49 phase becomes insufficient as in the first prior art. it is conceivable that.

Due to the insufficient formation of the silicide layer (TiSi 2) C49 phase, the salicide structure manufacturing method described in the second prior art, as in the first prior art, has a thickness of not more than 1 μm. It is considered that the technical problem that the resistance of the silicide layer in the fine wire is increased has not been sufficiently solved. Further, in the second prior art, a step of removing the unreacted refractory metal and the nitride of the refractory metal shown in FIG. 10 (manufacturing step P4).
In this case, there was a technical problem that it was considered difficult to insulate the gate electrode and the source electrode / drain electrode on the side wall insulating film 6 (see FIG. 8).

Among the patent publications of the second prior art, the inventors of the present invention disclose a first heat treatment step (manufacturing step P3) of a first rapid heat treatment step (manufacturing step P3) on sidewall insulating film 6. According to the heat treatment of 600 ° C. to 700 ° C.), the minute titanium oxide film and the titanium nitride film are laminated on the side wall insulating film 6, so that the second heat treatment step (STEP 2 in the manufacturing step P3) is performed. 700 ° C-9
In the heat treatment at 00 ° C., the silicon element diffuses from the gate electrode or the source electrode / drain electrode, and a silicide layer is formed on the side wall insulating film 6, and the insulating properties of the gate electrode and the source electrode / drain electrode are not ensured. Such problems will not occur.

However, since the titanium film remains on the side wall insulating film 6 during the heat treatment at 700 ° C. to 900 ° C. in the second heat treatment step (STEP 2 in the manufacturing process P3), the side wall insulating film 6 Due to oxygen being supplied from a certain silicon oxide film, the side wall insulating film 6
It is expected that the upper titanium oxide film contains a high concentration of oxygen and has a relatively large thickness.

The titanium oxide film formed by the second heat treatment step (STEP 2 in the production step P3) in the first rapid heat treatment step (the production step P3) has the following unreacted refractory metal and high In the step of removing the nitride of the melting point metal (manufacturing step P4), it is considered that it is difficult to remove by etching, and as a result, it is difficult to insulate the gate electrode and the source / drain electrodes. There was a technical problem of getting lost.

An object of the present invention is to solve such a conventional problem. In particular, the present invention has a salicide structure.
An object of the present invention is to provide a method for manufacturing a semiconductor device capable of reducing the resistance of a gate electrode and a source electrode / drain electrode in an OSFET.

That is, in the fine gate electrode and the source electrode / drain electrode having a salicide structure of 1 μm or less, the resistance of the silicide layer on the gate electrode and the source electrode / drain electrode is suppressed from increasing, and the line of the electrode wiring is suppressed. It is an object of the present invention to provide a method for manufacturing a semiconductor device for forming a salicide structure capable of realizing a silicide layer having a low layer resistance without depending on a width.

It is another object of the present invention to provide a method of manufacturing a semiconductor device for forming a salicide structure capable of securing insulation of a gate electrode and a source electrode / drain electrode.

Further, by realizing low resistance of the silicide layer on the gate electrode and the source electrode / drain electrode, a MOS FET which is required to be miniaturized so that the minimum device size becomes 0.5 μm or less. On the other hand, it is an object of the present invention to provide a method of manufacturing a semiconductor device for forming a salicide structure capable of realizing sufficient speed performance (specifically, high speed switching characteristics).

[0051]

According to a first aspect of the present invention, there is provided a salicide structure in which a gate electrode and a source electrode or a drain electrode are self-aligned and have a low resistance using a silicide film containing a high melting point metal. In the method for manufacturing a semiconductor device having a MOS transistor having a MOS transistor formed thereon, a high melting point metal forming step of depositing the high melting point metal on the semiconductor substrate 101, and the high melting point metal film deposited in the high melting point metal forming step To form a high resistance silicide layer 403 having a desired high resistance value
A first rapid thermal processing step, and selectively removing the high-melting metal film or the nitrided high-melting metal film that has not reacted in the rapid thermal processing by etching. A silicide layer forming step of leaving only the high-resistance silicide layer 403 formed in the heat treatment step, and a rapid heat treatment performed on the high-resistance silicide layer 403 formed in the first rapid heat treatment step to perform the high-resistance silicide layer 403. A method for manufacturing a semiconductor device, comprising: a second rapid heat treatment step for reducing the resistance of 403.

According to the first aspect of the present invention, the amorphous silicide layer is grown by performing high-resistance polycrystallization in the first rapid heat treatment step in the process of manufacturing the salicide structure 11. As a nucleus, a relatively high-resistance high-melting-point metal silicide can be formed uniformly, relatively finely, and relatively easily.

The refractory metal silicide thus formed is easily transformed into a relatively low-resistance refractory metal silicide in a second rapid heat treatment step which is a step subsequent to the first rapid heat treatment step. This has the effect of being able to perform.

According to this, the MOS of the salicide structure 11 is formed.
There is an effect that the resistance of the gate electrode 104 and the source electrode / drain electrode in the FET can be reduced.

As a result, the layer resistance of the gate electrode 104 and the thin line of the source electrode / drain electrode of 1 μm or less can be sufficiently reduced. Accordingly, the increase in the layer resistance of the thin wire as seen in the first prior art is suppressed, the resistance of the gate electrode 104 and the source electrode / drain electrode can be reduced, the parasitic resistance is reduced, and the fineness is reduced. M
There is an effect that the speed performance of the OS FET can be improved.

That is, 1 μm having the salicide structure 11
In the following minute gate electrode 104 and source electrode / drain electrode,
This has the effect of suppressing the increase in the resistance of the silicide layer on the drain electrode, and forming the salicide structure 11 capable of realizing a silicide layer having a low layer resistance without depending on the line width of the electrode wiring.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the high melting point metal forming step comprises depositing the high melting point metal on the semiconductor substrate 101 by a sputtering method. A method of manufacturing a semiconductor device.

According to the invention described in claim 2, according to claim 1
The same effect as the effect described in (1) is obtained.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the second aspect, the first rapid heat treatment step includes performing an amorphization process on the silicide layer to form an amorphous layer. A method for manufacturing a semiconductor device, comprising an amorphization step of forming a silicide layer.

According to the invention described in claim 3, according to claim 2
In addition to the effects described in (1), by performing the amorphization step of the first rapid heat treatment step in the manufacturing process of the salicide structure 11, the deposited refractory metal film and the polycrystalline This has the effect that a relatively amorphous silicide layer can be formed at the interface between silicon and the silicon substrate 101 constituting the source electrode / drain electrode.

Thereafter, by performing the high-resistance polycrystallizing step of the first rapid thermal processing step, the amorphous silicide layer formed in the amorphizing step is used as a growth nucleus to form a relatively high-resistance polycrystalline layer. A high refractory metal silicide can be formed uniformly, relatively finely and relatively easily.

The refractory metal silicide thus formed is easily transformed into a relatively low-resistance refractory metal silicide in a second rapid heat treatment step which is a step subsequent to the first rapid heat treatment step. This has the effect of being able to perform.

According to this, the MOS of the salicide structure 11 is formed.
There is an effect that the resistance of the gate electrode 104 and the source electrode / drain electrode in the FET can be reduced.

As a result, the layer resistance of the gate electrode 104 and the thin line of the source electrode / drain electrode of 1 μm or less can be sufficiently reduced. Accordingly, the increase in the layer resistance of the thin wire as seen in the first prior art is suppressed, the resistance of the gate electrode 104 and the source electrode / drain electrode can be reduced, the parasitic resistance is reduced, and the fineness is reduced. M
There is an effect that the speed performance of the OS FET can be improved.

That is, 1 μm having the salicide structure 11
In the following minute gate electrode 104 and source electrode / drain electrode,
This has the effect of suppressing the increase in the resistance of the silicide layer on the drain electrode, and forming the salicide structure 11 capable of realizing a silicide layer having a low layer resistance without depending on the line width of the electrode wiring.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to the third aspect, the first rapid heat treatment step includes a step of performing a polycrystallization treatment and a high resistance treatment on the amorphous silicide layer. A high-resistance polycrystallization step of increasing the resistance of the amorphous silicide layer to generate the high-resistance silicide layer 403.

According to the invention described in claim 4, according to claim 3,
In addition to the effects described in (1), by performing the amorphization step of the first rapid heat treatment step in the manufacturing process of the salicide structure 11, the deposited refractory metal film and the polycrystalline This has the effect that a relatively amorphous silicide layer can be formed at the interface between silicon and the silicon substrate 101 constituting the source electrode / drain electrode.

After that, the amorphous silicide layer formed in the amorphization step is formed by performing a polycrystallizing process of the amorphous silicide layer and a high resistance polycrystallization process for increasing the resistance. With growth as the nucleus of growth, a relatively high-resistance refractory metal silicide is formed uniformly, relatively finely and relatively easily.

The refractory metal silicide thus formed is easily transformed into a relatively low-resistance refractory metal silicide in a second rapid heat treatment step which is a step subsequent to the first rapid heat treatment step. This has the effect of being able to perform.

According to this, the MOS of the salicide structure 11 is formed.
There is an effect that the resistance of the gate electrode 104 and the source electrode / drain electrode in the FET can be reduced.

As a result, the layer resistance of the gate electrode 104 and the thin line of the source electrode / drain electrode of 1 μm or less can be sufficiently reduced. Accordingly, the increase in the layer resistance of the thin wire as seen in the first prior art is suppressed, the resistance of the gate electrode 104 and the source electrode / drain electrode can be reduced, the parasitic resistance is reduced, and the fineness is reduced. M
There is an effect that the speed performance of the OS FET can be improved.

That is, 1 μm having the salicide structure 11
In the following minute gate electrode 104 and source electrode / drain electrode,
This has the effect of suppressing the increase in the resistance of the silicide layer on the drain electrode, and forming the salicide structure 11 capable of realizing a silicide layer having a low layer resistance without depending on the line width of the electrode wiring.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourth aspect, the first rapid thermal processing step includes the step of performing the amorphizing step to perform the amorphizing. After forming the amorphous silicide layer and performing the amorphizing step, the high-resistance polycrystallizing step is performed on the amorphous silicide layer to form a polycrystalline and high-resistance high-resistance silicide layer. A method for manufacturing a semiconductor device, including a step of forming 403.

According to the invention set forth in claim 5, according to claim 4,
In addition to the effects described in (1), by performing the amorphization step of the first rapid heat treatment step in the manufacturing process of the salicide structure 11, the deposited refractory metal film and the polycrystalline This has the effect that a relatively amorphous silicide layer can be formed at the interface between silicon and the silicon substrate 101 constituting the source electrode / drain electrode.

Thereafter, the amorphous silicide layer formed in the amorphization step is formed by performing a high-resistance polycrystallization step for polycrystallizing the amorphous silicide layer and increasing the resistance. With growth as the nucleus of growth, a relatively high-resistance refractory metal silicide is formed uniformly, relatively finely and relatively easily.

The thus formed refractory metal silicide easily undergoes a phase transition to a relatively low-resistance refractory metal silicide in a second rapid heat treatment step subsequent to the first rapid heat treatment step. The effect that it becomes possible to do it is produced.

According to this, the MOS of the salicide structure 11 is formed.
There is an effect that the resistance of the gate electrode 104 and the source electrode / drain electrode in the FET can be reduced.

As a result, the layer resistance is sufficiently reduced even in the fine lines of 1 μm or less of the gate electrode 104 and the source / drain electrodes. Accordingly, the increase in the layer resistance of the thin wire as seen in the first prior art is suppressed, the resistance of the gate electrode 104 and the source electrode / drain electrode can be reduced, the parasitic resistance is reduced, and the fineness is reduced. M
There is an effect that the speed performance of the OS FET can be improved.

That is, 1 μm having the salicide structure 11
In the following minute gate electrode 104 and source electrode / drain electrode,
This has the effect of suppressing the increase in the resistance of the silicide layer on the drain electrode, and forming the salicide structure 11 capable of realizing a silicide layer having a low layer resistance without depending on the line width of the electrode wiring.

The invention described in claim 6 is the invention according to claim 3 or 5
In the method of manufacturing a semiconductor device according to the above, the amorphizing step includes performing the rapid heat treatment on the refractory metal film at a temperature of 400 ° C. or more and 550 ° C. or less to perform the amorphizing treatment of the silicide layer. Executing the step of producing the amorphous silicide layer.

According to the invention described in claim 6, according to claim 3,
Or in addition to the effect described in 5, the amorphizing step of the first rapid heat treatment step in the manufacturing process of the salicide
By running at a relatively low temperature of 0 ° C to 550 ° C,
A relatively amorphous silicide layer can be formed at the interface between the deposited refractory metal film and the polycrystalline silicon constituting the gate electrode 104 and the silicon substrate 101 constituting the source / drain electrodes. This has the effect.

Further, by performing the amorphizing step of the first rapid heat treatment step at a relatively low temperature of 400 ° C. to 550 ° C.,
There is an effect that an amorphous high-melting-point metal silicide layer can be formed without forming relatively high-resistance high-melting-point metal silicide which is easily formed at 600 ° C. or higher.

Thereafter, the amorphous silicide layer formed in the amorphization step is formed by performing a high-resistance polycrystallization step for polycrystallizing the amorphous silicide layer and increasing the resistance. With growth as the nucleus of growth, a relatively high-resistance refractory metal silicide is formed uniformly, relatively finely and relatively easily.

The refractory metal silicide thus formed is easily transformed into a relatively low-resistance refractory metal silicide in a second rapid heat treatment step, which is a subsequent step following the first rapid heat treatment step. The effect that it becomes possible to do it is produced.

According to this, the MOS of the salicide structure 11 is formed.
There is an effect that the resistance of the gate electrode 104 and the source electrode / drain electrode in the FET can be reduced.

As a result, the layer resistance of the gate electrode 104 and the thin line of the source electrode / drain electrode of 1 μm or less can be sufficiently reduced. Accordingly, the increase in the layer resistance of the thin wire as seen in the first prior art is suppressed, the resistance of the gate electrode 104 and the source electrode / drain electrode can be reduced, the parasitic resistance is reduced, and the fineness is reduced. M
There is an effect that the speed performance of the OS FET can be improved.

That is, 1 μm having the salicide structure 11
In the following minute gate electrode 104 and source electrode / drain electrode,
This has the effect of suppressing the increase in the resistance of the silicide layer on the drain electrode, and forming the salicide structure 11 capable of realizing a silicide layer having a low layer resistance without depending on the line width of the electrode wiring.

The invention according to claim 7 is the invention according to claim 3 or 5
In the method of manufacturing a semiconductor device according to the above, the amorphizing step includes performing the rapid heat treatment on the refractory metal film at a temperature of 400 ° C. or more and 550 ° C. or less in a nitrogen gas atmosphere to remove the silicide layer. A method for producing the amorphous silicide layer by performing a crystallization process.

According to the invention of claim 7, according to claim 3,
Or In addition to the effect described in 5, the heat treatment at a relatively low temperature in the amorphizing step of the first rapid heat treatment step and the heat treatment at a relatively high temperature in the high resistance polycrystallization step are performed in a nitrogen atmosphere. As a result, the amorphization step and the high-resistance polycrystallization step can be performed without replacing the atmosphere gas.
This has the effect of improving the throughput of the first rapid heat treatment step. It is desirable that such a high-resistance polycrystallization process be performed in a nitrogen atmosphere because, during heat treatment, silicon diffuses from the polycrystalline silicon forming the gate electrode 104 and the silicon substrate 101 forming the source / drain electrodes. In order to suppress the formation of a titanium silicide layer on the sidewall insulating film 106, it is considered that titanium is nitrided from the titanium surface.

The first step in the process of manufacturing the salicide structure 11 is as follows.
Amorphizing step in the rapid heat treatment step of 400 ° C. to 550
By performing the heat treatment at a relatively low temperature of about .degree. C. in a nitrogen gas atmosphere, the deposited high melting point metal film and the gate electrode
This has the effect that a relatively amorphous silicide layer can be formed at the interface between the polycrystalline silicon constituting the semiconductor and the silicon substrate 101 constituting the source / drain electrodes.

Further, by performing the amorphizing step of the first rapid heat treatment step at a relatively low temperature of 400 ° C. to 550 ° C.,
There is an effect that an amorphous high-melting-point metal silicide layer can be formed without forming relatively high-resistance high-melting-point metal silicide which is easily formed at 600 ° C. or higher.

Thereafter, the amorphous silicide layer formed in the amorphizing step is formed by performing a poly-crystallizing process for the amorphous silicide layer and a high-resistance poly-crystallizing step for increasing the resistance. With growth as the nucleus of growth, a relatively high-resistance refractory metal silicide is formed uniformly, relatively finely and relatively easily.

The refractory metal silicide thus formed is easily phase-transformed to a relatively low-resistance refractory metal silicide in a second rapid heat treatment step which is a subsequent step following the first rapid heat treatment step. The effect that it becomes possible to do it is produced.

According to this, the MOS of the salicide structure 11 is formed.
There is an effect that the resistance of the gate electrode 104 and the source electrode / drain electrode in the FET can be reduced.

As a result, the layer resistance of the gate electrode 104 and the thin line of the source electrode / drain electrode of 1 μm or less can be sufficiently reduced. Accordingly, the increase in the layer resistance of the thin wire as seen in the first prior art is suppressed, the resistance of the gate electrode 104 and the source electrode / drain electrode can be reduced, the parasitic resistance is reduced, and the fineness is reduced. M
There is an effect that the speed performance of the OS FET can be improved.

That is, 1 μm having the salicide structure 11
In the following minute gate electrode 104 and source electrode / drain electrode,
This has the effect of suppressing the increase in the resistance of the silicide layer on the drain electrode, and forming the salicide structure 11 capable of realizing a silicide layer having a low layer resistance without depending on the line width of the electrode wiring.

The invention described in claim 8 is the invention according to claim 3 or 5
In the method of manufacturing a semiconductor device according to the above, in the amorphizing step, the rapid heat treatment is performed on the refractory metal film in an argon gas atmosphere at a temperature of 400 ° C. or more and 550 ° C. or less to form the non-silicon layer. A method for producing the amorphous silicide layer by performing a crystallization process.

According to the invention described in claim 8, according to claim 3,
Or in addition to the effect described in 5, the relatively low-temperature heat treatment of the amorphization step of the first rapid heat treatment step is performed in an argon gas atmosphere, and the relatively high-temperature heat treatment of the high-resistance polycrystallization step is performed. By performing in a nitrogen atmosphere, the titanium surface is not nitrided at all during the relatively low-temperature heat treatment in the amorphization process, and the titanium surface is not treated at the relatively high-temperature heat treatment stage in the high-resistance polycrystallization process for the first time. Since the nitridation of the alloy begins, the effect of slightly promoting the formation of the titanium silicide (TiSi2) C49 phase is obtained.

Accordingly, the titanium silicide (TiSi2) C54 phase is sufficiently formed in the second rapid heat treatment step, and the layer resistance of the titanium silicide layer in the fine wire is reduced.

Also, since the heat treatment at 500 ° C. is performed in an argon gas atmosphere, there is a concern that titanium silicide may be formed on the sidewall insulating film 106 by diffusion of silicon from the gate electrode 104 and the source / drain electrodes. 5
Since the treatment is performed at a relatively low temperature of 00 ° C., the growth rate is extremely slow, and an effect is obtained that the insulation can be sufficiently performed at the time of etching.

Further, the amorphizing step of the first rapid heat treatment step in the process of manufacturing the salicide structure 11 is performed at 400 ° C. to 55 ° C.
By performing a relatively low temperature heat treatment at 0 ° C. in an argon gas atmosphere that is inert and easily obtains high purity, the deposited high melting point metal film, the polycrystalline silicon constituting the gate electrode 104 and the source electrode / drain A relatively amorphous silicide layer is formed with high purity at the interface with the silicon substrate 101 constituting an electrode.

Thereafter, the amorphous silicide layer formed in the amorphization step is formed by performing a high-resistance polycrystallization step for polycrystallizing the amorphous silicide layer and increasing the resistance. With growth as the nucleus of growth, a relatively high-resistance refractory metal silicide is formed uniformly, relatively finely and relatively easily.

The refractory metal silicide thus formed is easily transformed into a relatively low-resistance refractory metal silicide in a second rapid heat treatment step, which is a subsequent step following the first rapid heat treatment step. The effect that it becomes possible to do it is produced.

According to this, the MOS of the salicide structure 11 is formed.
There is an effect that the resistance of the gate electrode 104 and the source electrode / drain electrode in the FET can be reduced.

As a result, the layer resistance of the gate electrode 104 and the thin line of the source electrode / drain electrode of 1 μm or less can be sufficiently reduced. Accordingly, the increase in the layer resistance of the thin wire as seen in the first prior art is suppressed, the resistance of the gate electrode 104 and the source electrode / drain electrode can be reduced, the parasitic resistance is reduced, and the fineness is reduced. M
There is an effect that the speed performance of the OS FET can be improved.

That is, 1 μm having the salicide structure 11
In the following minute gate electrode 104 and source electrode / drain electrode,
This has the effect of suppressing the increase in the resistance of the silicide layer on the drain electrode, and forming the salicide structure 11 capable of realizing a silicide layer having a low layer resistance without depending on the line width of the electrode wiring.

The invention described in claim 9 is the third or fifth invention.
In the method of manufacturing a semiconductor device according to the above, in the amorphizing step, the rapid heat treatment is performed on the refractory metal film at a temperature of 400 ° C. or more and 550 ° C. or less in a hydrogen gas atmosphere to remove the silicide layer. A method for producing the amorphous silicide layer by performing a crystallization process.

According to the ninth aspect of the present invention, a third aspect is provided.
Or in addition to the effect described in 5, the heat treatment at a relatively low temperature of the amorphization step of the first rapid heat treatment step is performed in a hydrogen gas atmosphere, and the heat treatment at a relatively high temperature of the high resistance polycrystallization step is performed. By performing the treatment in a nitrogen atmosphere, there is an effect that nitriding of the titanium surface is not performed at all during the heat treatment at a relatively low temperature in the amorphization step. Further, oxygen or carbon remaining on the gate electrode 104 and the source electrode / drain electrode mixed in the process of manufacturing the MOS FET 10 is reduced by 50%.
Due to the reduction due to the diffusion of hydrogen during the heat treatment at 0 ° C., the effect of promoting the formation of the titanium silicide C49 phase during the heat treatment at a relatively high temperature in the high resistance polycrystallization step is achieved.

As a result, in the second rapid heat treatment step, the titanium silicide C54 phase is sufficiently formed, so that the layer resistance of the titanium silicide layer in the fine wire can be further reduced.

Also, by performing the heat treatment at 500 ° C. in a hydrogen gas atmosphere, there is a concern that titanium silicide may be formed on the sidewall insulating film 106 due to diffusion of silicon from the gate electrode 104 and the source / drain electrodes. But 5
Since the treatment is performed at a relatively low temperature of 00 ° C., the growth rate is very low, and an effect is obtained that insulation can be sufficiently performed during etching.

Further, the amorphizing step of the first rapid heat treatment step in the process of manufacturing the salicide structure 11 is performed at 400 ° C. to 55 ° C.
Nitrogen gas, which is easy to obtain high purity by heat treatment at a relatively low temperature of 0 ° C,
By performing in an atmosphere of argon gas or hydrogen gas, relatively amorphous metal is formed at the interface between the deposited high melting point metal and the polycrystalline silicon forming the gate electrode 104 and the silicon substrate 101 forming the source / drain electrodes. A high quality refractory metal silicide layer is formed with high purity.

Thereafter, by performing a high-resistance polycrystallization step for polycrystallizing the amorphous silicide layer and increasing the resistance, the amorphous high melting point formed in the amorphizing step is obtained. Using the metal silicide layer as a nucleus for growth, a relatively high-resistance high-melting-point metal silicide is formed uniformly, relatively finely, and relatively easily.

The refractory metal silicide thus formed is easily transformed into a relatively low-resistance refractory metal silicide in a second rapid heat treatment step, which is a subsequent step following the first rapid heat treatment step. The effect that it becomes possible to do it is produced.

According to this, the MOS of the salicide structure 11 is formed.
There is an effect that the resistance of the gate electrode 104 and the source electrode / drain electrode in the FET can be reduced.

As a result, the layer resistance of the gate electrode 104 and the thin line of the source electrode / drain electrode of 1 μm or less can be sufficiently reduced. As a result, the increase in the layer resistance of the thin wire as seen in the first prior art is suppressed, the resistance of the gate electrode 104 and the source electrode / drain electrode can be reduced, the parasitic resistance decreases, and the fineness decreases. M
There is an effect that the speed performance of the OS FET can be improved.

That is, 1 μm having the salicide structure 11
In the following minute gate electrode 104 and source electrode / drain electrode,
The effect of suppressing the increase in the resistance of the silicide layer on the drain electrode and forming the salicide structure 11 capable of realizing a silicide layer having a low layer resistance without depending on the line width of the electrode wiring is exhibited.

According to a tenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the third or fifth aspect, the amorphizing step includes forming the refractory metal film at a temperature of 400 ° C. or more and 550 ° C. or less. Performing the rapid heat treatment on the titanium metal film 401 to form an amorphous titanium silicide layer as the amorphous silicide layer by performing an amorphization process on the silicide layer. Of the semiconductor device.

According to the tenth aspect of the present invention, in addition to the effect of the third or fifth aspect, the amorphizing step of the first rapid heat treatment step in the manufacturing process of the salicide structure 11 is performed by four steps.
The heat treatment at a relatively low temperature of 00 ° C. to 550 ° C. is performed in a nitrogen gas, argon gas, or hydrogen gas atmosphere in which high purity can be easily obtained.
A relatively amorphous titanium silicide layer is formed with high purity at the interface between the polycrystalline silicon constituting the silicon substrate 101 and the silicon substrate 101 constituting the source / drain electrodes.

By performing the amorphizing step of the first rapid heat treatment step at a relatively low temperature of 400 ° C. to 550 ° C.,
There is an effect that an amorphous titanium silicide layer can be formed without forming relatively high-resistance titanium silicide which is easily formed at 600 ° C. or higher.

Thereafter, the amorphous titanium silicide formed in the amorphization step is formed by performing a polycrystallization process of the amorphous silicide layer and a high resistance polycrystallization step for increasing the resistance. Titanium silicide having a relatively high resistance is formed uniformly, relatively finely and relatively easily, with the layer as a nucleus of growth.

The thus formed titanium silicide C4
Ninth phase is a second step which is a post-step following the first rapid heat treatment step.
In the rapid heat treatment step, there is an effect that the phase can be easily changed to the titanium silicide C54 phase having a relatively low resistance.

According to this, there is an effect that the resistance of the titanium silicide layer is finally reduced in the thin lines of the gate electrode 104 and the source / drain electrodes. or,
During the amorphization step, silicon diffuses from the polycrystalline silicon forming the gate electrode 104 and the silicon substrate 101 forming the source electrode / drain electrode, and the side wall insulating film 10
The formation of the titanium silicide layer on 6 is also effected at a relatively low temperature, so that the effect is small. Accordingly, there is an effect that the problem of leakage of the gate electrode 104 and the source electrode / drain electrode does not occur.

As a result, the layer resistance of the gate electrode 104 and the thin line of the source electrode / drain electrode of 1 μm or less can be sufficiently reduced. As a result, the increase in the layer resistance of the thin wire as seen in the first prior art is suppressed, the resistance of the gate electrode 104 and the source electrode / drain electrode can be reduced, the parasitic resistance decreases, and the fineness decreases. M
There is an effect that the speed performance of the OS FET can be improved.

That is, 1 μm having the salicide structure 11
In the following minute gate electrode 104 and source electrode / drain electrode,
This has the effect of suppressing the increase in the resistance of the silicide layer on the drain electrode, and forming the salicide structure 11 capable of realizing a silicide layer having a low layer resistance without depending on the line width of the electrode wiring.

According to an eleventh aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourth or fifth aspect, the high-resistance polycrystallizing step includes forming the polycrystalline silicon layer on the silicide layer at a temperature of 600 ° C. to 750 ° C. A method of producing the high-resistance silicide layer 403 by performing a polycrystallization process and the high-resistance process.

According to the eleventh aspect of the present invention, in addition to the effect of the fourth or fifth aspect, the amorphizing step of the first rapid heat treatment step in the manufacturing process of the salicide structure 11 is performed by the fourth step.
By performing a relatively low-temperature heat treatment at 00 ° C. to 550 ° C. in a nitrogen gas, argon gas or hydrogen gas atmosphere in which high purity is easily obtained, the deposited high melting point metal film and the gate electrode 1
A relatively amorphous high-melting-point metal silicide layer is formed with high purity at the interface between the polycrystalline silicon constituting the semiconductor substrate 04 and the silicon substrate 101 constituting the source / drain electrodes.

By performing the amorphizing step of the first rapid heat treatment step at a relatively low temperature of 400 ° C. to 550 ° C.,
There is an effect that an amorphous high-melting-point metal silicide layer can be formed without forming relatively high-resistance high-melting-point metal silicide which is easily formed at 600 ° C. or higher.

Thereafter, using the amorphous refractory metal silicide layer formed uniformly in this manner as a nucleus for growth, polycrystallizing treatment of the amorphous silicide layer and treatment for increasing the resistance are performed. By performing the crystallization step at a temperature of 600 ° C. to 750 ° C. in a nitrogen gas, argon gas or hydrogen gas atmosphere, an amorphous high melting point metal silicide layer formed in the amorphization step is grown. As a nucleus, a refractory metal silicide having a relatively high resistance is formed uniformly, relatively finely and relatively easily.

The high melting point metal silicide thus formed is easily transformed into a relatively low resistance high melting point metal silicide in a second rapid heat treatment step which is a subsequent step following the first rapid heat treatment step. The effect that it becomes possible to do it is produced.

According to this, there is an effect that the resistance of the refractory metal silicide layer in the thin lines of the gate electrode 104 and the source / drain electrodes is eventually reduced.
During the amorphization step, silicon diffuses from the polycrystalline silicon forming the gate electrode 104 and the silicon substrate 101 forming the source / drain electrodes, thereby forming a refractory metal silicide layer on the sidewall insulating film 106. Also,
The effect is low because it is performed at a relatively low temperature. Accordingly, the gate electrode 104 and the source electrode /
This has the effect that the problem of leakage of the drain electrode does not occur.

As a result, the layer resistance of the gate electrode 104 and the thin line of the source electrode / drain electrode of 1 μm or less can be sufficiently reduced. Accordingly, the increase in the layer resistance of the thin wire as seen in the first prior art is suppressed, the resistance of the gate electrode 104 and the source electrode / drain electrode can be reduced, the parasitic resistance is reduced, and the fineness is reduced. M
There is an effect that the speed performance of the OS FET can be improved.

That is, 1 μm having the salicide structure 11
In the following minute gate electrode 104 and source electrode / drain electrode,
The effect of suppressing the increase in the resistance of the silicide layer on the drain electrode and forming the salicide structure 11 capable of realizing a silicide layer having a low layer resistance without depending on the line width of the electrode wiring is exhibited.

According to a twelfth aspect of the present invention, in the method of manufacturing a semiconductor device according to the eleventh aspect, the high-resistance polycrystallization step includes forming the polycrystalline layer on the silicide layer at a temperature of 600 ° C. or more and 750 ° C. or less. And a step of generating a titanium silicide layer C49 phase as the high-resistance silicide layer 403 by performing a passivation process.

According to the twelfth aspect, the same effect as the eleventh aspect can be obtained.

According to a thirteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourth or fifth aspect, the high-resistance polycrystallizing step includes the step of: A polycrystallizing process is performed to generate a titanium silicide layer C49 phase as the high resistance silicide layer 403, and at the same time, the titanium silicide layer C49
Forming a titanium nitride layer 402 on the titanium silicide layer C49 phase by performing the resistance increasing process on the phase.

According to the thirteenth aspect, the same effect as the fourth or fifth aspect can be obtained.

According to a fourteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourth or fifth aspect, the high-resistance polycrystallization step includes forming the polysilicon layer on the silicide layer at a temperature of 600 ° C. or more and 750 ° C. or less. The crystallization process is performed to generate the titanium silicide layer C49 phase as the high-resistance silicide layer 403, and at the same time, the titanium silicide layer C49 phase is subjected to the high-resistance process in a nitrogen gas atmosphere to perform the titanium silicide layer C49 phase. Titanium nitride layer 40 on top of phase
2 is a process for forming a semiconductor device.

According to the fourteenth aspect, the same effect as the fourth or fifth aspect can be obtained.

According to a fifteenth aspect of the present invention, in the method for manufacturing a semiconductor device according to the third or fifth aspect, the amorphizing step includes forming the refractory metal film at a temperature of 400 ° C. or more and 550 ° C. or less. Performing a rapid thermal treatment in a nitrogen gas atmosphere to perform an amorphization treatment of the silicide layer. The high-resistance polycrystallization step includes forming the polycrystalline layer on the silicide layer at a temperature of 600 ° C. or more and 750 ° C. or less. The crystallization process is performed to generate the titanium silicide layer C49 phase as the high-resistance silicide layer 403, and at the same time, the titanium silicide layer C49 phase is subjected to the high-resistance process in a nitrogen gas atmosphere to perform the titanium silicide layer C49 phase. Forming a titanium nitride layer 402 above the phase.

According to the fifteenth aspect of the present invention, in addition to the effect of the third or fifth aspect, the amorphizing step of the first rapid heat treatment step in the manufacturing process of the salicide structure 11 is performed by four steps.
By performing a relatively low-temperature heat treatment at a temperature of 00 ° C. to 550 ° C. in a nitrogen gas atmosphere in which high purity is easily obtained, the deposited titanium film, the polycrystalline silicon constituting the gate electrode 104 and the source electrode / drain A relatively amorphous titanium silicide layer is formed with high purity at the interface with the silicon substrate 101 constituting an electrode.

By performing the amorphizing step of the first rapid heat treatment step at a relatively low temperature of 400 ° C. to 550 ° C.,
There is an effect that an amorphous titanium silicide layer can be formed without forming relatively high-resistance titanium silicide which is easily formed at 600 ° C. or higher.

Thereafter, using the amorphous titanium silicide layer formed in this manner as a nucleus for growth, polycrystallizing treatment of the amorphous silicide layer and high resistance polycrystallizing treatment for increasing the resistance are performed. By performing the process at a temperature of 600 ° C. to 750 ° C. in a nitrogen gas, argon gas or hydrogen gas atmosphere, the amorphous titanium silicide layer formed in the amorphization process is used as a growth nucleus. A relatively high-resistance titanium silicide is formed uniformly, relatively finely and relatively easily.

The thus formed titanium silicide C4
Ninth phase is a second step which is a post-step following the first rapid heat treatment step.
In the rapid heat treatment step, there is an effect that the phase can be easily changed to the titanium silicide C54 phase having a relatively low resistance.

According to this, there is an effect that the resistance of the titanium silicide layer is finally reduced in the thin lines of the gate electrode 104 and the source / drain electrodes. or,
During the amorphization step, silicon diffuses from the polycrystalline silicon forming the gate electrode 104 and the silicon substrate 101 forming the source electrode / drain electrode, and the side wall insulating film 10
The formation of the titanium silicide layer on 6 is also effected at a relatively low temperature, so that the effect is small. Accordingly, there is an effect that the problem of leakage of the gate electrode 104 and the source electrode / drain electrode does not occur.

As a result, the layer resistance of the gate electrode 104 and the thin line of the source electrode / drain electrode of 1 μm or less can be sufficiently reduced. Accordingly, the increase in the layer resistance of the thin wire as seen in the first prior art is suppressed, the resistance of the gate electrode 104 and the source electrode / drain electrode can be reduced, the parasitic resistance is reduced, and the fineness is reduced. M
There is an effect that the speed performance of the OS FET can be improved.

According to a sixteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the third or fifth aspect, the amorphizing step includes forming the refractory metal film at a temperature of 400 ° C. or more and 550 ° C. or less. A step of performing a rapid heat treatment in an argon gas atmosphere to perform an amorphization treatment of the silicide layer, wherein the high-resistance polycrystallization step is performed at a temperature of 600 ° C. or more and 750 ° C.
At the following temperature, the polycrystallizing process is performed on the silicide layer to generate a titanium silicide layer C49 phase as the high-resistance silicide layer 403, and at the same time, the titanium silicide layer C49 phase is subjected to the high-resistance process in a nitrogen gas atmosphere. And forming a titanium nitride layer 402 on the titanium silicide layer C49 phase.

According to the sixteenth aspect of the present invention, in addition to the effect of the third or fifth aspect, the amorphizing step of the first rapid heat treatment step in the manufacturing process of the salicide structure 11 is performed by four steps.
By performing a relatively low temperature heat treatment of 00 ° C. to 550 ° C. in an argon gas atmosphere in which high purity can be easily obtained,
A relatively amorphous titanium silicide layer is formed with high purity at the interface between the deposited titanium film and the polycrystalline silicon forming the gate electrode 104 and the silicon substrate 101 forming the source / drain electrodes.

By performing the amorphizing step of the first rapid heat treatment step at a relatively low temperature of 400 ° C. to 550 ° C.,
There is an effect that an amorphous titanium silicide layer can be formed without forming relatively high-resistance titanium silicide which is easily formed at 600 ° C. or higher.

Thereafter, using the amorphous titanium silicide layer formed uniformly in this way as a nucleus for growth, a polycrystallizing treatment of the amorphous silicide layer and a high resistance polycrystallizing treatment for increasing the resistance are carried out. By performing the process at a temperature of 600 ° C. to 750 ° C. in a nitrogen gas, argon gas or hydrogen gas atmosphere, the amorphous titanium silicide layer formed in the amorphization process is used as a growth nucleus. A relatively high-resistance titanium silicide is formed uniformly, relatively finely and relatively easily.

The thus formed titanium silicide C4
Ninth phase is a second step which is a post-step following the first rapid heat treatment step.
In the rapid heat treatment step, there is an effect that the phase can be easily changed to the titanium silicide C54 phase having a relatively low resistance.

According to this, there is an effect that the resistance of the titanium silicide layer in the thin lines of the gate electrode 104 and the source / drain electrodes is eventually reduced. or,
During the amorphization step, silicon diffuses from the polycrystalline silicon forming the gate electrode 104 and the silicon substrate 101 forming the source electrode / drain electrode, and the side wall insulating film 10
The formation of the titanium silicide layer on 6 is also effected at a relatively low temperature, so that the effect is small. Accordingly, there is an effect that the problem of leakage of the gate electrode 104 and the source electrode / drain electrode does not occur.

As a result, the layer resistance of the gate electrode 104 and the thin line of the source electrode / drain electrode of 1 μm or less can be sufficiently reduced. Accordingly, the increase in the layer resistance of the thin wire as seen in the first prior art is suppressed, the resistance of the gate electrode 104 and the source electrode / drain electrode can be reduced, the parasitic resistance is reduced, and the fineness is reduced. M
There is an effect that the speed performance of the OS FET can be improved. According to a seventeenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the third or fifth aspect, the amorphizing step includes performing the rapid heat treatment on the refractory metal film at a temperature of 400 ° C. or more and 550 ° C. or less. A step of performing the amorphousizing treatment of the silicide layer in a hydrogen gas atmosphere, wherein the high-resistance polycrystallization step is performed at 600 ° C.
The polycrystallizing process is performed on the silicide layer at a temperature of not less than 750 ° C. to generate the titanium silicide layer C49 phase as the high-resistance silicide layer 403, and at the same time, the titanium silicide layer C49 phase is subjected to the high-resistance process. Executing in a nitrogen gas atmosphere, the titanium silicide layer C4
Forming a titanium nitride layer 402 as an upper layer of nine phases.

According to the seventeenth aspect of the present invention, in addition to the effect of the third or fifth aspect, the amorphizing step of the first rapid heat treatment step in the manufacturing process of the salicide structure 11 is performed by four steps.
The heat treatment at a relatively low temperature of 00 ° C. to 550 ° C. is performed in an atmosphere of a nitrogen gas, an argon gas, or a hydrogen gas atmosphere in which high purity can be easily obtained, so that the deposited titanium film and the polycrystal forming the gate electrode 104 are formed. A relatively amorphous titanium silicide layer is formed with high purity at the interface between silicon and the silicon substrate 101 constituting source / drain electrodes.

By performing the amorphizing step of the first rapid heat treatment step at a relatively low temperature of 400 ° C. to 550 ° C.,
There is an effect that an amorphous titanium silicide layer can be formed without forming relatively high-resistance titanium silicide which is easily formed at 600 ° C. or higher.

Thereafter, using the amorphous titanium silicide layer formed uniformly in this way as a nucleus for growth, a polycrystallizing treatment of the amorphous silicide layer and a high resistance polycrystallizing treatment for increasing the resistance are carried out. By performing the process at a temperature of 600 ° C. to 750 ° C. in a hydrogen gas atmosphere, a relatively high-resistance titanium is used as a growth nucleus using the amorphous titanium silicide layer formed in the amorphization process. The silicide is formed uniformly, relatively finely and relatively easily.

The thus formed titanium silicide C4
Ninth phase is a second step which is a post-step following the first rapid heat treatment step.
In the rapid heat treatment step, there is an effect that the phase can be easily changed to the titanium silicide C54 phase having a relatively low resistance.

According to this, there is an effect that the resistance of the titanium silicide layer is finally reduced in the thin lines of the gate electrode 104 and the source / drain electrodes. or,
During the amorphization step, silicon diffuses from the polycrystalline silicon forming the gate electrode 104 and the silicon substrate 101 forming the source electrode / drain electrode, and the side wall insulating film 10
The formation of the titanium silicide layer on 6 is also effected at a relatively low temperature, so that the effect is small. Accordingly, there is an effect that the problem of leakage of the gate electrode 104 and the source electrode / drain electrode does not occur.

As a result, the layer resistance of the gate electrode 104 and the thin line of the source electrode / drain electrode of 1 μm or less can be sufficiently reduced. Accordingly, the increase in the layer resistance of the thin wire as seen in the first prior art is suppressed, the resistance of the gate electrode 104 and the source electrode / drain electrode can be reduced, the parasitic resistance is reduced, and the fineness is reduced. M
There is an effect that the speed performance of the OS FET can be improved.

According to an eighteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the first to seventeenth aspects, the second rapid thermal processing step is formed in the first rapid thermal processing step. Said titanium silicide layer C
A method of manufacturing a semiconductor device, comprising: performing a rapid heat treatment on a 49 phase to change the titanium silicide layer C49 phase to a titanium silicide layer C54 phase 404 to reduce the resistance. .

According to the eighteenth aspect of the invention, the same effects as those of the first aspect can be obtained.

According to a nineteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the first to seventeenth aspects, the refractory metal film includes titanium. Of the semiconductor device.

According to the nineteenth aspect of the present invention, in addition to the effects of any one of the first to seventeenth aspects, the use of titanium as a refractory metal has a low resistivity. In addition, it is possible to form a silicide layer having relatively high heat resistance. Titanium has the advantage of having the lowest silicide resistivity and relatively heat resistance among the refractory metals titanium, cobalt, nickel, platinum and the like usually used to form the salicide structure 11. I have. Further, there is an effect that an amorphous titanium silicide layer can be formed relatively easily in the amorphizing step of 400 ° C. to 550 ° C. in the first rapid heat treatment step.

According to a twentieth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the first to seventeenth aspects, the refractory metal film includes titanium nitride. A method for manufacturing a semiconductor device characterized by the following.

According to the twentieth aspect of the present invention, in addition to the effects of any one of the first to seventeenth aspects, the use of titanium nitride as a refractory metal enables low resistivity to be achieved. This has an effect that a silicide layer having a relatively high heat resistance can be formed. Titanium nitride also has the advantage of having the lowest silicide resistivity and relatively high heat resistance among the refractory metal nitrides usually used to form the salicide structure 11. Further, there is an effect that an amorphous titanium silicide layer can be formed relatively easily in the amorphizing step of 400 ° C. to 550 ° C. in the first rapid heat treatment step.

According to a twenty-first aspect of the present invention, in the method for manufacturing a semiconductor device according to any one of the first to seventeenth aspects, the refractory metal film includes a titanium oxide. A method for manufacturing a semiconductor device characterized by the following.

According to the twenty-first aspect of the present invention, in addition to the effects of any one of the first to seventeenth aspects, the use of titanium oxide as a refractory metal allows a low resistivity to be obtained. This has an effect that a silicide layer having a relatively high heat resistance can be formed. Titanium nitride has the advantage of having the lowest silicide resistivity and relatively high heat resistance among the refractory metal oxides usually used for forming the salicide structure 11. Further, there is an effect that an amorphous titanium silicide layer can be formed relatively easily in the amorphizing step of 400 ° C. to 550 ° C. in the first rapid heat treatment step.

[0167]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Various embodiments of the present invention will be described below with reference to the drawings.

FIG. 1A shows a source electrode / drain electrode 1.
FIG. 1B is a cross-sectional view of an element structure of a MOS FET in which a gate electrode 07, a gate electrode 104, and a sidewall insulating film 106 are formed.
Is a MOS in which a high melting point metal film 401 is deposited on the entire surface of the semiconductor substrate 101 by a sputtering method in accordance with a high melting point metal forming process.
FIG. 1C is a cross-sectional view of the element structure of the FET, and FIG. 1C shows a MOS FE in which a relatively high-resistance silicide (silicide) layer of a refractory metal is formed by a first rapid thermal processing step.
FIG. 1D is a sectional view of the element structure of T. FIG. 1D shows the titanium nitride layer 402 formed on the side wall insulating film 106 by the first rapid heat treatment step, the gate electrode 104 and the source electrode /
FIG. 4 is a cross-sectional view of a device structure of a MOS FET in which a titanium nitride layer 402 on a titanium silicide (TiSi 2) C49 phase formed on a drain electrode 107 and an unreacted titanium layer are selectively etched and removed by a silicide layer forming step. FIG. 1 (e) shows a relatively low resistance silicide layer TiSi2 C54 of a high melting point metal according to a second rapid heat treatment step.
FIG. 4 is a sectional view of the element structure of a MOSFET in which a phase 404 is formed.

Salicide (SALIDE: Self)
Aligned Silicide technology)
LDD (Lightly) for improving hot carrier resistance in order to ensure the reliability of the MOS FET 10 itself.
Doped Drain) structure is formed, and the gate electrode 1 is formed.
In this technique, the resistance of the source electrode / drain electrode 107 is reduced by silicidation of the source electrode / drain electrode 107.

In the MOS FET 10, as shown in FIG. 1A, a well serving as a substrate electrode of the MOS FET 10 is formed on a semiconductor substrate 101 formed of a silicon semiconductor single crystal. An element isolation region 102 is formed by using an isolation technique. Thereafter, ion implantation for controlling the channel concentration of the MOS FET 10 is performed, and thereafter, a gate oxide film 103 and a gate electrode 104 are formed. .

Gate oxide film 103 and gate electrode 104
In the formation of the gate electrode 104, it is preferable to use the polycrystalline silicon 104 alone. At this time, the gate electrode 104 is made of polycrystalline silicon of 100 nm to 3 nm.
It is desirable to form it with a thickness of 00 nm.

The source electrode / drain electrode 107 has a resistance of 0.1 mm.
It is formed with a depth of 10 to 0.20 μm. Such a source electrode / drain electrode 107 is an n-channel MOS
In the case of the FET 10, arsenic is implanted and formed by ion implantation. In the case of the p-channel MOSFET 10, boron difluoride BF2 or boron B is preferably implanted and formed by ion implantation, and is approximately 0.10 to 0.20 μm. It is preferable to form with the depth of.

Preferably, side wall insulating film 106 is formed of a silicon oxide film having a thickness of about 0.10 to 0.15 μm.

In the MOS FET 10, following the formation of the gate oxide film 103 and the gate electrode 104, an impurity diffusion layer 105 having a relatively low concentration is formed by ion implantation using the gate electrode 104 as an implantation mask.

Here, in the case of an n-channel transistor, the conductivity type of the low-concentration impurity diffusion layer 105 is n-type,
In the case of a channel transistor, a low concentration impurity diffusion layer 1
Preferably, the conductivity type of 05 is set to p-type.

Specifically, an n-channel MOS FET
In the case of 10, it is preferable that arsenic or phosphorus be implanted by ion implantation. Also, p-channel MOS FE
In the case of T10, boron difluoride BF2 or boron B is preferably implanted by ion implantation.

After the ion implantation method, as shown in FIG. 1A, the gate electrode 104 is formed by an insulating film such as a silicon oxide film 106 formed by using a film forming means such as a thermal CVD method.
Is formed by using the sidewall insulating film 106, the gate electrode 104, and the element isolation region 102 as an implantation mask to form a high-concentration impurity diffusion layer 107 in a self-aligned manner using a doping technique such as an ion implantation method. .

At the time of forming the high concentration impurity diffusion layer 107,
Similar high-concentration impurities are implanted into gate electrode 104 in a self-aligned manner.

Here, in the case of an n-channel transistor, the conductivity type of high-concentration impurity diffusion layer 107 is set to n-type, and in the case of a p-channel transistor, the conductivity type of high-concentration impurity diffusion layer 107 is set to p-type. Is preferably performed.

FIG. 2 is a process flow chart for explaining a process of forming the salicide structure 11 in the method of manufacturing a semiconductor device according to the present invention. RTA stands for rapid heat treatment, and is an abbreviation for Rapid Thermal Anneal.

As shown in FIG. 2, in the method of manufacturing the semiconductor device, the gate electrode 104 and the source electrode or the drain electrode are raised to reduce the resistance of the gate electrode 104 and the source / drain electrode 107. A method for manufacturing a semiconductor device such as an IC, LSI, or ASIC having a MOS transistor 10 in which a salicide structure that self-aligns and lowers resistance using a silicide film containing a melting point metal is formed. A step of forming the drain electrode 107, the gate electrode 104, and the sidewall insulating film 106 (step S1), a step of forming a refractory metal (step S2), a first rapid heat treatment step (step S3), and a step of forming a silicide layer (step S4). It has a second rapid heat treatment step (step S5).

As shown in FIG. 2, the method for manufacturing a semiconductor device according to the present invention includes a step of forming a refractory metal (FIG. 1B or FIG. 2B).
After the execution of step S2), the first rapid heat treatment step (FIG. 1C or step S3 in FIG. 2) is executed, and the first rapid heat treatment step (FIG. 1C or step S3 in FIG. 2) is performed. It is desirable to use a process sequence for forming the salicide structure 11 by performing the second rapid thermal processing step (FIG. 1E or step S5 in FIG. 2) after the execution.

Hereinafter, each processing step will be described.

The high melting point metal forming step (step S2)
This is a step of depositing titanium on the semiconductor substrate 101, as shown in FIG. In particular, it is preferable that titanium is deposited on the entire surface of the semiconductor substrate 101 by a sputtering method or the like by a sputtering method from the viewpoint of film uniformity, film quality, and process cost.

As a result, there is an effect that the resistance of the titanium silicide layer in the thin lines of the gate electrode 104 and the source electrode / drain electrode 107 is eventually reduced. At the time of the amorphization step (STEP 1 in step S3), silicon diffuses from the polycrystalline silicon forming the gate electrode 104 and the silicon substrate 101 forming the source / drain electrodes 107, and titanium on the side wall insulating film 106 Forming a silicide layer can also be performed at a relatively low temperature (40
(0 ° C. to 550 ° C.). Thereby, there is an effect that the problem of leakage of the gate electrode 104 and the source electrode / drain electrode 107 does not occur.

As a result, the layer resistance can be sufficiently reduced even in the fine lines of 1 μm or less of the gate electrode 104 and the source / drain electrodes 107. Therefore, the first
The increase in the layer resistance of the thin wire as in the prior art is suppressed, the resistance of the gate electrode 104 and the source electrode / drain electrode 107 can be reduced, the parasitic resistance is reduced, and the speed of the fine MOS FET is reduced. There is an effect that the performance can be improved.

Further, a high melting point metal forming step (step S2)
Then, it is desirable to use titanium as the high melting point metal film 401.

At this time, the film thickness of titanium is determined by the gate electrode and the source / drain electrodes 10 required by the device.
7, the minimum size of the present MOS FET 10 is set to a device size of 0.5 μm or less.
The formation depth of the source electrode / drain electrode 107 is 0.15
It is preferably formed with a thickness of not more than μm.

At this time, if the silicide layer is formed too thick, the leakage current between the source electrode / drain electrode 107 and the substrate electrode increases, and the MOS FET 10
There is a risk of deteriorating the performance of the device. Therefore, about 5
It is desirable to deposit titanium having a thickness of 0 nm or less.

By using titanium as the high melting point metal, there is an effect that a silicide layer having low resistivity and relatively high heat resistance can be formed. Titanium is a metal having a high melting point, such as titanium, cobalt, which is usually used to form the salicide structure 11.
Among nickel, platinum and the like, silicide has the lowest resistivity and has the advantage of relatively heat resistance. Furthermore,
Amorphization step (STEP 1 of step S3) 4 of the first rapid thermal processing step (FIG. 1C or step S3 of FIG. 2)
At a temperature of 00 ° C. to 550 ° C., an effect is obtained that an amorphous titanium silicide layer can be formed relatively easily.

In the method of manufacturing a semiconductor device, titanium nitride may be used instead of titanium as the high melting point metal film 401. When the titanium nitride is used as the high melting point metal as described above, there is an effect that a silicide layer having a low resistivity and a relatively high heat resistance can be formed. Titanium nitride also has the advantage of having the lowest silicide resistivity and relatively high heat resistance among the refractory metal nitrides usually used to form the salicide structure 11. Further, a first rapid heat treatment step (FIG. 1C or step S3 in FIG. 2)
Amorphization step (STEP 1 in step S3) 400 ° C.
At a temperature of up to 550 ° C., an effect is obtained that an amorphous titanium silicide layer can be formed relatively easily. Further, for the same purpose, the refractory metal film 401
It is also possible to use titanium oxide instead of titanium. When the titanium oxide is used as the high melting point metal as described above, there is an effect that a silicide layer having a low resistivity and a relatively high heat resistance can be formed. Titanium nitride has the advantage of having the lowest silicide resistivity and relatively high heat resistance among the refractory metal oxides usually used for forming the salicide structure 11. Further, in the first rapid thermal processing step (FIG. 1 (c) or the step S3 in FIG. 2) of the amorphization step (STEP 1 in the step S3), at 400 ° C. to 550 ° C., the amorphous titanium is relatively easily formed. There is an effect that a silicide layer can be formed.

FIG. 3 is a graph for explaining a temperature profile used in a rapid heat treatment process performed in a conventional rapid heat treatment process. FIG. 4 is a graph for explaining a temperature profile used in the rapid heat treatment process performed in the first rapid heat treatment step (FIG. 1C or step S3 in FIG. 2) of FIG.

First Rapid Heat Treatment Step (Step S3)
As shown in FIG. 1 (c), the titanium film deposited in the high melting point metal forming step (FIG. 1 (b) or step S2 in FIG. 2) is subjected to a rapid heat treatment to have a desired high resistance value. This is a step of forming the high-resistance silicide layer 403.

In the first rapid thermal processing step (FIG. 1 (c) or step S3 in FIG. 2), the semiconductor substrate 101 on which titanium is deposited is introduced at about 700.degree.
Rapid heating to near high temperature and heat treatment by lamp heating for about 30 seconds are performed. At this time, in the high-resistance polycrystallizing step (step S2 in FIG. 1B or FIG. 2), titanium deposited on the semiconductor substrate 101 is formed on the polycrystalline silicon as the gate electrode 104 and the source electrode / drain electrode 10
A relatively high-resistance titanium silicide (TiSi2) C49 phase is formed on the silicon substrate 7.

The first rapid heat treatment step (FIG. 1C or step S3 in FIG. 2) includes an amorphization step (STEP 1 in step S3 in FIG. 2) and a high-resistance polycrystallization step (FIG. 2).
(Step 2 in Step S3) to form an amorphized amorphous silicide layer by performing an amorphization step (Step 1 in Step S3).
After performing the amorphization step (STEP 1 in step S3), the amorphous silicide layer is subjected to a high-resistance polycrystallizing step (STEP 2 in step S3) to perform a polycrystalline and high-resistance high-resistance silicide layer 403. Is characterized in that

Here, the amorphizing step (see STEP 1 in step S3) is a step of performing an amorphizing process on the silicide layer to generate an amorphous silicide layer.

Further, the amorphizing step (STE in step S3)
P1) An amorphous silicide layer is formed by performing a rapid thermal treatment on a titanium film in a nitrogen gas, argon gas or hydrogen gas atmosphere at a temperature of 400 ° C. or more and 550 ° C. or less to perform amorphization of the silicide layer. Is a step of generating

When the heat treatment is performed in a nitrogen atmosphere, a titanium nitride layer is formed on the titanium silicide (TiSi 2) C49 phase.

On the side wall insulating film 106, oxygen supplied from the silicon oxide film serving as the side wall insulating film 106 reacts with titanium to form a slight titanium oxide film. Electrode / Drain electrode 1
07, a titanium nitride layer is formed.

As described above, the first rapid heat treatment step (FIG. 1)
(C) or the relatively low temperature (400 ° C. to 55 ° C.) of the amorphization step (STEP 1 in step S3) in step S3 in FIG.
A heat treatment at a temperature of 0 ° C.) and a relatively high temperature heat treatment of a high-resistance polycrystallization step (STEP 2 in step S3) are performed in a nitrogen atmosphere. The semiconductor substrate 101 on which titanium is deposited is
After introduction into the TA device, as shown in FIG.
An amorphization step of rapidly heating to a relatively low temperature and performing lamp heating for about 60 seconds is performed.

At this time, the titanium deposited on the semiconductor substrate 101 uniformly forms a relatively amorphous titanium silicide layer on the polycrystalline silicon as the gate electrode 104 and the silicon substrate as the source / drain electrodes 107. Form.

By this, the amorphization step (step S3
1) and the high-resistance polycrystallizing step (STEP 2 in step S3) can be performed without replacing the atmosphere gas. As a result, the first rapid thermal processing step (FIG. 1) is performed.
(C) or the throughput of step S3) of FIG. 2 is improved. The reason why such a high-resistance polycrystallizing step (STEP 2 in step S3) is desirably in a nitrogen atmosphere is that the gate electrode 104 is not heat-treated during the heat treatment.
In order to suppress the diffusion of silicon from the polycrystalline silicon constituting silicon and the silicon substrate 101 constituting the source electrode / drain electrode 107 and the formation of a titanium silicide layer on the sidewall insulating film 106, titanium is nitrided from the titanium surface. It is thought that there is to be.

The first step in the process of manufacturing the salicide structure 11 is as follows.
Rapid heat treatment step (FIG. 1 (c) or step S in FIG. 2)
The amorphization step (3) (STEP 1 in step S3)
By performing a relatively low-temperature heat treatment at 400 ° C. to 550 ° C. in a nitrogen gas atmosphere, the deposited titanium film, the polycrystalline silicon forming the gate electrode 104 and the silicon substrate forming the source / drain electrodes 107 There is an effect that a relatively amorphous silicide layer can be formed at the interface with the substrate 101.

The amorphizing step (step S3) in the first rapid thermal processing step (FIG. 1 (c) or step S3 in FIG. 2).
By performing STEP 1) at a relatively low temperature of 400 ° C. to 550 ° C., an amorphous titanium silicide layer can be formed without forming relatively high-resistance titanium silicide easily formed at 600 ° C. or more. It has the effect of becoming

Thereafter, by performing a high-resistance polycrystallization step (STEP 2 in step S3) for polycrystallizing and increasing the resistance of the amorphous silicide layer, an amorphization step (step S3) is performed. Using the amorphous silicide layer formed in STEP 1) as a growth nucleus, relatively high-resistance titanium silicide is formed uniformly, relatively finely, and relatively easily.

The titanium silicide thus formed is
A second rapid thermal processing step (FIG. 1) which is a post-process following the first rapid thermal processing step (FIG. 1C or step S3 in FIG. 2).
In step (e) or step S5 in FIG. 2, an effect is obtained that a phase transition can be easily made to titanium silicide having a relatively low resistance.

According to this, the MOS of the salicide structure 11 is formed.
There is an effect that the resistance of the gate electrode 104 and the source electrode / drain electrode 107 in the FET can be reduced.

The amorphizing step (step S3) in the first rapid thermal processing step (FIG. 1 (c) or step S3 in FIG. 2)
Is performed in the argon gas atmosphere instead of the nitrogen gas atmosphere, and the relatively high temperature in the high-resistance polycrystallization step (STEP 2 in step S3) is performed. By performing the heat treatment in a nitrogen atmosphere, an amorphization step (STE in step S3) is performed.
No nitriding of the titanium surface is performed during the relatively low temperature (400 ° C. to 550 ° C.) heat treatment of P1), and this is the first time in the relatively high temperature heat treatment stage of the high-resistance polycrystallization process (STEP 2 in step S3). Since the nitridation of the titanium surface begins, a small amount of titanium silicide (TiSi2)
This has the effect of promoting the formation of the C49 phase.

The second rapid heat treatment step (FIG. 1)
In step (e) or step S5 in FIG. 2, the titanium silicide (TiSi2) C54 phase is sufficiently formed, and the layer resistance of the titanium silicide layer in the thin wire is reduced.

Further, since the heat treatment at 500 ° C. is performed in an argon gas atmosphere, there is a concern that titanium silicide may be formed on the sidewall insulating film 106 by diffusion of silicon from the gate electrode 104 and the source / drain electrodes 107. Since the treatment is performed at a relatively low temperature of 500 ° C. (a temperature of 400 ° C. to 550 ° C.), the growth rate is very slow, and an effect is obtained that insulation can be sufficiently performed at the time of etching.

Further, a first rapid heat treatment step (FIG. 1C or step S in FIG. 2) in the process of manufacturing the salicide structure 11 is performed.
The amorphization step (3) (STEP 1 in step S3)
By performing a relatively low-temperature heat treatment at 400 ° C. to 550 ° C. in an argon gas atmosphere that is inert and easily obtains high purity, the deposited titanium film and the polycrystalline silicon and source electrode / A relatively amorphous silicide layer is formed with high purity at the interface with the silicon substrate 101 forming the drain electrode 107.

Further, a first rapid heat treatment step (FIG. 1C)
Alternatively, the amorphizing step (step S3) in step S3 in FIG.
By performing the relatively low-temperature (400 ° C. to 550 ° C.) heat treatment in STEP 1) in a hydrogen gas atmosphere instead of a nitrogen gas atmosphere, relatively high-resistance titanium easily formed at 600 ° C. or higher. There is an effect that an amorphous titanium silicide layer can be formed without forming much silicide.

Thereafter, using the amorphous titanium silicide layer formed uniformly in this way as a nucleus for growth, a polycrystallizing treatment of the amorphous silicide layer and a high resistance polycrystallizing treatment for increasing the resistance are carried out. Step (Step 2 of Step S3) 60
By performing the process in a hydrogen gas atmosphere at a temperature of 0 ° C. to 750 ° C., an amorphization step (STEP in step S3) is performed.
Using the amorphous titanium silicide layer formed in 1) as a growth nucleus, a relatively high-resistance titanium silicide is formed uniformly, relatively finely, and relatively easily.

By performing a relatively high-temperature (600 ° C. to 750 ° C.) heat treatment in the high-resistance polycrystallization step (STEP 2 in step S3) in a nitrogen atmosphere, an amorphization step (step S3) is performed. In step 1), nitriding of the titanium surface during the heat treatment at a relatively low temperature (temperature of 400 ° C. to 550 ° C.) is not performed at all. Furthermore,
Oxygen or carbon remaining on the gate electrode 104 and the source electrode / drain electrode 107 mixed during the manufacturing process of the MOS FET 10 is reduced by diffusion of hydrogen during the heat treatment at 500 ° C., so that high resistance is obtained. There is an effect that the formation of the titanium silicide C49 phase is further promoted in the relatively high temperature heat treatment stage of the polycrystallization process (STEP 2 in step S3).

The second rapid heat treatment step (FIG. 1)
(E) or the step S5 in FIG. 2 has an effect that the titanium silicide C54 phase is sufficiently formed and the layer resistance of the titanium silicide layer in the fine wire can be further reduced.

According to this, there is an effect that the resistance of the titanium silicide layer in the thin lines of the gate electrode 104 and the source electrode / drain electrode 107 is eventually reduced. At the time of the amorphization step (STEP 1 in step S3), silicon diffuses from the polycrystalline silicon forming the gate electrode 104 and the silicon substrate 101 forming the source / drain electrodes 107, and titanium on the side wall insulating film 106 The effect of forming a silicide layer is relatively small since it is performed at a relatively low temperature. Accordingly, the gate electrode 104 and the source electrode / drain electrode 1
07 does not occur.

As a result, the layer resistance is sufficiently reduced even in the fine lines of 1 μm or less of the gate electrode 104 and the source / drain electrodes 107. Therefore, the first
The increase in the layer resistance of the thin wire as in the prior art is suppressed, the resistance of the gate electrode 104 and the source electrode / drain electrode 107 can be reduced, the parasitic resistance is reduced, and the speed of the fine MOS FET is reduced. There is an effect that the performance can be improved.

Further, by performing the heat treatment at 500 ° C. in a hydrogen gas atmosphere, titanium silicide may be formed on the sidewall insulating film 106 due to diffusion of silicon from the gate electrode 104 and the source / drain electrodes 107. However, since the treatment is performed at a relatively low temperature of 500 ° C. (a temperature of 400 ° C. to 550 ° C.), the growth rate is very low, and an effect is obtained that insulation can be sufficiently performed during etching.

Further, a first rapid heat treatment step (FIG. 1C or step S in FIG. 2) in the process of manufacturing the salicide structure 11 is performed.
The amorphization step (3) (STEP 1 in step S3)
The heat treatment at a relatively low temperature of 400 ° C. to 550 ° C. is performed in a nitrogen gas, argon gas, or hydrogen gas atmosphere in which high purity can be easily obtained.
A relatively amorphous titanium silicide layer is formed with high purity on the interface between the polycrystalline silicon constituting the silicon substrate 101 and the silicon substrate 101 constituting the source / drain electrodes 107.

As described above, by providing such an amorphization step, the first rapid heat treatment step (FIG. 1C or step S3 in FIG. 2) in the manufacturing process of the salicide structure 11 is performed. By performing the amorphization step, a relatively amorphous interface is formed between the deposited titanium film and the polycrystalline silicon forming the gate electrode 104 and the silicon substrate 101 forming the source / drain electrodes 107. This has an effect that a silicide layer can be formed.

Thereafter, a first rapid heat treatment step (FIG. 1)
(C) or by performing the high-resistance polycrystallization step (STEP 2 in step S3) in step S3 in FIG.
With the amorphous silicide layer formed in the amorphization step as a growth nucleus, titanium silicide having relatively high resistance is formed uniformly, relatively finely and relatively easily.

The titanium silicide thus formed is
A second rapid thermal processing step (FIG. 1) which is a post-process of the first rapid thermal processing step (FIG. 1C or step S3 in FIG. 2).
In step (e) or step S5 in FIG. 2, an effect is obtained that a phase transition can be easily made to titanium silicide having a relatively low resistance.

High resistance polycrystallization step (ST in step S3)
In EP2), the first rapid heat treatment step (FIG. 1C or step S3 in FIG. 2) is to raise the amorphous silicide layer for performing the polycrystallization treatment and the high resistance treatment on the amorphous silicide layer. This is a step of generating a high-resistance silicide layer 403 by resistance.

High-resistance polycrystallizing step (ST in step S3)
EP2) performs a polycrystallization process on the silicide layer at a temperature of 600 ° C. or more and 750 ° C. or less to perform titanium silicide layer C
This is a step of forming the titanium nitride layer 402 on the titanium silicide layer C49 phase by performing a resistance increasing process on the titanium silicide layer C49 phase in a nitrogen gas atmosphere while generating the 49 phase as the high resistance silicide layer 403. .

Specifically, after performing the amorphizing step, FIG.
As shown in the figure, rapid heating to a high temperature of about 700 ° C.,
Heat treatment is performed by lamp heating for about 30 seconds.

At this time, the relatively amorphous titanium silicide layer formed in the amorphization step is used as a growth nucleus on the polycrystalline silicon as the gate electrode 104 and the silicon substrate as the source / drain electrodes 107. Above, a relatively high-resistance titanium silicide (TiSi2) C49 phase is uniformly and relatively easily formed.

At this time, since an amorphous titanium silicide layer serving as a nucleus for growth is present, the grain size of the C49 phase formed is smaller than that of the first prior art.

After the first rapid heat treatment step (step S3 in FIG. 1C or FIG. 2), in the high-resistance polycrystallization step (STEP 2 in step S3), the titanium silicide (TiSi 2) A titanium nitride layer is formed.

On the side wall insulating film 106, oxygen supplied from the silicon oxide film as the side wall insulating film 106 reacts with titanium to form a slight titanium oxide film, on which the gate electrode 104 and the source are formed. Electrode / Drain electrode 1
07, a titanium nitride layer is formed.

The titanium deposited on the side wall insulating film 106 is subjected to a two-step RTA process (amorphization step and high-resistance polycrystallization step), so that the titanium is deposited on the side wall insulating film 106.
A minute oxidized titanium film is formed near the silicon oxide film interface, and nitrided titanium is formed thereon. That is, although not stoichiometric, a stacked structure 402 of titanium oxide and titanium nitride is obtained. The titanium oxide / titanium nitride layer 402 is subjected to a silicide layer formation step (FIG. 1D or step S4 in FIG. 2) described later in FIG. 1D.
It is etched away.

According to this, the amorphizing step (STEP in step S3) of the first rapid heat treatment step (FIG. 1 (c) or step S3 in FIG. 2) in the manufacturing process of the salicide structure 11 is performed.
1) by performing a relatively low-temperature heat treatment at 400 ° C. to 550 ° C. in a nitrogen gas atmosphere in which high purity can be easily obtained, so that the deposited titanium film, the polycrystalline silicon forming the gate electrode 104, and the source electrode A relatively amorphous titanium silicide layer is formed with high purity at the interface with the silicon substrate 101 constituting the / drain electrode 107.

The amorphizing step (step S3) in the first rapid thermal processing step (FIG. 1 (c) or step S3 in FIG. 2).
By performing STEP 1) at a relatively low temperature of 400 ° C. to 550 ° C., an amorphous titanium silicide layer can be formed without forming relatively high-resistance titanium silicide easily formed at 600 ° C. or more. It has the effect of becoming

Thereafter, using the amorphous titanium silicide layer formed uniformly in this way as a nucleus for growth, polycrystallizing treatment of the amorphous silicide layer and high-resistance polycrystallizing treatment for increasing the resistance are carried out. Step (Step 2 of Step S3) 60
By performing the process in a nitrogen gas atmosphere at a temperature of 0 ° C. to 750 ° C., an amorphization step (STEP S3) is performed.
Using the amorphous titanium silicide layer formed in 1) as a growth nucleus, a relatively high-resistance titanium silicide is formed uniformly, relatively finely, and relatively easily.

The titanium silicide thus formed is:
A second rapid thermal processing step (FIG. 1) which is a post-process following the first rapid thermal processing step (FIG. 1C or step S3 in FIG. 2).
In step (e) or step S5 in FIG. 2, an effect is obtained that a phase transition can be easily made to titanium silicide having a relatively low resistance.

According to this, there is an effect that the resistance of the titanium silicide layer in the thin lines of the gate electrode 104 and the source electrode / drain electrode 107 is eventually reduced. At the time of the amorphization step (STEP 1 in step S3), silicon diffuses from the polycrystalline silicon forming the gate electrode 104 and the silicon substrate 101 forming the source / drain electrodes 107, and titanium on the side wall insulating film 106 Forming a silicide layer can also be performed at a relatively low temperature (40
(0 ° C. to 550 ° C.). Thereby, there is an effect that the problem of leakage of the gate electrode 104 and the source electrode / drain electrode 107 does not occur.

As a result, the layer resistance is sufficiently reduced even in the fine lines of 1 μm or less of the gate electrode 104 and the source / drain electrodes 107. Therefore, the first
The increase in the layer resistance of the thin wire as in the prior art is suppressed, the resistance of the gate electrode 104 and the source electrode / drain electrode 107 can be reduced, the parasitic resistance is reduced, and the speed of the fine MOS FET is reduced. There is an effect that the performance can be improved.

As described above, according to the first rapid thermal processing step (FIG. 1C or step S3 in FIG. 2), the amorphizing step (step S3) for the manufacturing process of the salicide structure 11 is performed. Is performed at a relatively low temperature of 400 ° C. to 550 ° C. to deposit the titanium film, the polycrystalline silicon forming the gate electrode 104, and the silicon substrate 101 forming the source / drain electrodes 107. This has the effect that a relatively amorphous silicide layer can be formed at the interface with.

The amorphizing step (step S3) in the first rapid thermal processing step (step S3 in FIG. 1 (c) or FIG. 2)
By performing STEP 1) at a relatively low temperature of 400 ° C. to 550 ° C., an amorphous titanium silicide layer can be formed without forming relatively high-resistance titanium silicide easily formed at 600 ° C. or more. It has the effect of becoming

Thereafter, by performing a high-resistance polycrystallization step (STEP 2 in step S3) for performing a polycrystallization process and a high-resistance process of the amorphous silicide layer, an amorphous process (step S3) is performed. Using the amorphous silicide layer formed in STEP 1) as a growth nucleus, relatively high-resistance titanium silicide is formed uniformly, relatively finely, and relatively easily.

The titanium silicide thus formed is:
A second rapid thermal processing step (FIG. 1) which is a post-process following the first rapid thermal processing step (FIG. 1C or step S3 in FIG. 2).
In step (e) or step S5 in FIG. 2, an effect is obtained that a phase transition can be easily made to titanium silicide having a relatively low resistance.

According to this, the MOS of the salicide structure 11 is formed.
There is an effect that the resistance of the gate electrode 104 and the source electrode / drain electrode 107 in the FET can be reduced.

[0242] Silicide layer forming step (step S4)
As shown in FIG. 1D, the first rapid heat treatment step (FIG. 1 (C)) is performed by selectively etching and removing a titanium film that has not reacted or a nitrided titanium film in the rapid heat treatment. This is a step of leaving only the high-resistance silicide layer 403 formed in c) or step S3) of FIG.

According to the first rapid thermal processing step (FIG. 1C or step S3 in FIG. 2), the titanium nitride layer 402 formed on the side wall insulating film 106 and the source / drain electrodes 107 on the gate electrode 104 The titanium nitride layer on the titanium silicide C49 phase formed thereon and the unreacted titanium layer are selectively etched away with respect to the formed titanium silicide layer C49 phase.

At this time, in this embodiment, it is desirable to use a mixed solution of hydrogen peroxide, ammonia and water as the etching solution. By providing such an etchant, the unreacted titanium layer and titanium nitride layer are selectively etched away, so that the gate electrode 104 and the source / drain electrodes 107 can be electrically insulated. It has the effect of becoming

As described above, in the method of manufacturing a semiconductor device according to the second prior art, the first rapid thermal processing step (FIG. 1) is performed.
(C) or in step S3) of FIG.
Since the relatively high-temperature heat treatment at 900 ° C. is performed, oxygen is supplied into the titanium from the silicon oxide film serving as the sidewall insulating film 106, and a thick titanium oxide film that is relatively difficult to etch with an etchant is formed. There is. If the unreacted titanium layer remains due to insufficient nitridation of the titanium film on the silicon oxide film by RTA treatment in a nitrogen atmosphere at 600 ° C. to 700 ° C., the heat treatment at a relatively high temperature of 700 ° C. to 900 ° C. In addition, there is a problem that the silicon element diffuses from the gate electrode 104 and the source electrode / drain electrode 107 to form a titanium silicide layer on the silicon oxide film.

Due to these problems, the gate electrode 10
4 and the source electrode / drain electrode 107 could not be sufficiently insulated, increasing the leakage current in the MOS FET 10 and possibly deteriorating the performance of the MOS FET 10. On the other hand, in the method of manufacturing the semiconductor device 10 of the present embodiment, the maximum heat treatment temperature in the first rapid heat treatment step (FIG. 1C or step S3 in FIG. 2) is 750 ° C. or less, which is the first prior art. Since the gate electrode 104 and the source electrode / drain electrode 107 can be sufficiently insulated because the temperature is set at a relatively low temperature similar to that described above, there is an effect that deterioration of the performance of the MOSFET 10 can be avoided.

Next, in FIG. 4 (FIG. 1 (e)), the second
Rapid heat treatment step (FIG. 1 (e) or step S in FIG. 2)
By 5), a relatively low-resistance silicide layer (TiSi2) C54 phase of a high melting point metal is formed. The second rapid heat treatment step (FIG. 1E or step S5 in FIG. 2) is generally performed by a rapid heat treatment at 800 ° C. to 850 ° C., and is performed in a nitrogen atmosphere or an argon atmosphere. Since the nitrided titanium film on the side wall insulating film 106 has been removed by etching in the above-described process, there is no problem in insulation even if the RTA process is performed in an argon gas atmosphere.
Rapid heat treatment step (FIG. 1 (c) or step S in FIG. 2)
Titanium silicide (TiSi2) C4 formed in 3)
This is preferable because nine phases are not nitrided. The first
Rapid heat treatment step (FIG. 1 (c) or step S in FIG. 2)
The relatively high resistance titanium silicide (T) formed in 3)
The iSi2) C49 phase is subjected to a second rapid heat treatment step (FIG. 1).
By (e) or step S5 in FIG. 2, a phase transition to a titanium silicide (TiSi2) C54 phase having a relatively low resistance is performed. According to the method for manufacturing a semiconductor device of the present invention, the C49 phase formed is relatively uniform and relatively fine,
Easily phase transition to C54 phase. As a result, the gate electrode 104 and the source / drain electrode 10
7, the layer resistance of the titanium silicide layer is sufficiently lower than that of the first prior art.

Second Rapid Heat Treatment Step (Step S5)
As shown in FIG. 1E, the high-resistance silicide layer 403 formed in the first rapid thermal processing step (FIG. 1C or step S3 in FIG. 2) is subjected to a rapid thermal processing to This is a step of reducing the resistance of the layer 403.

As described above, according to the present embodiment, high-resistance polycrystallization is performed in the first rapid thermal processing step (step S3 in FIG. 1C or FIG. 2) in the process of manufacturing the salicide structure 11. By performing this, it is possible to obtain an effect that a relatively high-resistance titanium silicide can be formed uniformly, relatively finely, and relatively easily by using an amorphous silicide layer as a growth nucleus.

The titanium silicide thus formed is:
A second rapid thermal processing step (FIG. 1) which is a post-process of the first rapid thermal processing step (FIG. 1C or step S3 in FIG. 2).
In step (e) or step S5 in FIG. 2, an effect is obtained that a phase transition can be easily made to titanium silicide having a relatively low resistance.

According to this, the MOS of the salicide structure 11 is formed.
There is an effect that the resistance of the gate electrode 104 and the source electrode / drain electrode 107 in the FET can be reduced.

As a result, the layer resistance is sufficiently reduced even in the fine lines of 1 μm or less of the gate electrode 104 and the source / drain electrodes 107. Therefore, the first
The increase in the layer resistance of the thin wire as in the prior art is suppressed, the resistance of the gate electrode 104 and the source electrode / drain electrode 107 can be reduced, the parasitic resistance is reduced, and the speed of the fine MOS FET is reduced. There is an effect that the performance can be improved.

That is, 1 μm having the salicide structure 11
In the following fine gate electrode 104 and source electrode / drain electrode 107, the resistance of the silicide layer on the gate electrode 104 and the source electrode / drain electrode 107 is suppressed from being increased, and is low without depending on the line width of the electrode wiring. Salicide structure 1 that can realize silicide layer having layer resistance
1 can be formed.

[0254]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Various embodiments of the method for manufacturing a semiconductor device 10 according to the present invention will be described below.

First, the first embodiment will be described.

In the following embodiments, the layer resistance of the titanium silicide layer uses the gate electrode 104 implanted with arsenic and the gate electrode 104 implanted with boron. FIG. 1 (a)
As shown in FIG. 3, an n-channel MOSFET 10 and a p-channel MOSFET 10 having a salicide structure formed thereon.
Is prepared.

At this time, the impurity implantation into the gate electrode 104 and the source electrode / drain electrode 107 of the n-channel MOS FET 10 and the p-channel MOS FET 10 is performed simultaneously after the formation of the side wall insulating film 106, and the side wall insulating curtain 1 is formed.
06 and the field oxide film 102 as an implantation mask,
For the n-channel MOS FET 10, arsenic is implanted under the conditions of an acceleration voltage of 30 keV and a dose of 3 × 10 ¹⁵ cm ⁻² , and for the p-channel MOS FET 10, BF2 is accelerated at an acceleration voltage of 20 keV and a dose of Amount = 3 x 1
The injection was performed at an injection condition of 0 ¹⁵ cm ^-2 .

As the sidewall insulating film 106, a silicon oxide film formed by a thermal CVD method is used, and has a thickness of 150 nm.
m. The minimum size of the gate electrode 104 is 0.30
It was formed up to μm. After impurity implantation, rapid thermal treatment RT
Activation at 950 ° C. was performed by Method A.

Next, as shown in FIG. 1B, titanium, which is a high melting point metal, was formed by sputtering using a DC magnetron sputtering method. At this time, the titanium film was deposited to a thickness of 35 nm.

Next, as shown in FIG. 1C, a first RTA process which is a feature of the present invention was performed. The heat treatment at 500 ° C. for 60 seconds was performed in a nitrogen atmosphere continuously, almost in the same manner as the heat treatment process shown in FIG.

Next, as shown in FIG. 1D, unreacted titanium and nitrided titanium were selectively removed by etching with respect to the titanium silicide layer by using a mixed solution of hydrogen peroxide, ammonia and water. .

Thereafter, as shown in FIG. 1E, a second rapid heat treatment step (step S5) is performed in a nitrogen atmosphere.
The test was performed at 850 ° C. for 10 seconds.

After that, an interlayer insulating film was formed, a connection hole between an electrode and a metal wiring was formed, and a metal wiring was formed in a normal MOSFET 10 manufacturing process.

FIG. 5 is a graph for explaining the line width dependency of the layer resistance of the titanium silicide layer on the gate electrode 104 obtained in the first embodiment.
The dotted line (curve A) and the one-dot chain line (curve B) show the gate electrode 1 of the layer resistance of the electrode obtained by the manufacturing method of the first prior art.
FIG. 5A shows the line width dependency of the gate electrode 104, and the solid line (curve C) shows the line width dependency of the layer resistance of the electrode obtained by the method of manufacturing a semiconductor device of the present invention. n
FIG. 5B is a graph for explaining the line width dependency of the layer resistance of the gate electrode 104 into which arsenic has been implanted during the fabrication of the channel transistor. FIG. 6 is a graph for explaining the dependence of the layer resistance of the gate electrode 104 on the line width of the gate electrode 104.

In FIGS. 5A and 5B, the solid line is
The layer resistance of the electrode obtained by the method for manufacturing a semiconductor device of the present invention is shown, and the dotted line and the dashed line indicate the layer resistance of the same electrode obtained by the manufacturing method of the first prior art. The dotted line is the first
Rapid heat treatment step (FIG. 1 (c) or step S in FIG. 2)
As 3), a heat treatment at 700 ° C. for 30 seconds was performed in a nitrogen atmosphere, and the dashed line indicates a heat treatment at 700 ° C. for 60 seconds performed in a nitrogen atmosphere as a first rapid heat treatment step. .

As shown in FIGS. 5A and 5B, the layer resistance of the titanium silicide gate electrode 104 is reduced, and both the gate electrode 104 into which arsenic is implanted and the gate electrode 104 into which boron is implanted are formed. It can be seen that a low-resistance layer resistance almost independent of the line width is obtained.

Also, since the layer resistance is not reduced in the manufacturing method of the first prior art shown by the dashed line,
The lowering of the layer resistance in the first embodiment is not due to the formation time of the titanium silicide C49 phase,
It is thought that this is due to the formation of the amorphous titanium silicide layer due to the heat treatment at a low temperature of ℃.

Next, a second embodiment will be described.

As shown in FIG. 1A, a case is considered where an n-channel MOSFET 10 and a p-channel MOSFET 10 having a salicide structure are formed.

At this time, the implantation of impurities into the gate electrode 104 and the source / drain electrodes 107 of the n-channel MOS FET 10 and the p-channel MOS FET 10 is performed simultaneously after the formation of the sidewall insulating film 106,
06 and the field oxide film 102 as an implantation mask,
For channel MOS FET 10, arsenic accelerating voltage = 30 keV, performed at injection a dose of ^{= 3 × 10 15 cm -2,} BF2 acceleration voltage for p-channel MOS FET 10 = 20 keV, a dose = 3 × 10 ¹⁵
The injection was performed under the condition of cm ⁻² .

As the sidewall insulating film 106, a silicon oxide film formed by a thermal CVD method is used, and the film thickness is 150 n.
m. The minimum size of the gate electrode 104 is 0.30
It was formed up to μm. After impurity implantation, rapid thermal treatment RT
Activation at 950 ° C. was performed by Method A.

Next, as shown in FIG. 1B, titanium, which is a high melting point metal, was formed by sputtering using a DC magnetron sputtering method. At this time, the titanium film was deposited to a thickness of 35 nm.

Next, as shown in FIG. 1C, the first RTA process was performed.

The heat treatment process shown in FIG.
Heat treatment at 00 ° C. for 60 seconds was performed in an argon gas atmosphere, and heat treatment at 700 ° C. for 30 seconds was performed in a nitrogen atmosphere.

Next, as shown in FIG. 1D, unreacted titanium and nitrided titanium were selectively removed by etching with respect to the titanium silicide layer by using a mixed solution of hydrogen peroxide, ammonia and water. .

Thereafter, as shown in FIG. 1E, a second rapid heat treatment step (step S5) is performed in a nitrogen atmosphere.
The test was performed at 850 ° C. for 10 seconds. After that, normal MOS FET
In the ten manufacturing steps, formation of an interlayer insulating film, formation of connection holes between electrodes and metal wiring, and formation of metal wiring were performed.

FIG. 6 is a graph for explaining the line width dependency of the layer resistance of the titanium silicide layer on the gate electrode 104 into which arsenic was implanted during the fabrication of the n-channel transistor, and the dotted line (curve A) is a graph for explaining the dependence of the layer resistance of the gate electrode 104 on the line width of the gate electrode 104 obtained by the manufacturing method of the first prior art, and the solid line (curve B) is obtained by the second embodiment. 6 is a graph for explaining the dependence of the layer resistance of the gate electrode 104 on the line width of the gate electrode 104.

In FIG. 6, the vertical axis represents an n-channel MOS
This is the layer resistance of the gate electrode 104 into which arsenic of the FET 10 has been implanted. The solid line represents the layer resistance of the electrode obtained by the method of manufacturing a semiconductor device of the present invention, and the dotted line represents the layer resistance of the same electrode obtained by the method of manufacturing the first prior art.
The dotted line indicates the first rapid heat treatment step (FIG. 1C).
Alternatively, as step S3) in FIG. 2, a heat treatment at 700 ° C. for 30 seconds is performed in a nitrogen atmosphere.

As shown in FIG. 6, according to the manufacturing method of the second embodiment, the layer resistance of the titanium silicide gate electrode 104 is reduced, and a low-resistance layer resistance almost independent of the line width is obtained. You can see that there is.

Further, it is considered that the layer resistance of the thin wire is further reduced as compared with the manufacturing method of the present invention shown in FIG.

The reason for this is that since the heat treatment at 500 ° C. was performed in an argon gas atmosphere, nitriding of the titanium surface was not performed at all during the heat treatment, and the nitriding of the titanium surface started at the stage of the heat treatment at 700 ° C. for the first time. It is thought that this is because, though slightly, the formation of the titanium silicide (TiSi2) C49 phase was promoted.

When the heat treatment at 500 ° C. is performed in an argon gas atmosphere, the gate electrode 104 on the side wall insulating film 106 is formed.
There is a concern that titanium silicide may be formed due to diffusion of silicon from the source electrode / drain electrode 107. However, since the process is performed at a relatively low temperature of 500 ° C., the growth rate is very slow. In the case of the etching shown in FIG.

Next, a third embodiment will be described.

Also, the layer resistance of the titanium silicide layer obtained in the third embodiment will be described in comparison with the first prior art, taking the gate electrode 104 implanted with arsenic as an example.

As shown in FIG. 1A, an n-channel MOSFET 10 and a p-channel MOSFET 10 having a salicide structure are manufactured.

At this time, impurity implantation into the gate electrode 104 and the source / drain electrodes 107 of the n-channel MOS FET 10 and the p-channel MOS FET 10 is performed simultaneously after the formation of the sidewall insulating film 106,
6 and the field oxide film 102 as implantation masks, arsenic is implanted into the n-channel MOS FET 10 under the conditions of an acceleration voltage = 30 keV and a dose = 3 × 10 ¹⁵ cm ⁻² , The
BF2 is acceleration voltage = 20 keV, dose = 3 × 10 ¹⁵
The injection was performed under the condition of cm ⁻² .

As the sidewall insulating film 106, a silicon oxide film formed by a thermal CVD method is used, and has a thickness of 150 nm.
m. The minimum size of the gate electrode 104 is 0.30
It was formed up to μm.

After the impurity implantation, activation was performed at 950 ° C. by a rapid thermal processing RTA method.

Next, as shown in FIG. 1B, titanium, which is a high melting point metal, was formed by sputtering using a DC magnetron sputtering method. At this time, the titanium film was deposited to a thickness of 35 nm.

Next, as shown in FIG. 1C, a first RTA process which is a feature of the present invention was performed. As in the heat treatment process shown in FIG. 4, heat treatment at 500 ° C. for 60 seconds was performed in a hydrogen gas atmosphere, and heat treatment at 700 ° C. for 30 seconds was performed in a nitrogen atmosphere.

Next, as shown in FIG. 1D, unreacted titanium and nitrided titanium were selectively removed by etching with respect to the titanium silicide layer using a mixed solution of hydrogen peroxide, ammonia and water. .

Thereafter, as shown in FIG. 1E, a second rapid heat treatment step (step S5) is performed in a nitrogen atmosphere.
The test was performed at 850 ° C. for 10 seconds.

After that, an interlayer insulating film was formed, a connection hole between an electrode and a metal wiring was formed, and a metal wiring was formed in a normal MOSFET 10 manufacturing process.

FIG. 7 is a graph for explaining the line width dependence of the layer resistance of the titanium silicide layer on the gate electrode 104 into which arsenic has been implanted during the fabrication of the n-channel transistor. A) is a graph for explaining the line width dependence of the gate resistance of the gate electrode 104 obtained by the manufacturing method of the first prior art, and the solid line (curve B) is obtained by the third embodiment. 6 is a graph for explaining the dependence of the layer resistance of the gate electrode 104 on the line width of the gate electrode 104.

In FIG. 7, the vertical axis represents an n-channel MOS
This is the layer resistance of the gate electrode 104 into which arsenic of the FET 10 has been implanted. The solid line represents the layer resistance of the electrode obtained by the method of manufacturing a semiconductor device of the present invention, and the dotted line represents the layer resistance of the same electrode obtained by the method of manufacturing the first prior art. The dotted line is obtained by performing a heat treatment at 700 ° C. for 30 seconds in a nitrogen atmosphere as a first rapid heat treatment process (step S3 in FIG. 1C or FIG. 2).

It can be seen that the layer resistance of the titanium silicide gate electrode 104 was reduced by the manufacturing method of the present invention, and a low layer resistance completely independent of the line width was obtained.

Further, it is considered that the layer resistance is further reduced in the thin wires even in comparison with the manufacturing method of the present invention shown in FIG.

The reason for this is that the heat treatment at 500 ° C. was performed in a hydrogen gas atmosphere, so that the titanium surface was not nitrided at all during the heat treatment. Oxygen or carbon remaining on the source / drain electrodes 107 was reduced by diffusion of hydrogen during the heat treatment at 500 ° C., thereby further promoting the formation of the C49 phase at the heat treatment at 700 ° C. Is thought to be.

Since the heat treatment at 500 ° C. is performed in a hydrogen gas atmosphere, the gate electrode 104 on the side wall insulating film 106 is formed.
There is a concern that titanium silicide may be formed due to diffusion of silicon from the source electrode / drain electrode 107.
Since the treatment is performed at a relatively low temperature of 00 ° C., the growth rate is very low, and sufficient insulation can be achieved at the time of etching shown in FIG.

[0300]

According to the first aspect of the present invention, an amorphous silicide layer is grown by performing high-resistance polycrystallization in the first rapid heat treatment step in the salicide structure manufacturing process. As a nucleus, there is an effect that a relatively high-resistance refractory metal silicide can be formed uniformly, relatively finely and relatively easily.

The high melting point metal silicide thus formed is easily phase-transformed to a relatively low resistance high melting point metal silicide in the second rapid heat treatment step which is a step subsequent to the first rapid heat treatment step. This has the effect of being able to perform.

According to this, the MOS F of the salicide structure
This has the effect that the resistance of the gate electrode and the source electrode / drain electrode in ET can be reduced.

[0303] As a result, the layer resistance is sufficiently reduced even in the fine lines of 1 μm or less of the gate electrode and the source electrode / drain electrode. Thereby, the increase in the layer resistance of the thin wire as seen in the first prior art is suppressed,
Gate electrode and source electrode / drain electrode can have low resistance, parasitic resistance decreases, and fine MOS FET
This has the effect that the speed performance of the vehicle can be improved.

That is, in the fine gate electrode and the source electrode / drain electrode having a salicide structure of 1 μm or less, the resistance of the silicide layer on the gate electrode and the source electrode / drain electrode is suppressed from increasing, and the line of the electrode wiring is suppressed. There is an effect that a salicide structure capable of realizing a silicide layer having a low layer resistance without depending on the width can be formed.

According to the second aspect of the present invention, the first aspect
The same effect as the effect described in (1) is obtained.

According to the invention set forth in claim 3, according to claim 2
The same effect as the effect described in (1) is obtained.

[0307] According to the invention described in claim 4, according to claim 2 of the present invention.
Or, in addition to the effect described in 3, the refractory metal film deposited and the polycrystal forming the gate electrode are formed by performing the amorphizing step of the first rapid thermal processing step in the salicide structure manufacturing process. This has the effect that a relatively amorphous silicide layer can be formed at the interface between silicon and the silicon substrate constituting the source / drain electrodes.

After that, by performing the high-resistance polycrystallization step of the first rapid heat treatment step, the amorphous silicide layer formed in the amorphization step is used as a growth nucleus to obtain a relatively high resistance. A high refractory metal silicide can be formed uniformly, relatively finely and relatively easily.

The high melting point metal silicide thus formed is easily phase-transformed into a relatively low resistance high melting point metal silicide in a second rapid heat treatment step which is a step subsequent to the first rapid heat treatment step. This has the effect of being able to perform.

According to this, MOS F of salicide structure is used.
This has the effect that the resistance of the gate electrode and the source electrode / drain electrode in ET can be reduced.

According to the invention described in claim 5, according to claim 2,
Or, in addition to the effect described in 3, the refractory metal film deposited and the polycrystal forming the gate electrode are formed by performing the amorphizing step of the first rapid thermal processing step in the salicide structure manufacturing process. This has the effect that a relatively amorphous silicide layer can be formed at the interface between silicon and the silicon substrate constituting the source / drain electrodes.

Thereafter, the amorphous silicide layer formed in the amorphizing step is formed by performing a high-resistance poly-crystallizing step for polycrystallizing and increasing the resistance of the amorphous silicide layer. With growth as the nucleus of growth, a relatively high-resistance refractory metal silicide is formed uniformly, relatively finely and relatively easily.

The thus formed refractory metal silicide easily undergoes a phase transition to a relatively low-resistance refractory metal silicide in a second rapid heat treatment step which is a step subsequent to the first rapid heat treatment step. This has the effect of being able to perform.

According to this, the MOS F of the salicide structure is formed.
This has the effect that the resistance of the gate electrode and the source electrode / drain electrode in ET can be reduced.

According to the invention described in claim 6, according to claim 4,
Or in addition to the effect described in 5, the refractory metal film deposited and the polycrystal forming the gate electrode are formed by performing the amorphizing step of the first rapid heat treatment step in the salicide structure manufacturing process. This has the effect that a relatively amorphous silicide layer can be formed at the interface between silicon and the silicon substrate constituting the source / drain electrodes.

Thereafter, the amorphous silicide layer formed in the amorphization step is formed by performing a high-resistance polycrystallization step for polycrystallizing and increasing the resistance of the amorphous silicide layer. With growth as the nucleus of growth, a relatively high-resistance refractory metal silicide is formed uniformly, relatively finely and relatively easily.

The high melting point metal silicide thus formed is easily transformed into a relatively low resistance high melting point metal silicide in a second rapid heat treatment step, which is a step subsequent to the first rapid heat treatment step. The effect that it becomes possible to do it is produced.

According to this, MOS F of salicide structure is used.
This has the effect that the resistance of the gate electrode and the source electrode / drain electrode in ET can be reduced.

[0319] According to the invention of claim 7, according to claim 4,
Or in addition to the effect described in 6, the amorphizing step of the first rapid heat treatment step in the salicide structure manufacturing process is performed at 400 ° C.
By performing the process at a relatively low temperature of about 550 ° C., a relatively amorphous film is formed at the interface between the deposited refractory metal film and the polycrystalline silicon constituting the gate electrode and the silicon substrate constituting the source / drain electrodes. This produces an effect that a high quality silicide layer can be formed.

By performing the amorphizing step of the first rapid heat treatment step at a relatively low temperature of 400 ° C. to 550 ° C.,
There is an effect that an amorphous high-melting-point metal silicide layer can be formed without forming relatively high-resistance high-melting-point metal silicide which is easily formed at 600 ° C. or higher.

Thereafter, the amorphous silicide layer formed in the amorphization step is formed by performing a polycrystallization process for the amorphous silicide layer and a high resistance polycrystallization step for increasing the resistance. With growth as the nucleus of growth, a relatively high-resistance refractory metal silicide is formed uniformly, relatively finely and relatively easily.

The high melting point metal silicide thus formed is easily transformed into a relatively low resistance high melting point metal silicide in a second rapid heat treatment step which is a subsequent step following the first rapid heat treatment step. The effect that it becomes possible to do it is produced.

According to this, MOS F of salicide structure is used.
This has the effect that the resistance of the gate electrode and the source electrode / drain electrode in ET can be reduced.

[0324] According to the invention of claim 8, according to claim 4,
Or in addition to the effect described in 6, the heat treatment at a relatively low temperature in the amorphizing step of the first rapid heat treatment step and the heat treatment at a relatively high temperature in the high resistance polycrystallization step are performed in a nitrogen atmosphere. As a result, the amorphization step and the high-resistance polycrystallization step can be performed without replacing the atmosphere gas.
This has the effect of improving the throughput of the first rapid heat treatment step. The reason why such a high-resistance polycrystallization process is desirably performed in a nitrogen atmosphere is that, during heat treatment, silicon diffuses from the polycrystalline silicon forming the gate electrode and the silicon substrate forming the source / drain electrodes, and It is considered that titanium is nitrided from the titanium surface in order to suppress formation of a titanium silicide layer on the insulating film.

The amorphous formation step of the first rapid heat treatment step in the salicide structure fabrication process is performed by performing a relatively low temperature heat treatment at 400 ° C. to 550 ° C. in a nitrogen gas atmosphere. This has the effect that a relatively amorphous silicide layer can be formed at the interface between the melting point metal film and the polycrystalline silicon forming the gate electrode and the silicon substrate forming the source / drain electrodes.

By performing the amorphizing step of the first rapid heat treatment step at a relatively low temperature of 400 ° C. to 550 ° C.,
There is an effect that an amorphous high-melting-point metal silicide layer can be formed without forming relatively high-resistance high-melting-point metal silicide which is easily formed at 600 ° C. or higher.

Thereafter, the amorphous silicide layer formed in the amorphization step is formed by performing a polycrystallization process of the amorphous silicide layer and a high resistance polycrystallization step for increasing the resistance. With growth as the nucleus of growth, a relatively high-resistance refractory metal silicide is formed uniformly, relatively finely and relatively easily.

The high melting point metal silicide thus formed is easily transformed into a relatively low resistance high melting point metal silicide in a second rapid heat treatment step, which is a subsequent step following the first rapid heat treatment step. The effect that it becomes possible to do it is produced.

According to this, MOS F of salicide structure is used.
This has the effect that the resistance of the gate electrode and the source electrode / drain electrode in ET can be reduced.

According to the ninth aspect of the present invention, the fourth aspect of the present invention is provided.
Or in addition to the effect described in 6, the relatively low-temperature heat treatment of the amorphization step of the first rapid heat treatment step is performed in an argon gas atmosphere, and the relatively high-temperature heat treatment of the high-resistance polycrystallization step is performed. By performing in a nitrogen atmosphere, the titanium surface is not nitrided at all during the heat treatment at a relatively low temperature in the amorphization step, and the titanium surface is not treated for the first time during the heat treatment at a relatively high temperature in the high-resistance polycrystallization step. Since the nitridation of the alloy begins, the effect of slightly promoting the formation of the titanium silicide (TiSi2) C49 phase is obtained.

As a result, the titanium silicide (TiSi 2) C54 phase is sufficiently formed in the second rapid heat treatment step, and the layer resistance of the titanium silicide layer in the fine wire is reduced.

Since the heat treatment at 500 ° C. is performed in an argon gas atmosphere, there is a concern that titanium silicide may be formed on the sidewall insulating film due to diffusion of silicon from the gate electrode and the source / drain electrodes. Since the treatment is performed at a relatively low temperature, the growth rate is very slow, and an effect is obtained that insulation can be sufficiently performed at the time of etching.

Further, the amorphizing step of the first rapid heat treatment step in the process of forming the salicide structure is performed at 400 ° C. to 550 ° C.
By performing a relatively low-temperature heat treatment in an argon gas atmosphere that is inert and easily obtains high purity, the deposited high melting point metal film, polycrystalline silicon forming the gate electrode, and the source electrode / drain electrode are formed. A relatively amorphous silicide layer is formed with high purity at the interface with the silicon substrate to be formed.

Thereafter, the amorphous silicide layer formed in the amorphization step is formed by performing a polycrystallization process of the amorphous silicide layer and a high-resistance polycrystallization step for increasing the resistance. With growth as the nucleus of growth, a relatively high-resistance refractory metal silicide is formed uniformly, relatively finely and relatively easily.

The thus formed refractory metal silicide easily undergoes a phase transition to a relatively low-resistance refractory metal silicide in a second rapid heat treatment step which is a step subsequent to the first rapid heat treatment step. The effect that it becomes possible to do it is produced.

According to this, MOS F of salicide structure is used.
This has the effect that the resistance of the gate electrode and the source electrode / drain electrode in ET can be reduced.

According to the tenth aspect of the invention, in addition to the effect of the fourth or sixth aspect, the relatively low temperature heat treatment in the amorphizing step of the first rapid heat treatment step is performed in a hydrogen gas atmosphere. By performing the relatively high-temperature heat treatment of the high-resistance polycrystallization process in a nitrogen atmosphere in a nitrogen atmosphere, so that the titanium surface is not nitrided at all during the relatively low-temperature heat treatment of the amorphization process. This has the effect. Further, oxygen or carbon remaining on the gate electrode and the source electrode / drain electrode mixed in the process of manufacturing the MOS FET 10 is reduced to 500 ° C.
Is reduced by the diffusion of hydrogen during the heat treatment of
This has the effect of promoting the formation of the titanium silicide C49 phase at the relatively high temperature heat treatment stage of the high resistance polycrystallization process.

Accordingly, in the second rapid heat treatment step, the titanium silicide C54 phase is sufficiently formed, and the effect is obtained that the layer resistance of the titanium silicide layer in the fine wire can be further reduced.

Also, by performing the heat treatment at 500 ° C. in a hydrogen gas atmosphere, there is a concern that titanium silicide may be formed on the sidewall insulating film due to diffusion of silicon from the gate electrode and the source / drain electrodes. Since the treatment is performed at a relatively low temperature of 500 ° C., the growth rate is very slow, and there is an effect that insulation can be sufficiently performed during etching.

Further, the amorphizing step of the first rapid heat treatment step in the process of forming the salicide structure is performed at 400 ° C. to 550 ° C.
Is performed in a nitrogen gas, argon gas, or hydrogen gas atmosphere in which high purity can be easily obtained, thereby depositing a high melting point metal, polycrystalline silicon constituting a gate electrode, and a source electrode / drain electrode. A relatively amorphous high-melting-point metal silicide layer is formed with high purity at the interface with the silicon substrate.

Thereafter, the high-resistance polycrystallizing step for polycrystallizing the amorphous silicide layer and increasing the resistance is performed, whereby the amorphous high melting point formed in the amorphizing step is formed. Using the metal silicide layer as a nucleus for growth, a relatively high-resistance high-melting-point metal silicide is formed uniformly, relatively finely, and relatively easily.

The refractory metal silicide thus formed is easily transformed into a relatively low-resistance refractory metal silicide in a second rapid heat treatment step, which is a subsequent step following the first rapid heat treatment step. The effect that it becomes possible to do it is produced.

According to this, the MOS F of the salicide structure is used.
This has the effect that the resistance of the gate electrode and the source electrode / drain electrode in ET can be reduced.

According to the eleventh aspect of the present invention, in addition to the effect of the fourth or sixth aspect, the amorphizing step of the first rapid heat treatment step in the process of forming the salicide structure is performed by 400 steps.
By performing a relatively low-temperature heat treatment at a temperature of from about 550 ° C. to about 550 ° C. in a nitrogen gas, argon gas, or hydrogen gas atmosphere in which high purity is easily obtained, a deposited titanium film, polycrystalline silicon constituting a gate electrode, and a source electrode A relatively amorphous titanium silicide layer is formed with high purity at the interface with the silicon substrate constituting the drain / drain electrode.

By performing the amorphizing step of the first rapid heat treatment step at a relatively low temperature of 400 ° C. to 550 ° C.,
There is an effect that an amorphous titanium silicide layer can be formed without forming relatively high-resistance titanium silicide which is easily formed at 600 ° C. or higher.

Thereafter, the amorphous titanium silicide formed in the amorphizing step is formed by executing a high-resistance poly-crystallizing step for polycrystallizing and increasing the resistance of the amorphous silicide layer. Titanium silicide having a relatively high resistance is formed uniformly, relatively finely and relatively easily, with the layer as a nucleus of growth.

The titanium silicide C4 thus formed
Ninth phase is a second step which is a post-step following the first rapid heat treatment step.
In the rapid heat treatment step, there is an effect that the phase can be easily changed to the titanium silicide C54 phase having a relatively low resistance.

According to this, there is an effect that the resistance of the titanium silicide layer in the thin lines of the gate electrode and the source electrode / drain electrode is eventually reduced. Also, during the amorphization step, it is relatively difficult for silicon to diffuse from the polycrystalline silicon constituting the gate electrode and the silicon substrate constituting the source electrode / drain electrode to form a titanium silicide layer on the sidewall insulating film. The effect is small because it is performed at a low temperature. Accordingly, there is an effect that the problem of leakage of the gate electrode and the source electrode / drain electrode does not occur.

That is, in the fine gate electrode and the source electrode / drain electrode having a salicide structure of 1 μm or less, the resistance of the silicide layer on the gate electrode and the source electrode / drain electrode is suppressed from increasing, and the line of the electrode wiring is suppressed. There is an effect that a salicide structure capable of realizing a silicide layer having a low layer resistance without depending on the width can be formed.

According to the twelfth aspect of the present invention, in addition to the effect of the fifth or sixth aspect, the amorphizing step of the first rapid heat treatment step in the process of forming the salicide structure is performed by 400 steps.
By performing a relatively low-temperature heat treatment at a temperature of about 550 ° C. to about 550 ° C. in a nitrogen gas, argon gas or hydrogen gas atmosphere in which high purity is easily obtained, the deposited high melting point metal film, polycrystalline silicon forming the gate electrode, A relatively amorphous high-melting-point metal silicide layer is formed with high purity at the interface with the silicon substrate constituting the source / drain electrodes.

By performing the amorphizing step of the first rapid heat treatment step at a relatively low temperature of 400 ° C. to 550 ° C.,
There is an effect that an amorphous high-melting-point metal silicide layer can be formed without forming relatively high-resistance high-melting-point metal silicide which is easily formed at 600 ° C. or higher.

Thereafter, using the amorphous refractory metal silicide layer formed uniformly in this manner as a nucleus for growth, polycrystallizing treatment of the amorphous silicide layer and treatment for increasing the resistance are performed. By performing the crystallization step at a temperature of 600 ° C. to 750 ° C. in a nitrogen gas, argon gas or hydrogen gas atmosphere, an amorphous high melting point metal silicide layer formed in the amorphization step is grown. As a nucleus, a refractory metal silicide having a relatively high resistance is formed uniformly, relatively finely and relatively easily.

The thus formed refractory metal silicide easily undergoes a phase transition to a relatively low-resistance refractory metal silicide in a second rapid heat treatment step which is a subsequent step following the first rapid heat treatment step. The effect that it becomes possible to do it is produced.

According to this, there is an effect that the resistance of the refractory metal silicide layer in the thin wires of the gate electrode and the source electrode / drain electrode is eventually reduced. Also, at the time of the amorphization step, silicon diffuses from the polycrystalline silicon constituting the gate electrode and the silicon substrate constituting the source electrode / drain electrode to form a refractory metal silicide layer on the side wall insulating film. The effect is low because it is performed at a relatively low temperature. Accordingly, there is an effect that the problem of leakage of the gate electrode and the source electrode / drain electrode does not occur.

According to the thirteenth aspect, the same effect as the twelfth aspect can be obtained.

According to the fourteenth aspect, the same effect as the fifth or sixth aspect can be obtained.

According to the fifteenth aspect, the same effect as the fifth or sixth aspect can be obtained.

According to the sixteenth aspect of the present invention, in addition to the effect of the fourth or sixth aspect, the amorphizing step of the first rapid heat treatment step in the salicide structure manufacturing process is performed by 400 steps.
By performing a relatively low-temperature heat treatment at a temperature of 550 ° C. to 550 ° C. in a nitrogen gas atmosphere in which high purity can be easily obtained, the deposited titanium film, polycrystalline silicon constituting the gate electrode, and the source electrode / drain electrode are formed. A relatively amorphous titanium silicide layer is formed with high purity at the interface with the silicon substrate to be constituted.

By performing the amorphizing step of the first rapid heat treatment step at a relatively low temperature of 400 ° C. to 550 ° C.,
There is an effect that an amorphous titanium silicide layer can be formed without forming relatively high-resistance titanium silicide which is easily formed at 600 ° C. or higher.

Thereafter, using the amorphous titanium silicide layer formed uniformly in this way as a nucleus for growth, a polycrystallizing treatment of the amorphous silicide layer and a high resistance polycrystallizing treatment for increasing the resistance are carried out. By performing the process at a temperature of 600 ° C. to 750 ° C. in a nitrogen gas, argon gas or hydrogen gas atmosphere, the amorphous titanium silicide layer formed in the amorphization process is used as a growth nucleus. A relatively high-resistance titanium silicide is formed uniformly, relatively finely and relatively easily.

The titanium silicide C4 thus formed
Ninth phase is a second step which is a post-step following the first rapid heat treatment step.
In the rapid heat treatment step, there is an effect that the phase can be easily changed to the titanium silicide C54 phase having a relatively low resistance.

According to this, there is an effect that the resistance of the titanium silicide layer is finally reduced in the thin lines of the gate electrode and the source electrode / drain electrode. Also, during the amorphization step, it is relatively difficult for silicon to diffuse from the polycrystalline silicon constituting the gate electrode and the silicon substrate constituting the source electrode / drain electrode to form a titanium silicide layer on the sidewall insulating film. The effect is small because it is performed at a low temperature. Accordingly, there is an effect that the problem of leakage of the gate electrode and the source electrode / drain electrode does not occur.

According to the seventeenth aspect of the present invention, in addition to the effect of the fourth or sixth aspect, the amorphizing step of the first rapid heat treatment step in the salicide structure manufacturing process is performed by 400 steps.
By performing the heat treatment at a relatively low temperature of about 550 ° C. to about 550 ° C. in an argon gas atmosphere in which high purity can be easily obtained, the deposited titanium film, the polycrystalline silicon constituting the gate electrode, and the source electrode / drain electrode are formed. A relatively amorphous titanium silicide layer is formed with high purity at the interface with the silicon substrate to be constituted.

By performing the amorphizing step of the first rapid heat treatment step at a relatively low temperature of 400 ° C. to 550 ° C.,
There is an effect that an amorphous titanium silicide layer can be formed without forming relatively high-resistance titanium silicide which is easily formed at 600 ° C. or higher.

Thereafter, using the amorphous titanium silicide layer formed uniformly in this manner as a nucleus for growth, a polycrystallizing treatment of the amorphous silicide layer and a high resistance polycrystallizing treatment for increasing the resistance are carried out. By performing the process at a temperature of 600 ° C. to 750 ° C. in a nitrogen gas, argon gas or hydrogen gas atmosphere, the amorphous titanium silicide layer formed in the amorphization process is used as a growth nucleus. A relatively high-resistance titanium silicide is formed uniformly, relatively finely and relatively easily.

The titanium silicide C4 thus formed
Ninth phase is a second step which is a post-step following the first rapid heat treatment step.
In the rapid heat treatment step, there is an effect that the phase can be easily changed to the titanium silicide C54 phase having a relatively low resistance.

According to this, there is an effect that the resistance of the titanium silicide layer is finally reduced in the thin lines of the gate electrode and the source / drain electrodes. Also, during the amorphization step, it is relatively difficult for silicon to diffuse from the polycrystalline silicon constituting the gate electrode and the silicon substrate constituting the source electrode / drain electrode to form a titanium silicide layer on the sidewall insulating film. The effect is small because it is performed at a low temperature. Accordingly, there is an effect that the problem of leakage of the gate electrode and the source electrode / drain electrode does not occur.

According to the eighteenth aspect of the present invention, in addition to the effect of the fourth or sixth aspect, the amorphizing step of the first rapid heat treatment step in the salicide structure manufacturing process is performed by 400 steps.
By performing a relatively low-temperature heat treatment at a temperature of from about 550 ° C. to about 550 ° C. in an atmosphere of a nitrogen gas, an argon gas, or a hydrogen gas atmosphere in which high purity is easily obtained, the deposited titanium film, polycrystalline silicon constituting a gate electrode, A relatively amorphous titanium silicide layer is formed with high purity at the interface with the silicon substrate forming the source / drain electrodes.

By performing the amorphizing step of the first rapid heat treatment step at a relatively low temperature of 400 ° C. to 550 ° C.,
There is an effect that an amorphous titanium silicide layer can be formed without forming relatively high-resistance titanium silicide which is easily formed at 600 ° C. or higher.

Then, using the amorphous titanium silicide layer formed uniformly in this way as a nucleus for growth, polycrystallizing treatment of the amorphous silicide layer and high resistance polycrystallizing for increasing the resistance are performed. By performing the process at a temperature of 600 ° C. to 750 ° C. in a hydrogen gas atmosphere, a relatively high-resistance titanium is used as a growth nucleus using the amorphous titanium silicide layer formed in the amorphization process. The silicide is formed uniformly, relatively finely and relatively easily.

The titanium silicide C4 thus formed
Ninth phase is a second step which is a post-step following the first rapid heat treatment step.
In the rapid heat treatment step, there is an effect that the phase can be easily changed to the titanium silicide C54 phase having a relatively low resistance.

According to this, there is an effect that the resistance of the titanium silicide layer is finally reduced in the thin lines of the gate electrode and the source / drain electrodes. Also, during the amorphization step, it is relatively difficult for silicon to diffuse from the polycrystalline silicon constituting the gate electrode and the silicon substrate constituting the source electrode / drain electrode to form a titanium silicide layer on the sidewall insulating film. The effect is small because it is performed at a low temperature. Accordingly, there is an effect that the problem of leakage of the gate electrode and the source electrode / drain electrode does not occur.

According to the nineteenth aspect, an effect similar to the effect according to any one of the first to eighteenth aspects is obtained.

According to the twentieth aspect of the present invention, in addition to the effects of any one of the first to eighteenth aspects, the use of titanium as a refractory metal has a low resistivity. In addition, it is possible to form a silicide layer having relatively high heat resistance. Titanium also has the advantage of having the lowest resistivity of silicide and relatively heat resistance among the high melting point metal titanium, cobalt, nickel, platinum and the like usually used to form a salicide structure. . Further, there is an effect that an amorphous titanium silicide layer can be formed relatively easily in the amorphizing step of 400 ° C. to 550 ° C. in the first rapid heat treatment step.

According to the twenty-first aspect of the present invention, in addition to the effect of any one of the first to eighteenth aspects, a low resistivity is obtained by using titanium nitride as a high melting point metal. This has an effect that a silicide layer having a relatively high heat resistance can be formed. Titanium nitride also has the advantage of having the lowest silicide resistivity and relatively heat resistance among refractory metal nitrides usually used to form salicide structures. Further, there is an effect that an amorphous titanium silicide layer can be formed relatively easily in the amorphizing step of 400 ° C. to 550 ° C. in the first rapid heat treatment step.

According to the twenty-second aspect of the present invention, in addition to the effects of any one of the first to eighteenth aspects, the use of titanium oxide as a refractory metal enables low resistivity. This has an effect that a silicide layer having a relatively high heat resistance can be formed. Titanium nitride also has the advantage of having the lowest silicide resistivity and relatively heat resistance among the refractory metal oxides commonly used to form salicide structures. Further, there is an effect that an amorphous titanium silicide layer can be formed relatively easily in the amorphizing step of 400 ° C. to 550 ° C. in the first rapid heat treatment step.

[Brief description of the drawings]

FIG. 1A is a cross-sectional view of an element structure of a MOS FET in which a source / drain electrode, a gate electrode and a side wall insulating film are formed, and FIG. 1B is a high melting point metal formed by a high melting point metal forming step. FIG. 1 is a cross-sectional view of a device structure of a MOS FET in which a film is deposited on the entire surface of a semiconductor substrate by a sputtering method.
FIG. 1C is a cross-sectional view of a device structure of a MOS FET in which a relatively high-resistance silicide layer of a refractory metal is formed in the first rapid heat treatment step, and FIG. 1D is a sectional view in accordance with the first rapid heat treatment step. The titanium nitride layer formed on the sidewall insulating film, the titanium nitride layer formed on the titanium silicide (TiSi2) C49 phase formed on the gate electrode and the source / drain electrode, and the unreacted titanium layer are formed in the silicide layer forming step. FIG. 1 (e) is a cross-sectional view of a device structure of a MOS FET selectively removed by etching, and FIG. 1 (e) shows a relatively low-resistance silicide layer TiSi of a refractory metal formed by a second rapid heat treatment step.
FIG. 3 is a sectional view of an element structure of a MOS FET in which a 2C54 phase is formed.

FIG. 2 is a process flow chart for explaining a process of forming a salicide structure in the method of manufacturing a semiconductor device according to the present invention.

FIG. 3 is a graph illustrating a temperature profile used in a rapid heat treatment process performed in a conventional rapid heat treatment process.

FIG. 4 is a graph for explaining a temperature profile used in a rapid heat treatment process performed in a first rapid heat treatment process of FIG. 2;

FIG. 5 is a graph for explaining the gate electrode line width dependency of the layer resistance of the titanium silicide layer on the gate electrode obtained by the first embodiment, which is represented by a dotted line (curve A) and a dashed line (curve). B) shows the dependence of the layer resistance of the electrode obtained by the first conventional manufacturing method on the gate electrode line width, and the solid line (curve C) shows the layer resistance of the electrode obtained by the manufacturing method of the semiconductor device of the present invention. FIG. 5A is a graph for explaining the gate electrode line width dependency of the layer resistance of the gate electrode into which arsenic is implanted during the fabrication of an n-channel transistor. FIG. 5B is a graph for explaining the gate electrode line width dependence of the layer resistance of the gate electrode into which boron is implanted during the fabrication of the p-channel transistor.

FIG. 6 is a graph for explaining the gate electrode line width dependence of the layer resistance of a titanium silicide layer on a gate electrode into which arsenic has been implanted during fabrication of an n-channel transistor;
A dotted line (curve A) is a graph for explaining the gate electrode line width dependence of the layer resistance of the gate electrode obtained by the manufacturing method of the first prior art, and a solid line (curve B) is obtained by the second embodiment. 6 is a graph for explaining the dependence of the layer resistance of the gate electrode on the gate electrode line width.

FIG. 7 is a graph for explaining the gate electrode line width dependence of the layer resistance of a titanium silicide layer on a gate electrode into which arsenic has been implanted during fabrication of an n-channel transistor;
A dotted line (curve A) is a graph for explaining the gate electrode line width dependency of the layer resistance of the gate electrode obtained by the manufacturing method of the first prior art, and a solid line (curve B) is obtained by the third embodiment. 6 is a graph for explaining the dependence of the layer resistance of the gate electrode on the gate electrode line width.

FIG. 8 shows a first prior art MOS having a salicide structure.
FIG. 2 is a sectional view of an element structure of the FET.

FIG. 9 is a flowchart of a manufacturing process of a salicide structure of the MOS FET of FIG. 8;

FIG. 10 is a flowchart showing a manufacturing process of a salicide structure of a MOS FET according to a second conventional technique.

[Explanation of symbols]

Reference Signs List 10 MOS transistor 11 salicide structure 101 semiconductor substrate (well) 102 field oxide film (element isolation region) 103 gate oxide film 104 polycrystalline silicon (gate electrode) 105 low-concentration impurity diffusion layer 106 silicon oxide film (sidewall insulating film) 107 High concentration impurity diffusion layer (source / drain electrode) 401 Refractory metal film (Titanium metal film) 402 Titanium nitride layer 403 High resistance silicide layer (Titanium silicide layer C)
49 phase, titanium silicide layer C54 phase) 404 titanium silicide (TiSi2) C54 phase

Claims (21)

[Claims] 1. A M-layer having a salicide structure formed on a gate electrode and a source electrode or a drain electrode by using a silicide film containing a refractory metal in a self-aligned manner.
In a method of manufacturing a semiconductor device having an OS transistor, a high melting point metal forming step of depositing the high melting point metal on the semiconductor substrate; and performing a rapid heat treatment on the high melting point metal film deposited in the high melting point metal forming step. And forming a high-resistance silicide layer having a desired high-resistance value by a two-step first rapid heat treatment step; and selecting the high-melting metal film unreacted in the rapid heat treatment or the nitrided high-melting metal film. A silicide layer forming step of leaving only the high-resistance silicide layer formed in the first rapid heat treatment step, by removing the high-resistance silicide layer formed in the first rapid heat treatment step; A second rapid heat treatment step of performing a rapid heat treatment on the resistance silicide layer to lower the resistance of the high resistance silicide layer; The method of manufacturing a semiconductor device according to claim. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the refractory metal is a step of depositing the refractory metal on the semiconductor substrate by using a sputtering method. . 3. The method according to claim 1, wherein the first rapid heat treatment step includes an amorphization step of performing an amorphization process on the silicide layer to generate an amorphous silicide layer. 3. The method for manufacturing a semiconductor device according to item 2. 4. The first rapid heat treatment step includes: increasing a resistance of the amorphous silicide layer, which performs a polycrystallization process and a high-resistance process on the amorphous silicide layer, to form the high-resistance silicide layer. The method for manufacturing a semiconductor device according to claim 3, further comprising a high-resistance polycrystallization step to be generated. 5. The first rapid heat treatment step includes performing the amorphization step to form the amorphized amorphous silicide layer, and after performing the amorphization step, The semiconductor device according to claim 4, further comprising a step of performing the high-resistance polycrystallization step on the amorphous silicide layer to form a polycrystalline and high-resistance high-resistance silicide layer. Manufacturing method. 6. The amorphizing step is performed at a temperature of 400 ° C. or higher and 55
Performing the rapid heat treatment on the refractory metal film at a temperature of 0 ° C. or less to perform an amorphization process on the silicide layer to generate the amorphous silicide layer. A method for manufacturing a semiconductor device according to claim 3. 7. The amorphizing step is performed at a temperature of 400 ° C. or higher and 55
A step of performing the rapid heat treatment on the refractory metal film at a temperature of 0 ° C. or lower in a nitrogen gas atmosphere to perform an amorphization process on the silicide layer to generate the amorphous silicide layer. The method of manufacturing a semiconductor device according to claim 3, wherein: 8. The amorphizing step is performed at a temperature of 400 ° C. or more and 55
Performing the rapid heat treatment on the refractory metal film at a temperature of 0 ° C. or lower in an argon gas atmosphere to perform an amorphization process on the silicide layer to generate the amorphous silicide layer. The method of manufacturing a semiconductor device according to claim 3, wherein: 9. The method according to claim 9, wherein the amorphizing step is performed at a temperature of 400 ° C. or more and 55 ° C.
Performing the rapid heat treatment on the refractory metal film at a temperature of 0 ° C. or less in a hydrogen gas atmosphere to perform an amorphization process on the silicide layer to generate the amorphous silicide layer. The method of manufacturing a semiconductor device according to claim 3, wherein: 10. The method according to claim 1, wherein the amorphizing step is performed at a temperature of 400 ° C. or higher.
The rapid heat treatment is performed on the titanium metal film as the refractory metal film at a temperature of 50 ° C. or less to perform the amorphization process on the silicide layer to convert the amorphous titanium silicide layer into the amorphous silicide. The method according to claim 3, wherein the method is a step of forming a layer. 11. The high-resistance polycrystallization step is performed at 600 ° C.
6. The step of performing the polycrystallization process and the high-resistance process on the silicide layer at a temperature of not less than 750 ° C. and generating the high-resistance silicide layer. 7. Of manufacturing a semiconductor device. 12. The high-resistance polycrystallization step is performed at 600 ° C.
12. The semiconductor according to claim 11, wherein the polycrystallizing process is performed on the silicide layer at a temperature of not less than 750 ° C. to generate a titanium silicide layer C49 phase as the high-resistance silicide layer. Device manufacturing method. 13. The high-resistance polycrystallization step is performed at 600 ° C.
The polycrystallizing process is performed on the silicide layer at a temperature of not less than 750 ° C. to generate the titanium silicide layer C49 phase as the high-resistance silicide layer, and the high-resistance process is performed on the titanium silicide layer C49 phase. 6. The method of manufacturing a semiconductor device according to claim 4, wherein a step of forming a titanium nitride layer on the titanium silicide layer C49 phase is performed. 14. The high-resistance polycrystallizing step performs the polycrystallization process on the silicide layer at a temperature of 600 ° C. or more and 750 ° C. or less to generate a titanium silicide layer C49 phase as the high-resistance silicide layer. A step of performing the resistance increasing process on the titanium silicide layer C49 phase in a nitrogen gas atmosphere to form a titanium nitride layer on the titanium silicide layer C49 phase. 6. The method for manufacturing a semiconductor device according to item 5. 15. The method according to claim 15, wherein the amorphizing step is performed at a temperature of 400 ° C. or more and 55 ° C.
Performing the rapid heat treatment on the refractory metal film at a temperature of 0 ° C. or less in a nitrogen gas atmosphere to perform an amorphization process on the silicide layer; The polycrystallizing process is performed on the silicide layer at a temperature not less than 750 ° C. to generate a titanium silicide layer C49 phase as the high-resistance silicide layer, and at the same time, the titanium silicide layer C4
6. The semiconductor according to claim 3, wherein the step of increasing the resistance of the nine phases is performed in a nitrogen gas atmosphere to form a titanium nitride layer on the titanium silicide layer C49. Device manufacturing method. 16. The method according to claim 16, wherein the amorphizing step is performed at a temperature of 400 ° C. or more and 55 ° C.
Performing the rapid heat treatment on the refractory metal film at a temperature of 0 ° C. or less in an argon gas atmosphere to perform an amorphization process on the silicide layer; The polycrystallizing process is performed on the silicide layer at a temperature not less than 750 ° C. to generate a titanium silicide layer C49 phase as the high-resistance silicide layer, and at the same time, the titanium silicide layer C4
6. The semiconductor according to claim 3, wherein the step of increasing the resistance of the nine phases is performed in a nitrogen gas atmosphere to form a titanium nitride layer on the titanium silicide layer C <b> 49 phase. 7. Device manufacturing method. 17. The method according to claim 17, wherein the amorphizing step is performed at a temperature of 400 ° C. or more and 55 ° C.
A step of performing the rapid heat treatment on the refractory metal film at a temperature of 0 ° C. or less in a hydrogen gas atmosphere to perform an amorphization treatment of the silicide layer; The polycrystallizing process is performed on the silicide layer at a temperature of not less than 750 ° C. to generate a titanium silicide layer C49 phase as the high-resistance silicide layer, and at the same time, the titanium silicide layer C4
6. The semiconductor according to claim 3, wherein the step of increasing the resistance of the nine phases is performed in a nitrogen gas atmosphere to form a titanium nitride layer on the titanium silicide layer C49 phase. 7. Device manufacturing method. 18. The second rapid heat treatment step includes performing a rapid heat treatment on the titanium silicide layer C49 phase formed in the first rapid heat treatment step to convert the titanium silicide layer C49 phase into a titanium silicide layer C54 phase. The method for manufacturing a semiconductor device according to any one of claims 1 to 17, wherein the lowering of the resistance is performed by causing a phase transition. 19. The method of manufacturing a semiconductor device according to claim 1, wherein said high melting point metal film includes titanium. 20. The method of manufacturing a semiconductor device according to claim 1, wherein said high-melting-point metal film includes titanium nitride. 21. The method for manufacturing a semiconductor device according to claim 1, wherein the high melting point metal film includes a titanium oxide.