JP2000004019A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device resistant to degradation caused by the center of carrier trapping, and method of producing the same. SOLUTION: A gate oxide film 13 comprises an ONO film 13b with large barrier energy to a substrate 1 in the vicinity of drain regions 7b and 10b. This energy barrier prevents the trapping of DAHC in the gate oxide film. A common oxide film 13a is provided, except in the vicinity of the drain regions 7b and 10b. Thereby, the action of a MOS transistor becomes fast, as compared with the use of uniform ONO film of high permittivity as the oxide film 13. As a result of this, carrier implantation into the oxide film is prevented without a lowering the operation speed of the semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a technique for preventing deterioration due to hot carriers.

[0002]

2. Description of the Related Art MOS (Metal Oxide Se)
The transistor includes an N ^- source / drain region 7, an N ⁺ source / drain region 10, a gate oxide film 4, and a gate 5 electrode, as shown in FIG. FIG. 1 shows a manufacturing process for obtaining such a structure.
2 to 15 show the order of steps.

As shown in FIG. 12, first, after a LOCOS oxide film 2 is formed on a semiconductor substrate 1, channel ion implantation 3 is performed. Then, after forming a gate oxide film 4 as shown in FIG. 13, polysilicon is deposited and patterned as shown in FIG. 14 to form a gate electrode 5, N ⁻ ion implantation 6 is performed, and an N ⁻ source is formed. / Drain region 7 is formed. Next, a sidewall film 8 is formed, and N ⁺ ion implantation 9 is performed to form N ⁺ source / drain regions 10, thereby completing the basic structure of the n-type MOSFET (FIG. 1).
5).

[0004] In order to realize a high-density integrated circuit, elements are being miniaturized, while the operating voltage of the elements is TTL.
(Transistor-Transistor Lo
gic) level (5 V or 3.3 V), the electric field in the gate oxide film 4 or the semiconductor substrate 1 is effectively increased with miniaturization of the element.

[0005] Therefore, carriers (electrons or holes) traveling in the substrate under the gate oxide film 4 are accelerated by the electric field and have high energy, and some of them have an energy barrier at the substrate / oxide film interface during traveling of the channel. After getting over, it is captured at the capture center in the gate oxide film 4. This type of carrier is known as CHE (Channel Hot Electron).
is called.

In addition, carriers having high energy reaching the N ⁺ drain 10 collide with impurity atoms to generate new electron-hole pairs, and a part thereof is formed between the semiconductor substrate 1 and the gate oxide film 4. It is trapped at the trapping center in the gate oxide film 4 over the energy barrier at the interface. This type of carrier is a DAHC (Drain AvalancheHo)
t Carrier).

FIG. 16 shows an interface state 12 and an interface fixed charge 1 existing in the gate oxide film 4 in addition to the trapping center 11.
3 and the state of the movable ions 14 are shown. When the semiconductor substrate 1 is formed of silicon and the gate oxide film 4 is formed of a silicon oxide film, the cause of the existence of the interface state 12 is a distorted Si—O bond or an unsaturated bond of silicon.

[0008]

Embedded image

[0009] Mobile ions 14 are sodium ions (Na ^+), potassium ion (K ⁺⁾ alkaline ions such as, a charge Q _m. The charges of these ions affect the electrical characteristics of the MOS transistor.

The electrical characteristics of a MOS transistor are given by Equation 1 in the triode region.

[0011]

(Equation 1)

Here, _ID is the drain current, W is the gate width, L is the gate length, μ is the mobility, C _OX is the gate capacitance, and V
_G is the gate voltage, the V _T gate threshold voltage, the V _D is the drain voltage.

FIG. 17 shows the gate voltage V _G of the drain current _ID .
Is a graph illustrating the dependence (I _D -V _G characteristics) for. Interface state 12, interface fixed charge 13, mobile ion 14
The basic characteristic in the case where no is present is as shown in a curve 15.

In the case of an n-type MOS transistor, when the interface fixed charge 13 (charge amount Q ₀ ) is generated, the gate threshold voltage V _T is affected by the electric flux generated from the charge, and the gate threshold voltage V _T is Q ₀ /
It decreases by C _OX . Therefore, I _D -V _G characteristics 1
7, the gate voltage shifts to the negative side as compared with the basic characteristic represented by the curve 15.

Further, the interface state 12 occurs, which since the amount of electric charge can move freely to capture part of the free carriers is reduced, as indicated by the curve 17 of I _D -V _G characteristics 17, The transconductance is lower than the basic characteristic represented by the curve 15.

In the gate oxide film 4, since the charge has a distribution ρ (x) in the thickness direction, the gate threshold voltage V
_{T is as} follows.

[0017]

(Equation 2)

Here, φ _MS is the difference between the work functions of the semiconductor and the metal, t _OX is the thickness of the gate oxide film 4, Q _D is the charge of the inversion layer, Q _B is the charge of the depletion layer, and C _OX is the charge of the depletion layer. The magnitude of the capacitance formed by the gate oxide film 4, φ _F, is the Fermi potential.
When the trapping center 11 is in the gate oxide film 4, when an electron exceeding the energy barrier at the interface between the semiconductor prayer 1 and the gate oxide film 4 is trapped by the trapping center 11, the trapping center 11 is in a negatively charged state. (The charge amount Q _t ), and the gate threshold voltage V _T fluctuates according to Equation 2.

When the semiconductor substrate 1 is formed of silicon and the gate oxide film 4 is formed of a silicon oxide film, the capture center 11 is formed by the moisture, the capture center formed by the high-temperature heat treatment, It is known that the center is a trapping center or the like generated by carrier injection into the substrate. Hereinafter, silicon and a silicon oxide film will be described.

First, the trapping center caused by water is as follows.
Water in the oxide film (H ₂ O) at high temperature (Si-O-Si)
Reacts with the hydrogen to generate structural defects such as SiOH (silanol) and SiH. Among them, it is reported that SiOH acts as a trapping center 11 for electrons, but SiH does not act as a trapping center for carriers. It has been reported that the trapping center of SiOH is significantly reduced by heat treatment in a non-oxidizing atmosphere at 1000 ° C. or higher.

Further, in the normal manufacturing process of MOS transistors on a silicon wafer, since polysilicon is deposited at a high temperature after the formation of the gate oxide film 4, it is considered that the trapping centers caused by moisture almost disappear.

On the other hand, regarding the trapping center by the high-temperature heat treatment, after the OH groups and oxygen ions in the silicon oxide film escape, the unsaturated bonds of silicon atoms (formula 1) and oxygen vacancies

[0023]

Embedded image

A structural defect is generated. This structural defect acts as a capture center 11 for electrons.

In addition, as the trapping center by the high-temperature heat treatment, there is a trapping center due to a distorted Si—O bond existing near the interface between the silicon substrate and the silicon oxide film. This trap center acts on holes. The density of the trapping center by the high-temperature heat treatment increases when the trapping center is heat-treated in a non-oxidizing atmosphere at a high temperature.

Next, regarding the trapping centers generated by the carrier injection into the oxide film, the increase in the number of unsaturated silicon atoms in the vicinity of the interface due to such injection may be caused by XPS (X-ray Photoemission).
(Spectroscopy).

It is known that in a conventional MOS transistor manufacturing process, heat treatment in a hydrogen atmosphere before forming the gate oxide film 4 greatly reduces the interface states 12 and the interface fixed charges 13. By this processing, MO
The initial operation of the S transistor controllable and becomes the gate electrode 5 exempt from the effects of an interface state 12 and interfacial fixed charge 13, variations in the gate threshold voltage V _T in a wafer becomes smaller. However, when hot carriers are injected into the gate oxide film 4, unsaturated silicon atoms are generated near the interface between the semiconductor substrate 1 and the gate oxide film 4. If left this, the gate threshold voltage V _T varies over time, cause malfunctions.

Further, a conventional flash EEPROM (E
Electrically-Erasable and
In the case of a programmable ROM, as shown in FIG.
9 and a control gate 20 are formed. If a uniform SiO ₂ film is used for the gate oxide film 18, the F-gate between the floating gate 19 and the source region 21 at the time of data erasing is used.
The gate oxide film 14 is degraded by an N (Fowler-Nordheim) tunnel current.

[0029]

The conventional semiconductor device and the method for manufacturing the same are constructed as described above. When the element is miniaturized, the electric field in the semiconductor substrate increases, and the carrier is accelerated by the electric field to increase the energy. And the problem that the energy barrier of the semiconductor substrate / gate oxide film is exceeded, and the carrier trapping center is newly formed by the unsaturated silicon atoms near the semiconductor substrate / oxide film interface, which leads to the deterioration of the operation of the semiconductor device. There was a point.

The present invention has been made in order to solve the above-mentioned problems, and there is no carrier injection into an oxide film even after long-time operation, and unsaturated atoms near the semiconductor substrate / oxide film interface are reduced. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which can avoid deterioration in operation due to generation.

[0031]

According to a first aspect of the present invention, there is provided a semiconductor device, comprising: a semiconductor substrate; a gate insulating film formed on the semiconductor substrate; a gate electrode formed on the gate insulating film; The semiconductor device includes first and second semiconductor layers formed on the main surface of the semiconductor substrate so as to sandwich the gate insulating film, and at least the first semiconductor layer near the gate insulating film contains nitrogen atoms.

According to a second aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a gate insulating film formed on the semiconductor substrate; a gate electrode formed on the gate insulating film; The semiconductor device includes first and second semiconductor layers formed so as to sandwich the gate insulating film, and the gate electrode contains nitrogen atoms.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 shows the present invention.
1 shows a cross-sectional view of a MOS transistor according to a first embodiment.
You. N in the upper surface of the silicon substrate 1^-Source region 7a, N⁺
Source region 10a, N^-Drain region 7b and N⁺Dray
Forming region 10b. N^-Source region 7a and N ^-
The silicon substrate 1 extends over the drain region 7b.
A gate oxide film 13 is formed on the upper surface of the substrate. Game
A gate electrode 5 is formed on the oxide film 13 and
Are formed with side walls 8, respectively.

ONO (Oxide-Nitride-O)
The xide) film has a higher energy barrier for electrons and holes than the SiO ₂ film. Therefore, the gate oxide film 1
When an ONO film is used for the third region, DAH near the drain region
Injection of C into the gate oxide film 13 is less likely to occur than in the case where an SiO ₂ film is used for the gate oxide film 13, and the deterioration of the gate oxide film 13 is suppressed.

On the other hand, the ONO film is different from the SiO ₂ film in that
Large permittivity. Therefore, when the gate oxide film 13 is formed of a uniform ONO film, the operation speed of the MOS transistor is reduced.

For this reason, in the present embodiment, in the MOS transistor, a part 13b of the gate oxide film 13 is formed of an ONO film near the N ⁻ drain region 7b in order to suppress DAHC injection into the gate oxide film 13. are doing. In order to prevent the operating speed of the MOS transistor from deteriorating, another portion 13a of the gate oxide film 13 is
It is formed of _two films.

With such a configuration, further advantages are obtained. Since the ONO film has a larger dielectric constant than the SiO ₂ film, the amount of charge generated near the pinch-off point near the N ⁻ drain region 7b is larger than that when the SiO ₂ film is used as a part 13b of the gate oxide film. Become. For this reason, the drain current and the current driving rate increase.

Embodiment 2 FIG. 2 is a sectional view of a cell transistor of a flash EEPROM according to a second embodiment of the present invention. Source region 2 in the upper surface of semiconductor substrate 1
1, a drain region 22 is formed, and a source region 2 is formed.
The gate oxide film 18 is formed on the upper surface of the semiconductor substrate 1 from 1 to the drain region 22. A floating gate 19 and a control gate 20 are formed inside the gate oxide film 18.

In this embodiment, the gate oxide film 18 is formed of the ONO film 18a in the vicinity of the source region 21, and the gate oxide film 18 is formed of SiO ₂ in other portions.
It is composed of a film 18b. Therefore, the deterioration due to the FN tunnel current between the source region 21 and the floating gate 19 at the time of data erasing is caused by the fact that the gate oxide film 18 is formed of SiO ₂
It is suppressed more than the case where only the film is used.

If the gate oxide film 18 is formed with a uniform O
When the gate oxide film 18 is formed of the NO film, the DAHC injection current between the floating gate 19 and the drain region 22 at the time of data writing becomes difficult to flow, and the write efficiency is deteriorated as compared with the case where the gate oxide film 18 is formed of the SiO ₂ film. Also, O
Since the NO film has a higher dielectric constant than the SiO ₂ film, the capacitance between the floating gate 19 and the semiconductor substrate 1 increases, and the operation speed decreases.

Therefore, the gate oxide film 18 is formed of the ONO film 18a only in the vicinity of the source region 21, and the other portions, for example, in the vicinity of the drain region 22, are the SiO ₂ film
8b.

That is, CHE and DA between the drain region 22 and the floating gate 19 during data writing.
The deterioration due to the FN tunnel current between the source region 21 and the floating gate 19 at the time of data erasure can be suppressed while preventing the injection efficiency of HC and suppressing the decrease in the writing efficiency.

Embodiment 3 3 to 6 show a method for manufacturing a semiconductor device according to the third embodiment of the present invention. First, as shown in FIG. 3, an oxide film 4 is formed on the upper main surface of the semiconductor substrate 1.
a and a polysilicon film 5a are formed. For example, oxide film 4a
Is formed with a thickness of 7 nm, and the polysilicon film 5a is formed with a thickness of 350 nm. Next, as shown in FIG.
The oxide film 4a and the polysilicon film 5a are patterned to form a gate oxide film 4 and a gate electrode 5 respectively.

Then, as shown in FIG. 5, the resist 11 covers the semiconductor substrate 1 from the portion where the source region is to be formed in the future to the upper surface of the gate electrode 5. The gate oxide film 4 (drain end) and the gate electrode 5 near the future formation of the drain region in the semiconductor substrate 1 are not covered with the resist 11. Thereafter, for example, nitrogen ions are applied at an energy of 10 keV and a dose of 2.0 × 10 ¹³ / c.
The injection is performed obliquely at m ² and an incident angle of 45 °, and nitrogen ions are introduced into the drain end of the gate oxide film 4. At this time, nitrogen ions are also introduced into the gate electrode 5 and the portion where the drain region is to be formed in the semiconductor substrate 1 in the future, and the following effects are brought about. First, the effect of introducing nitrogen into the gate electrode 5 is as follows.
Diffusion of impurities into the transistor can be prevented, and fluctuations in the threshold voltage of the transistor can be suppressed. That is, the polysilicon film 5a contains impurities such as boron and phosphorus, and when the gate oxide film 4 becomes thin, these impurities diffuse through the gate oxide film 4 and reach the semiconductor substrate 1 during a heat treatment described later. And the threshold voltage is varied. However, when nitrogen is introduced into the gate electrode 5, fluctuation of the threshold voltage is suppressed because nitrogen has a function of suppressing diffusion of impurities. Next, by introducing nitrogen into a portion of the semiconductor substrate 1 where a drain region is to be formed in the future, a decrease in reliability of the transistor due to hot carriers can be prevented. Since nitrogen is a donor impurity like phosphorus and arsenic, by introducing nitrogen into the drain region formed by the donor, the impurity distribution in the direction parallel to the upper surface of the semiconductor substrate 1 is moderated, and the electric field in the drain region is reduced. This is because it eases. Furthermore, since nitrogen getsters minute defects near the junction of the drain region, junction leakage current can be reduced, and as a result, power consumption of the transistor can be reduced.

Thereafter, the resist 11 is removed, and a heat treatment is performed so that the ONO film 1 is formed on the drain end of the gate oxide film 4.
3b is formed. The gate oxide film other than the drain end is left as it is, and becomes a part 13a of the gate oxide film (FIG. 6).

Through these steps, a gate oxide film 13 having a dielectric constant that is not uniform in the lateral direction is formed. Similar effects can be obtained by selectively implanting other ions, for example, phosphorus or arsenic ions into the gate oxide film 4 by ion implantation.

Thereafter, N is obtained by a known technique.^-Source
Region 7a, N⁺Source region 10a, N ^-Drain region 7b
And N⁺By forming the drain region 10b and the like,
The MOS transistor according to the first embodiment shown in FIG.
Can be

Alternatively, by forming the source region 21, the drain region 22, the floating gate 19, the control gate 20, and the like, the cell transistor of the flash EEPROM according to the second embodiment shown in FIG. 2 can be obtained.

Embodiment 4 7 to 9 show a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention. In the third embodiment, since nitrogen ions are introduced into gate oxide film 4 by ion implantation, there is a problem that a large number of defects serving as carrier capture centers are introduced into gate oxide film 4. In this embodiment, to avoid this,
Nitriding oxidation by gas is performed.

First, the gate electrode 5 is made of polysilicon.
(FIG. 7), a nitrogen gas and an oxygen gas are flowed in a furnace when the sidewalls are formed. As a result, both ends of the gate oxide film 4 are nitrided and oxidized, an ONO film 13b is formed at both ends of the gate oxide film 13, and the other portions are left as oxide films 13a. Here, “nitriding oxidation” means that nitriding and oxidation are performed simultaneously or alternately. For example, in forming the gate oxide film 13, gases are introduced in the order of oxygen gas, nitrogen gas, and oxygen gas, but these may or may not include nitrogen gas, oxygen gas, and nitrogen gas, respectively.

Thereafter, for example, TEOS (Tetra
An oxide film 8a is deposited by flowing Ethoxy Silane (FIG. 8).

Further, as shown in FIG. 9, when anisotropic etching is performed by RIE, a gate oxide film 13 having ONO films 13b on both ends and a sidewall 8 having ONO films 13b on the bottom surface are formed.

Thereafter, by forming the N ⁻ source / drain region 7, the N ⁺ source / drain region 10 and the like by a known technique, a MOS transistor as shown in FIG. 10 can be obtained. As described in Embodiment 1,
The MOS transistor shown in FIG. 1 has an advantage that it is not necessary to use the source and the drain separately.

Embodiment 5 FIG. FIG. 11 is a sectional view showing a semiconductor manufacturing method according to the fifth embodiment of the present invention. When MOS transistors are formed on one main surface of the semiconductor wafer 100, the thickness of the gate oxide film in the wafer 1 may vary. This may cause variation in electrical characteristics between MOS transistors on the same wafer.

Therefore, in order to suppress this kind of variation in electrical characteristics, the gate oxide film 30 formed on the wafer 1 is formed.
Then, the ion implantation 40 of ions such as nitrogen is selectively performed so that the dielectric constant of the gate oxide film has a distribution, thereby suppressing variations in electrical characteristics due to variations in film thickness. Specifically, the ion implantation 40 is performed in a portion where the gate oxide film 30 is thick.

[0056]

According to the first aspect of the present invention, there is provided a semiconductor device comprising:
Nitrogen atoms are bonded to unsaturated silicon atoms near the interface between the semiconductor layer and the gate insulating film, thereby reducing the generation of interface states. In the semiconductor device according to the second aspect of the present invention, since the gate electrode contains nitrogen atoms, diffusion of impurities contained in the gate electrode into the gate oxide film by the nitrogen atoms is suppressed.

According to the semiconductor device of the present invention, the injection of DAHC into the gate oxide film near the first semiconductor layer is suppressed. Therefore, deterioration of performance such as fluctuation of gate threshold voltage and reduction of transconductance is suppressed.

Further, since nitrogen atoms are bonded to unsaturated silicon atoms near the interface between the first semiconductor layer and the gate insulating film to reduce the generation of interface states, the fluctuation of the threshold voltage can be suppressed.

Further, when the gate electrode contains a nitrogen atom, fluctuations in the threshold voltage of the semiconductor device can be suppressed. Furthermore, when a portion adjacent to the first semiconductor layer among the portions sandwiched by the first and second semiconductor layers contains nitrogen atoms, it is possible to prevent a decrease in the reliability of the semiconductor device due to hot carriers. it can.

[Brief description of the drawings]

FIG. 1 is a sectional view of a MOS transistor according to a first embodiment of the present invention;

FIG. 2 is a diagram showing a flash E according to a second embodiment of the present invention;
FIG. 3 is a cross-sectional view of a cell transistor of an EPROM memory.

FIG. 3 is a cross-sectional view showing a third embodiment of the present invention in the order of steps.

FIG. 4 is a sectional view showing a third embodiment of the present invention in the order of steps.

FIG. 5 is a sectional view showing Embodiment 3 of the present invention in the order of steps.

FIG. 6 is a cross-sectional view showing a third embodiment of the present invention in the order of steps.

FIG. 7 is a sectional view showing a fourth embodiment of the present invention in the order of steps.

FIG. 8 is a sectional view showing a fourth embodiment of the present invention in the order of steps.

FIG. 9 is a cross-sectional view showing a fourth embodiment of the present invention in the order of steps.

FIG. 10 is a sectional view showing a fourth embodiment of the present invention in the order of steps.

FIG. 11 is a sectional view showing Embodiment 5 of the present invention in the order of steps.

FIG. 12 is a cross-sectional view showing a manufacturing step of a conventional MOS transistor in the order of steps.

FIG. 13 is a cross-sectional view showing a conventional MOS transistor manufacturing process in the order of processes.

FIG. 14 is a cross-sectional view showing a conventional MOS transistor manufacturing process in the order of processes.

FIG. 15 is a cross-sectional view showing a manufacturing step of a conventional MOS transistor in the order of steps.

FIG. 16 is a schematic diagram showing a trap center, an interface state, an interface fixed charge, and a mobile ion in a gate oxide film.

FIG. 17 is a graph showing electric characteristics of a MOS transistor.

FIG. 18 is a cross-sectional view showing a structure of a conventional flash EEPROM memory cell transistor.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 4 gate oxide film 5 polysilicon gate 7 N ^- source / drain region 7a N ^- source region 7b N ^- drain region 10 N ⁺ source / drain region 10a N ⁺ source region 10b N ⁺ drain region 18 gate oxide film 19 Floating gate 21 Source region 22 Drain region

Claims (2)

[Claims] A semiconductor substrate; a gate insulating film formed on the semiconductor substrate; a gate electrode formed on the gate insulating film; and a gate insulating film interposed between main surfaces of the semiconductor substrate. A semiconductor device comprising: first and second semiconductor layers formed, wherein at least the first semiconductor layer near the gate insulating film contains nitrogen atoms. 2. A semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and a gate insulating film sandwiched on a main surface of the semiconductor substrate. A semiconductor device, comprising: first and second semiconductor layers formed, wherein the gate electrode contains nitrogen atoms.