JPH02162738A - Manufacture of mos fet - Google Patents
Manufacture of mos fetInfo
- Publication number
- JPH02162738A JPH02162738A JP31795188A JP31795188A JPH02162738A JP H02162738 A JPH02162738 A JP H02162738A JP 31795188 A JP31795188 A JP 31795188A JP 31795188 A JP31795188 A JP 31795188A JP H02162738 A JPH02162738 A JP H02162738A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate electrode
- gate
- ion
- nitride film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000000034 method Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 11
- 239000010703 silicon Substances 0.000 claims abstract description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 17
- 229920005591 polysilicon Polymers 0.000 abstract description 17
- 150000004767 nitrides Chemical class 0.000 abstract description 15
- 238000005468 ion implantation Methods 0.000 abstract description 13
- 239000012535 impurity Substances 0.000 abstract description 8
- 230000003647 oxidation Effects 0.000 abstract description 8
- 238000007254 oxidation reaction Methods 0.000 abstract description 8
- 230000000873 masking effect Effects 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 47
- 238000009792 diffusion process Methods 0.000 description 10
- 230000003071 parasitic effect Effects 0.000 description 10
- 230000000694 effects Effects 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は半導体装置の製造方法に関し、特に、ＭＯＳ
ＦＥＴのゲートに対する寄生容量の低減を目的とした製
造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device.
The present invention relates to a manufacturing method aimed at reducing parasitic capacitance to the gate of an FET.
［従来の技術］
従来のＭＯＳ ＦＥＴの製造方法は、シリコン基板を薄
く酸化し、さらにシリコン窒化膜をデポジションしホト
エツチング技術を使用して前記窒化膜をパターニングし
た後、窒化膜を、耐酸化マスクとして用いて厚いフィー
ルド酸化膜を形成するロコス工程と、前記ロコス工程の
終了した基板にポリシリコン等を積層させ、同じくホト
エツチング技術を使用して、ゲート電極を形成する工程
と、前記ゲート電極を１つのマスクとして、イオン注入
技術によりシリコン基板に不純物を導入し、ソース・ト
レインとなる拡散領域をセルフアライメントで形成する
工程と、拡散領域およびゲート電極と金属配線を絶縁す
る薄膜層を積層し、これにバイアホールを形成し、更に
、金属配線を形成する工程からなるのが、−船釣である
。[Prior Art] A conventional method for manufacturing a MOS FET involves thinly oxidizing a silicon substrate, depositing a silicon nitride film, patterning the nitride film using photo-etching technology, and then applying an oxidation-resistant mask to the nitride film. a LOCOS process in which a thick field oxide film is formed using the LOCOS process; a process in which polysilicon, etc. is laminated on the substrate after the LOCOS process, and a gate electrode is formed using the same photo-etching technique; As a mask, impurities are introduced into the silicon substrate using ion implantation technology, a diffusion region that will become a source train is formed by self-alignment, and a thin film layer is laminated to insulate the diffusion region, gate electrode, and metal wiring. The process of forming a via hole and then forming a metal wiring is the process of - boat fishing.
第２図はこの従来法を用いて形成されたＭＯＳＦＥＴの
断面図であり、シリコン基板４の主面には、ロコス法に
より形成された厚いフィールド酸化膜５とゲート酸化膜
６が形成され、ゲート酸化膜６上にポリシリコンゲート
ｌが形成されている。また、シリコン基板４中には、ソ
ース領域２、ドレイン領域３が形成されている。FIG. 2 is a cross-sectional view of a MOSFET formed using this conventional method. On the main surface of a silicon substrate 4, a thick field oxide film 5 and a gate oxide film 6 formed by the LOCOS method are formed. A polysilicon gate l is formed on the oxide film 6. Further, in the silicon substrate 4, a source region 2 and a drain region 3 are formed.
［発明が解決しようとする課題］
発明が上述した従来の技術により形成されたＭＯＳ Ｆ
ＥＴのでは第２図に示されるように、ゲート電極には、
本来の動作に必要なゲート容ｆｆ１ｃ１と、動作に不必
要な寄生容ｆｆ１ｃ２〜Ｃ５が構造的に存在する。ゲー
トとソース・ドレインの直接型なりによる寄生容量Ｃ２
，Ｃ３は、ソース・トレイン拡散層のシャロー化や、Ｌ
ＤＤ構造の採用により低減されている。一方、シリコン
基板への不純物導入を行う場合、ゲート電極膜をマスク
として使用するセルフアライメント方式のイオン注入時
にゲート電極は、加速されたイオンを基板までつきぬけ
させないマスク効果を維持する必要性があり、このため
に、ゲート電極は十分な厚みが必要であり、フリンジ効
果による寄生容量Ｃ４、Ｃ５は、近年のＭＯＳ ＦＥＴ
の微細化にもかかわらず、依然大きな容量となっている
。ゲートの寄生容量が大きいことは、ゲートの電圧が変
化した場合、ゲート容量のチャージまたはディスチャー
ジに用する時間の増加を意味し、論理ゲートを構成した
場合の遅延時間を招くという問題がある。[Problem to be solved by the invention] The invention is a MOS F formed by the above-mentioned conventional technology.
In the ET, as shown in Figure 2, the gate electrode is
Structurally, there are a gate capacitance ff1c1 necessary for the original operation and parasitic capacitances ff1c2 to C5 unnecessary for the operation. Parasitic capacitance C2 due to direct formation of gate and source/drain
, C3 is for making the source train diffusion layer shallower and for L
This is reduced by adopting the DD structure. On the other hand, when introducing impurities into a silicon substrate, during ion implantation using a self-alignment method that uses the gate electrode film as a mask, the gate electrode needs to maintain a masking effect that prevents accelerated ions from penetrating into the substrate. For this reason, the gate electrode needs to be sufficiently thick, and the parasitic capacitances C4 and C5 due to the fringe effect are
Despite miniaturization, the capacity is still large. A large parasitic capacitance of the gate means that when the gate voltage changes, the time required to charge or discharge the gate capacitance increases, resulting in a delay time when a logic gate is configured.
［課題を解決するための手段］
本発明のＭＯＳ ＦＥＴの製造方法は、半導体装置の製
造方法において、
ロコス工程を終了したシリコン基板に薄いゲート電極膜
をデポジションする工程と、
ゲート電極膜上に、シリコン窒化膜をデポジションする
工程と、
ホトエツチング技術を使用して、前記シリコン窒化膜と
ゲート電極膜の二層膜を連続してパターニングする工程
と、
該パターニングされたゲート電極およびシリコン窒化膜
をマスクとして用いてソース・ドレイン形成用不純物を
基板内に導入する工程と、ゲート電極上の前記シリコン
窒化膜を除去する工程とを有している。[Means for Solving the Problems] A method for manufacturing a MOS FET of the present invention is a method for manufacturing a semiconductor device, and includes the steps of depositing a thin gate electrode film on a silicon substrate that has undergone a LOCOS process, and depositing a thin gate electrode film on the gate electrode film. , a step of depositing a silicon nitride film, a step of successively patterning the two-layer film of the silicon nitride film and the gate electrode film using a photoetching technique, and a step of depositing the patterned gate electrode and the silicon nitride film. The method includes a step of introducing impurities for forming a source/drain into the substrate using a mask, and a step of removing the silicon nitride film on the gate electrode.
［作用］
ゲート電極となるポリシリコンの厚みを従来より薄くす
る一方、シリコン窒化膜を重ねて二重構造とすることに
より、イオン注入マスクとして十分な厚みを確保しつつ
ゲート電極の薄膜化を図ることができる。[Operation] By making the polysilicon that becomes the gate electrode thinner than before, and by stacking silicon nitride films to create a double structure, the gate electrode can be made thinner while ensuring sufficient thickness as an ion implantation mask. be able to.
［実施例］
次に、本発明の実施例について図面を参照して説明する
。[Example] Next, an example of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を工程順に示した断面図であ
る。FIG. 1 is a sectional view showing an embodiment of the present invention in the order of steps.
第１図（ａ）は、シリコン基板４に窒化膜（不図示）を
耐酸化マスクとしてパターニングし、酸化してフィール
ド酸化ｗＡ５を形成した後に窒化膜を除去した状態、つ
まりロコス工程の完了したものである。FIG. 1(a) shows a state in which a nitride film (not shown) is patterned on a silicon substrate 4 as an oxidation-resistant mask, oxidized to form a field oxide wA5, and then the nitride film is removed, that is, the LOCOS process is completed. It is.
次に、ゲート電極と基板を絶縁するための酸化を行い、
ゲート酸化膜６を形成したものが、第１図（ｂ）である
。Next, oxidation is performed to insulate the gate electrode and the substrate.
FIG. 1(b) shows the structure with the gate oxide film 6 formed thereon.
次に、ゲート電極膜としてはポリシリコンＭｌを積層す
る（第１図（Ｃ） ） 、この時の膜圧は、１０００人
前後である。従来の膜圧はソース・ドレインのイオン注
入時のマスク性能を維持するために４０００人〜８００
０人程度がよく用いられている。−例として、ボロンを
加速エネルギー５０Ｋ ｅ ｖでイオン注入する場合、
ポリシリコンが完全なマスク効果を保持するためには、
約３２００人の膜圧が最低必要となる。しかし、本実施
例の場合は、ポリシリコン膜１の厚さを従来より薄く形
成する。Next, polysilicon Ml is laminated as a gate electrode film (FIG. 1(C)), and the film thickness at this time is about 1,000. Conventional film thickness is 4000 to 800 to maintain mask performance during source/drain ion implantation.
Around 0 people is often used. - For example, when boron is ion-implanted at an acceleration energy of 50 K e v,
In order for polysilicon to retain its full masking effect,
A minimum membrane pressure of approximately 3,200 people is required. However, in the case of this embodiment, the thickness of polysilicon film 1 is formed thinner than in the conventional case.
次に、ゲート電極膜上に窒化膜７をデポジションし、イ
オン注入時のマスク効果の不足分を補う（第１図（ｄ）
）、ボロンな５０Ｋ ｅ ｙでイオン打込みする場合、
窒化膜圧は約２０００人である。一方、ゲート電極膜を
薄くしたことによる抵抗の増加は、ポリシリコンの不純
物拡散濃度を増加させ非抵抗を下げるか、あるいは白金
（ｐｔ）などを用いて電極膜をポリサイド化することに
より回避できる。 次に、ホトエツチング技術を用いて
、窒化膜上にホトレジストのゲート電極パターンな整形
した後、異方性のりアクチブイオンエツチングにより窒
化膜７とポリシリコン膜ｌを連続してエツチングする。Next, a nitride film 7 is deposited on the gate electrode film to compensate for the lack of masking effect during ion implantation (Fig. 1(d)).
), when performing ion implantation with boron 50K e y,
The nitride film pressure is about 2000. On the other hand, an increase in resistance due to thinning of the gate electrode film can be avoided by increasing the impurity diffusion concentration of polysilicon to lower the non-resistance, or by polyciding the electrode film using platinum (PT) or the like. Next, a photoresist gate electrode pattern is formed on the nitride film using a photoetching technique, and then the nitride film 7 and the polysilicon film 1 are successively etched using anisotropic active ion etching.
エツチングは、ＣＦ４ガス雰囲気中ならば窒化膜とポリ
シリコン膜のエツチング速度が同等となる条件を設定す
ることは容易である。For etching, it is easy to set conditions such that the etching rate of the nitride film and the polysilicon film are the same in a CF4 gas atmosphere.
ゲート電極のエツチング終了後、セルフアライメントに
より、ライトトレインとなる不純物（Ｎ型チャネルのＭ
ＯＳであれば、砒素（Ａ ｓ ）イオン）をイオン注入
する（第１図（ｅ） ） 。After etching the gate electrode, self-alignment allows the impurity (M of the N-type channel) to become a light train.
If it is an OS, arsenic (A s ) ions) are implanted (FIG. 1(e)).
次に、イオン注入後のアニールとＬＤＤ構造に必要なゲ
ートのサイドウオール８を形成するための酸化を行う、
この時、イオン注入のマスクとしてのゲート上の窒化膜
は、ゲート表面の耐酸化マスクとして作用する。よって
ゲート電極は、側面のみ酸化される。また、酸化を８５
０℃程度の水蒸気雰囲気中で行えば、不純物濃度の高い
ポリシリコンに比べて、シリコン基板の酸化レートは極
めて小さい、よって、ゲートの側面のみが酸化された状
態となる。この後、深いジャンクションの低抵抗領域２
ａ、３ｂを形成するためのイオン注入を行う、Ｎチャネ
ルのＭＯＳの場合、リン（Ｐ）イオンを注入する（第１
図（ｆ） ） 。Next, annealing after ion implantation and oxidation to form gate sidewalls 8 necessary for the LDD structure are performed.
At this time, the nitride film on the gate, which serves as a mask for ion implantation, acts as an oxidation-resistant mask for the gate surface. Therefore, only the side surfaces of the gate electrode are oxidized. Also, oxidation is 85%
If performed in a water vapor atmosphere at about 0° C., the oxidation rate of the silicon substrate is extremely low compared to polysilicon with a high impurity concentration, so only the side surfaces of the gate are oxidized. After this, deep junction low resistance region 2
In the case of an N-channel MOS, in which ion implantation is performed to form elements a and 3b, phosphorus (P) ions are implanted (first
Figure (f)).
最後にゲート電極上の窒化膜７は、不必要となるから熱
燐酸を使用して除去する（第１図（ｇ） ） 。Finally, since the nitride film 7 on the gate electrode is no longer needed, it is removed using hot phosphoric acid (FIG. 1(g)).
以上のようにして形成されたＭＯＳ ＦＥＴに電極配線
を施して半導体装置を構成する。A semiconductor device is constructed by applying electrode wiring to the MOS FET formed as described above.
［発明の効果］
以上説明したように本発明は、ゲート電極膜を薄膜化し
、ゲート電極上に窒化膜を積石して二重構造としてゲー
ト電極パターンを形成し、ソース・ドレインの不純物イ
オン注入を行う製造方法とすることで、ゲート電極膜厚
を任意に薄膜化でき、フリンジ効果によるゲート電極の
寄生容量を大幅に低減できる効果がある。これにより、
ＭＯＳＦＥＴにより構成された論理ゲートの遅延を低減
できる効果がある。[Effects of the Invention] As explained above, the present invention reduces the thickness of the gate electrode film, stacks a nitride film on the gate electrode to form a double structure gate electrode pattern, and implants impurity ions into the source and drain. By using a manufacturing method that performs the following, the gate electrode film thickness can be arbitrarily reduced, and the parasitic capacitance of the gate electrode due to the fringe effect can be significantly reduced. This results in
This has the effect of reducing the delay of a logic gate configured with MOSFETs.
また、ゲート電極膜をポリシリコン、イオン注入に対す
るマスク性能の補足膜として窒化膜を使用すれば、ＭＯ
Ｓ ＦＥＴのＬＤＤ構造を容易に形成できる効果がある
。In addition, if polysilicon is used as the gate electrode film and a nitride film is used as a supplementary film for masking performance against ion implantation, MO
This has the effect of easily forming the LDD structure of SFET.
第１図（ａ） 〜（ｇ）は本発明のＭＯＳ ＦＥＴの製
造方法の一実施例を工程順に示した断面図、第２図は従
来例により形成されたＭＯＳ ＦＥＴの断面図である。
１・・・ゲート電極（ポリシリコンまたはポリサイドゲ
ート）、
２・・・ソース（またはドレイン拡散層）、３・・・ト
レイン（またはソース拡散層）、４・・・シリコン基板
、
５・・・フィールド酸化膜、
６・・・ゲート電極膜、
７・・・窒化膜、
８・・・ＬＤＤ用ゲート酸化膜、
ＣＩ・・・ゲート容量、
Ｃ２・・・ゲートと拡散のオーバーラツプによる寄生容
量、
Ｃ３・・・ゲートと拡散のオーバーラツプによる寄生容
量、
Ｃ４・・・ゲート側面と拡散のフリンジ効果による寄生
容量、
Ｃ５・・・ゲート側面と拡散のフリンジ効果による寄生
容量。FIGS. 1(a) to 1(g) are cross-sectional views showing an example of the method for manufacturing a MOS FET of the present invention in the order of steps, and FIG. 2 is a cross-sectional view of a MOS FET formed by a conventional example. DESCRIPTION OF SYMBOLS 1... Gate electrode (polysilicon or polycide gate), 2... Source (or drain diffusion layer), 3... Train (or source diffusion layer), 4... Silicon substrate, 5... Field oxide film, 6... Gate electrode film, 7... Nitride film, 8... Gate oxide film for LDD, CI... Gate capacitance, C2... Parasitic capacitance due to overlap between gate and diffusion, C3 ... Parasitic capacitance due to overlap between gate and diffusion, C4... Parasitic capacitance due to fringe effect between gate side surface and diffusion, C5... Parasitic capacitance due to fringe effect between gate side surface and diffusion.
Claims (1)
をデポジションする工程と、 ゲート電極膜上に、シリコン窒化膜をデポジションする
工程と、 ホトエッチング技術を使用して、前記シリコン窒化膜と
ゲート電極膜の二層膜を連続してパターニングする工程
と、 該パターニングされたゲート電極およびシリコン窒化膜
をマスクとして用いてソース・ドレイン形成用不純物を
基板内に導入する工程と、 ゲート電極上のシリコン窒化膜を除去する工程とを有す
るＭＯＳＦＥＴの製造方法。[Claims] A method for manufacturing a semiconductor device, comprising: a step of depositing a thin gate electrode film on a silicon substrate that has undergone a LOCOS process; a step of depositing a silicon nitride film on the gate electrode film; and a photoetching step. a step of sequentially patterning the two-layer film of the silicon nitride film and the gate electrode film using a technique; 1. A method for manufacturing a MOSFET, comprising: a step of introducing a silicon nitride film on a gate electrode; and a step of removing a silicon nitride film on a gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31795188A JPH02162738A (en) | 1988-12-15 | 1988-12-15 | Manufacture of mos fet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31795188A JPH02162738A (en) | 1988-12-15 | 1988-12-15 | Manufacture of mos fet |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02162738A true JPH02162738A (en) | 1990-06-22 |
Family
ID=18093835
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31795188A Pending JPH02162738A (en) | 1988-12-15 | 1988-12-15 | Manufacture of mos fet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02162738A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5476802A (en) * | 1991-08-26 | 1995-12-19 | Semiconductor Energy Laboratory Co., Ltd. | Method for forming an insulated gate field effect transistor |
| US5707721A (en) * | 1995-09-29 | 1998-01-13 | Samsung Electronics Co., Ltd. | Methods of forming field effect transistors having oxidation-controlled gate lengths |
| US6049092A (en) * | 1993-09-20 | 2000-04-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US6259120B1 (en) | 1993-10-01 | 2001-07-10 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for fabricating the same |
| US6489632B1 (en) | 1993-01-18 | 2002-12-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a gate oxide film |
| US6777763B1 (en) | 1993-10-01 | 2004-08-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for fabricating the same |
| EP1665334A2 (en) * | 2003-08-26 | 2006-06-07 | International Business Machines Corporation | Method to produce transistor having reduced gate height |
| WO2009058242A1 (en) * | 2007-10-31 | 2009-05-07 | Advanced Micro Devices, Inc. | Method for adjusting the height of a gate electrode in a semiconductor device |
| WO2009108366A2 (en) * | 2008-02-29 | 2009-09-03 | Advanced Micro Devices, Inc. | A semiconductor device comprising a metal gate stack of reduced height and method of forming the same |
| JP2010519724A (en) * | 2007-01-04 | 2010-06-03 | フリースケール セミコンダクター インコーポレイテッド | Formation of semiconductor device having metal electrode and structure of semiconductor device |
-
1988
- 1988-12-15 JP JP31795188A patent/JPH02162738A/en active Pending
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5476802A (en) * | 1991-08-26 | 1995-12-19 | Semiconductor Energy Laboratory Co., Ltd. | Method for forming an insulated gate field effect transistor |
| US6995432B2 (en) | 1993-01-18 | 2006-02-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a gate oxide film with some NTFTS with LDD regions and no PTFTS with LDD regions |
| US7408233B2 (en) | 1993-01-18 | 2008-08-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having N-channel thin film transistor with LDD regions and P-channel thin film transistor with LDD region |
| US6489632B1 (en) | 1993-01-18 | 2002-12-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a gate oxide film |
| US6049092A (en) * | 1993-09-20 | 2000-04-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US7166503B2 (en) | 1993-10-01 | 2007-01-23 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a TFT with laser irradiation |
| US6777763B1 (en) | 1993-10-01 | 2004-08-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for fabricating the same |
| US6259120B1 (en) | 1993-10-01 | 2001-07-10 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for fabricating the same |
| US5707721A (en) * | 1995-09-29 | 1998-01-13 | Samsung Electronics Co., Ltd. | Methods of forming field effect transistors having oxidation-controlled gate lengths |
| EP1665334A2 (en) * | 2003-08-26 | 2006-06-07 | International Business Machines Corporation | Method to produce transistor having reduced gate height |
| EP1665334A4 (en) * | 2003-08-26 | 2011-02-23 | Ibm | Method to produce transistor having reduced gate height |
| JP2010519724A (en) * | 2007-01-04 | 2010-06-03 | フリースケール セミコンダクター インコーポレイテッド | Formation of semiconductor device having metal electrode and structure of semiconductor device |
| WO2009058242A1 (en) * | 2007-10-31 | 2009-05-07 | Advanced Micro Devices, Inc. | Method for adjusting the height of a gate electrode in a semiconductor device |
| GB2466759A (en) * | 2007-10-31 | 2010-07-07 | Globalfoundries Inc | Method for adjusting the height of a gate electrode in a semiconductor device |
| US8361844B2 (en) | 2007-10-31 | 2013-01-29 | Globalfoundries Inc. | Method for adjusting the height of a gate electrode in a semiconductor device |
| WO2009108366A2 (en) * | 2008-02-29 | 2009-09-03 | Advanced Micro Devices, Inc. | A semiconductor device comprising a metal gate stack of reduced height and method of forming the same |
| WO2009108366A3 (en) * | 2008-02-29 | 2009-10-29 | Advanced Micro Devices, Inc. | A semiconductor device comprising a metal gate stack of reduced height and method of forming the same |
| US8293610B2 (en) | 2008-02-29 | 2012-10-23 | Globalfoundries Inc. | Semiconductor device comprising a metal gate stack of reduced height and method of forming the same |
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