JPH05267334A - Manufacture of integrated circuit device - Google Patents

Abstract

PURPOSE:To eliminate overlap of source/drain layers of high concentration with a gate electrode in a MOS transistor having an inverted T-shaped gate electrode. CONSTITUTION:The method for manufacturing an integrated circuit device comprises the steps of forming a first sidewall 9a, forming an N-type first polycrystalline silicon film 6a to become a lower layer gate electrode by RIE, then removing the sidewall 9a, forming a second sidewall 11 thicker than the sidewall 9a, and ion implanting to form source/drain layers 10a of high N-type concentration.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an integrated circuit device, and more particularly to a method of manufacturing a MOS transistor having a gate overlap type LDD structure.

[0002]

2. Description of the Related Art Proceedings of International Electron Device Meeting in December 1987 38-
Page 41 (Proc. Intl. Electron.
Devices Meeting, PP. 38-41
(Dec. 1987)), a conventional method for manufacturing an MO transistor having a gate-overlap type LDD structure (referred to as "GOLD" type) will be described with reference to FIG.

A field oxide film 2 and a gate oxide film 4 for element isolation are selectively formed on the main surface of a P type silicon substrate 1, and a phosphorus-doped first polycrystalline silicon film 5 is formed on the entire surface. Then, the native oxide film 6 is formed on the surface. Next, a second polycrystalline silicon film doped with phosphorus is formed on the entire surface. Then, the second polycrystalline silicon film is processed into a desired shape by photolithography using the natural oxide film 6 as an etching stopper, and the polycrystalline silicon film 7 is formed.
To form. Next, phosphorus is ion-implanted to form the N type low concentration layer 8 [FIG. 2 (a)].

A silicon dioxide film is deposited on the entire surface by a CVD method and RIE is performed to form a side wall 9 of the silicon dioxide film on the side surface of the polycrystalline silicon film 7. In this step, the natural oxide film 6 becomes the natural oxide film 6a [FIG. 2 (b)].

The first polycrystalline silicon film 5 is etched by using the polycrystalline silicon film 7 and the side walls 9 as a mask to form a polycrystalline silicon film 5a [FIG. 2].
(C)]. The "GOLD" type gate electrode is composed of the polycrystalline silicon films 7 and 5a (and the natural oxide film 6a and the sidewall 9).

Arsenic ion implantation and annealing are performed, and N
The high concentration layer 10 of the mold is formed [FIG. 2 (d)]. afterwards,
The conventional "GOLD" type integrated circuit device is formed by forming an interlayer insulating film, a contact hole, and a wiring metal by a known method.

[0007]

DISCLOSURE OF THE INVENTION The conventional GOL described above
In the method of manufacturing a D-type MOS transistor, high-concentration layers of source / drain are formed by self-aligned ion implantation with a gate electrode. Therefore, the subsequent heat treatment diffuses the impurities forming the high-concentration layer, and as a result, the gate electrode and the high-concentration layer overlap.

Due to this overlap, (1) the parasitic capacitance between the gate and the drain and between the gate and the source is increased, and the operation speed of the device is reduced. (2) Band-to-band tunneling occurs at the overlap portion. There is a problem.

[0009]

In the method of manufacturing an integrated circuit device according to the present invention, a sidewall and a source / drain for determining a gate electrode length of a MOS transistor having a gate overlap type LDD structure are used. Sidewalls for forming the concentration layer are separately formed and used separately.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG.

On the main surface of the P type silicon substrate 1, element isolation regions 600 to 1 are formed by selective oxidation (LOCOS).
A field oxide film 2 having a film thickness of 000 nm is formed. Next, in an atmosphere of dry oxygen at 700 to 900 ° C. for 10 to 25
A gate oxide film 4 having a film thickness of nm is formed. A phosphorus-doped N-type first polycrystalline silicon film 5 of 50 to 100 nm, which is a constituent material of a lower gate electrode of the GOLD type gate electrode, is formed. 1 to the surface of the polycrystalline silicon film 5
A natural oxide film 6 having a film thickness of 10 nm is formed. Phosphorus-doped N-type second polycrystalline silicon having a film thickness of 100 to 200 nm, which is a constituent material of the upper gate electrode of the GOLD type gate electrode, is deposited by the LPCVD method.

The second polycrystalline silicon film is dry-etched by photolithography to remove the polycrystalline silicon film 7.
To form. When this dry etching is performed with a gas containing fluorine or chlorine, a sufficient selection ratio between the second polycrystalline silicon film and the natural oxide film 6 is obtained, and the natural oxide film 6 serves as an etching stopper. 30 to 10 phosphorus
Ion implantation is performed at 0 keV and 5 × 10 ^{13 to} 3 × 10 ¹³ cm ⁻² to form the N-type low concentration layer 8 (FIG. 1A).

A silicon nitride film having a thickness of 100 to 200 nm is deposited by the LPCVD method. RIE is performed on the silicon nitride film of No. 2 by a gas system containing fluorine to form the first sidewall 9a on the side surface of the polycrystalline silicon film 7. Polycrystalline silicon film 7 and first sidewall 9
Using a as a mask, the natural oxide film 6 and the polycrystalline silicon film 5 are sequentially dry-etched by a gas system containing fluorine or chlorine. As a result, the natural oxide film 6a and the polycrystalline silicon film 5a are formed. The first side wall 9a is selectively removed by hot phosphoric acid [FIG. 1 (b)].

100-200 nm by LPCVD method
A silicon dioxide film having a thickness of 2 is deposited, and RIE is performed on the silicon dioxide film with a gas system containing fluorine to form the second sidewall 11 [FIG. 1 (c)]. The gate electrode of this embodiment is formed from the N-type polycrystalline silicon film 5a which is the lower layer gate electrode, the N-type polycrystalline silicon film 7 which is the upper layer gate electrode (and the natural oxide film 6a, the second sidewall 11). Composed.

Arsenic is added at 20 to 70 keV, 1 to 5 × 10 ¹⁵
cm ⁻² ions are implanted to form an N-type high concentration layer 10a on the surface of the silicon substrate 1 [FIG. 1 (d)]. The following is the same as the normal process. A BPSG film is grown to a thickness of 600 to 800 nm by the CVD method, and reflow is performed in a nitrogen atmosphere at 850 to 900 ° C. for 20 to 40 minutes. A contact hole is opened by photolithography. Thickness 0.
An aluminum film containing silicon having a thickness of 6 to 1.0 μm is sputtered, and a wiring metal is patterned by photolithography.

[0016]

As described above, according to the present invention, the gate
In a method of manufacturing a MOS transistor having an overlap type LDD structure (inverted T-shaped gate electrode),
By separating the side wall for determining the gate electrode length and the side wall for forming the high concentration layer, the overlap between the gate electrode and the source or drain can be zero.

As a result, increase in parasitic capacitance, which is a drawback of the conventional MOS transistor having an inverted T-shaped gate electrode,
It is possible to solve the problem of occurrence of band-to-band tunneling and further improve the performance of the MOS transistor having this structure.

[Brief description of drawings]

FIG. 1 is a cross-sectional view in process order for explaining an embodiment of the present invention.

2A to 2D are cross-sectional views in order of processes for explaining a conventional method for manufacturing an integrated circuit device.

[Explanation of symbols]

 1 P-type silicon substrate 2 Field oxide film 3 P-type channel stopper 4 Gate oxide film 5, 5a, 7 N-type polycrystalline silicon film 6, 6a Natural oxide film 8 N-type low concentration layer 9, 9a, 11 Sidewall 10,10a N type high concentration layer

Claims (2)

[Claims] 1. A step of selectively forming a field oxide film and a gate oxide film on one main surface of a P-type silicon substrate, and an N-type polycrystalline silicon film is deposited on the entire surface to form the polycrystalline silicon film. A step of forming a natural oxide film on the surface and forming a conductive film on the entire surface; a step of patterning the conductive film into a desired shape by photolithography; and a step of ion implantation on the surface of the silicon substrate. A step of forming an N-type low-concentration layer and a step of depositing a first insulating film on the entire surface and performing RIE etch back to form a first insulating film on the side surface of the conductive film.
The step of forming the sidewalls of the above, the step of sequentially etching the natural oxide film and the polycrystalline silicon film using the conductor film and the first sidewall as a mask, and the removal of the first sidewall Then, a second insulating film is deposited on the entire surface, and the side surface of the conductive film, the side surface of the natural oxide film, the side surface of the polycrystalline silicon film, and the first side wall are covered by RIE etchback. Forming a second sidewall made of the second insulating film covering the upper surface of the naturally participating film, and forming an N-type high concentration layer on the surface of the silicon substrate by ion implantation And a step of depositing an interlayer insulating film on the entire surface, a step of forming a contact hole, and a step of forming a wiring metal, a method of manufacturing an integrated circuit device. 2. The method of manufacturing an integrated circuit device according to claim 1, wherein the first insulating film is a silicon nitride film.