JPS61144877A - Production of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device with low-melting point metallic gate which is capable of high-speed switching operation and suited for miniaturization, by a method wherein a gate is formed on an opening after the mask layer at the time of ion injection has been removed so as to form source and drain diffusion layers and a gate electrode self-matchingly. CONSTITUTION:An insulation film 2 of SiO2 is formed on a p type Si substrate, and an opening is partially opened on the film to form an element region. The region is heat-oxidized to form an insulation film 3 to evaporate Al on the film. Then, the Al is removed to form a mask layer 4 of Al with the photoetching method on the part which is to be a channel region. As is ion- injected to form a high-concentration n type impurity layer 5. An inter-layer insulation film 6 is formed, and a mask layer 4 is exposed with flatening etching method. Then, the layer 4 and lower insulation layer of SiO2 are removed to form a gate insulation film 7 of SiO2 on this part. An opening is opened on the film 6 onthe layer 5 to form a contact hole 10, and Al is evaporated over the surface, and a source electrode, drain electrode 8, and gate electrode 9 are formed to obtain a MOST.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a MO8 type semiconductor device using a low melting point metal such as aluminum (81) for the gate electrode. It is used for.

[Technical background of the invention]

MO8 type semiconductor device using a low melting point metal for the gate electrode,
For example, in manufacturing an aluminum gate MO8 type semiconductor device, the melting point of aluminum (6
Since heat treatment at a high temperature of about 60° C. or higher cannot be performed, the source/drain diffusion layer is generally formed before forming the gate electrode. Therefore, the source/drain diffusion layer and the gate electrode are not formed in a self-aligned manner. In other words, the edges of the source/drain diffusion layer and the edge of the gate electrode overlapped, and it was not possible to make the two edges coincide.

For this reason, methods have been developed for manufacturing source/drain diffusion layers and gate electrodes in a self-aligned manner.

Hereinafter, with reference to FIG. 2 of the accompanying drawings, a method of manufacturing a self-alignable aluminum gate MO8 type semiconductor device according to the prior art will be described, taking as an example the manufacturing process of an N-channel MOS transistor. First, as shown in Figure 2(a), P
An insulating film 12 made of a silicon dioxide film is deposited on a mold silicon substrate 11, and holes are selectively opened in portions corresponding to element regions to expose the silicon substrate.

Next, as shown in FIG. 2(b), the exposed silicon substrate 11
After forming a thin silicon dioxide film 13 on the surface of the channel, a resist 14 is left on the region including the channel portion by photolithography, and using this resist 14 as a mask, N-type impurities are ion-implanted to form a high-concentration source. A drain diffusion layer 15 is formed.

Furthermore, as shown in FIG. 2(C), an interlayer insulating film 16 is deposited on the entire surface by CVD or the like, and holes are formed in the region spanning the high concentration source/drain layers in the element region by photolithography (second Figure (d)). Thereafter, a new silicon dioxide film is grown by, for example, a thermal oxidation method to form a gate insulating film 17 as shown in FIG. A contact hole 21 is formed by opening the film.

Next, aluminum was deposited and photolithographically applied.
Source/drain electrodes 18 and gate electrodes 19 are formed in such a way that gate electrodes 19 do not overlap the heavily doped source/drain diffusion layer regions. Next, N-type impurity ions are implanted using the gate electrode 19 as a mask, and as shown in FIG. form. Then, heat treatment is performed at a temperature below the melting point of aluminum to remove impurities.
By activating lI20 and stabilizing the threshold voltage, a semiconductor device as shown in FIG. 2 (l) is manufactured.

In the semiconductor device manufactured in this way, the impurity layer 2
0 is formed in self-alignment with the gate electrode 19, so there is no overlap between the end of the gate electrode and the M portion of the source/drain region.

[Problems with background technology]

In the above manufacturing method, the source/drain diffusion layer, which is formed before the gate electrode, is formed before a low melting point alloy such as aluminum is deposited, so
It becomes possible to perform heat treatment at a high temperature of 000° C. or higher, and sufficient activation can be performed. Therefore, the source/drain diffusion layer becomes a diffusion layer with a small resistance value.

However, the impurity 1120 formed for self-alignment with the gate electrode has a concentration around the melting point of aluminum (
Since the heat treatment can only be performed at a temperature of 660° C., sufficient activation is not possible, resulting in a high resistance value. Therefore, during operation, between the source 1F111 and the channel, the drain f
Fi! A high resistance is generated between fA and the channel, leading to a decrease in conductance and making high-speed switching operation difficult. Furthermore, since the gate electrode needs to be formed with enough margin to avoid overlapping the source/drain diffusion layer, it has the disadvantage that it is not suitable for miniaturization and high integration.

[Purpose of the Invention] The present invention has been made to solve the above-mentioned drawbacks of the conventional technology, and by forming source/drain diffusion layers with extremely low resistance values and gate electrodes in a self-alignable manner, high-speed operation can be achieved. It is an object of the present invention to provide a method for manufacturing a semiconductor device having a low melting point metal gate electrode that can perform a switching operation and is suitable for miniaturization.

[Summary of the invention]

In order to achieve the above object, the present invention forms a mask layer through an insulating film in the area that will become the inter-channel region, uses this as a mask during impurity ion implantation, then forms an interlayer insulating film, and uses planarization technology to A method of manufacturing a semiconductor device is provided, in which a mask layer is selectively removed after flattening, and a gate insulating film is then formed in an opening where the mask layer is removed.

(Embodiment of the Invention) Hereinafter, an embodiment of the present invention will be described with reference to FIG. 1 of the accompanying drawings.

FIG. 1 is a cross-sectional view of the manufacturing process of a semiconductor device for forming a 1-gate MO8T-transistor into an N channel by the manufacturing method according to the same embodiment.

First, a first insulating film 2 is formed by growing a silicon dioxide film to a thickness of 5000 nm on a P-type silicon substrate 1 by thermal oxidation. Then, as shown in FIG. 1(a), the first insulator I12 is partially opened by photolithography to form an element region on the substrate 1. Then, as shown in FIG.

Next, a second insulating film 3 is formed by growing a silicon dioxide film to a thickness of 5,000 Å on the entire surface by thermal oxidation, and aluminum is deposited to a thickness of 5,000 Å on the entire surface, and a second insulating film 3 is formed by photolithography. is removed, and an aluminum mask l! is applied only to the portion that will become the channel region, as shown in FIG. 1(b). form 14. Here, this mask layer may be made of a metal other than aluminum as long as it serves as a mask during ion implantation and can be easily and selectively removed in a subsequent process. Then, 5× at an accelerating voltage of 80KV
Arsenic ions of 1015/ai are ion-implanted to form a high concentration N-type impurity layer 5 as shown in FIG. 1(b). In this case, since the mask layer 4 is formed in the Ea region which becomes the channel, ion implantation is not performed.

Next, silicon dioxide is deposited to a thickness of 1.0 μm by low-temperature vapor phase growth such as plasma CVD to form interlayer insulating film 6 as shown in FIG. 1(C). It is then etched from the top using known planarization techniques to make it planar.

Note that this etching is performed on the mask layer 4 as shown in FIG. 1(d).
Continue until exposed. Then, after removing the exposed mask layer 4 by etching, the second insulating layer 3 formed under the mask layer 4 is removed, and a pure silicon dioxide film is applied to this part using, for example, a thermal oxidation method. The gate insulating film 7 is formed as shown in FIG. 1(e).

Next, in this state, a heat treatment is performed at a high temperature (for example, Iooo°C) to sufficiently activate the high concentration N-type impurity layer 5, and then a thick interlayer insulation layer on the high concentration N-type impurity layer 5 is formed by photolithography. 116 is partially opened to form a contact hole 10 (FIG. 1(f)). Then, aluminum is deposited on the entire surface to a thickness of about 1 μm, for example, as shown in Fig. 1 (9).
), a source electrode, a drain electrode 8 and a gate electrode 9 are formed. Note that the subsequent processing is performed in accordance with a known manufacturing process for aluminum gate MOS transistors to manufacture a semiconductor device.

Therefore, according to this method, the gate electrode 9 is formed in the area where the mask layer that is used as a mask when ion-implanting the high concentration N-type impurity layer that will become the source/drain expansion layer is removed. Electrode 9 and impurity layer 5 can be formed in a self-aligned manner.

Note that the above method has been described for manufacturing an N-channel MO8 type semiconductor device, but the present invention is applicable to manufacturing a P-channel MO8 type semiconductor device.
It can also be applied to the manufacture of type semiconductor devices.

〔Effect of the invention〕

As described above, according to the present invention, by forming the gate in the area where the mask layer was removed during ion implantation, the source/drain diffusion layer and the gate electrode can be formed in a self-aligned manner, so that the conductance due to the series resistance can be reduced. A method for manufacturing a semiconductor device with a low-melting-point metal gate, which exhibits a small decrease in performance, enables high-speed switching operation, and is suitable for miniaturization can be obtained. In addition, in contrast to the conventional technology, which requires photolithography to form a gate insulating film, this invention does not require this process, thus reducing the number of mask alignment steps by one, thereby reducing the cost of the product. It is possible to achieve this goal.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a semiconductor device for explaining a manufacturing method according to an embodiment of the present invention, and FIG. 2 is a sectional view of a semiconductor device for explaining a manufacturing process according to a conventional technique. DESCRIPTION OF SYMBOLS 1... Silicon, 2... First insulating film, 3... Second insulating film, 4... Mask layer, 5... Impurity layer, 6
...Interlayer insulating film, 7... Gate insulating film.

Claims (1)

[Claims] 1. After forming a first insulating film on a semiconductor substrate, selectively removing a portion corresponding to an element region to form an opening; and forming a second insulating film in the element region. After forming the film, a step of forming a mask layer in a portion that will become a channel region, a step of forming an impurity diffusion layer in the device region other than the mask layer, and a step of forming an interlayer insulating film over at least the entire surface of the device region. After that, a step of planarizing the interlayer insulating film by etching until the mask layer is exposed, a step of selectively removing the mask layer, and a step of removing the second insulating layer under the mask layer. A method for manufacturing a semiconductor device, comprising: forming a gate insulating film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the mask layer is formed by vapor deposition of a low melting point metal. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the low melting point metal is aluminum.