JP2001196585A - Insulated-gate field-effect transistor and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an insulated-gate field-effect transistor, which has source and drain diffused layers on both sides of a gate electrode, is formed in a self- aligned manner and without etching damages, while increase in man-hours is suppressed in a process which is close to a normal process and moreover, can suppress short-channel effects and can reduce parasitic resistance, and to provide a manufacturing method of the transistor. SOLUTION: An insulated-gate transistor, which has a gate electrode provided on a semiconductor substrate via a gate insulating film, is provided with sidewall insulating films provided on both side surfaces of the gate electrode and source and drain diffused layers provided on both sides of the gate electrode, semiconductor sidewalls are respectively provided on the side surfaces of the sidewall insulating films, the semiconductor sidewalls are respectively used as each one part of the source and drain diffused layers and silicide layers are respectively provided on the surfaces of the semiconductor sidewalls.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for forming a semiconductor device. More specifically, the present invention relates to a method for forming an insulated gate field effect transistor (MOSFET).

[0002]

2. Description of the Related Art In general, a semiconductor integrated circuit often includes an insulated gate field effect transistor as a semiconductor element. At present, in the popular semiconductor integrated circuits,
Along with the miniaturization of devices, variations in threshold voltage due to variations in gate length, increase in leakage current due to deterioration of subthreshold characteristics, and deterioration of transistor characteristics due to short channel effects such as punch-through have become problems.

In order to solve this problem, it is known that a shallow source / drain junction is effective.
Therefore, conventionally, the source / drain injection energy has been reduced to achieve a shallow junction. Suppression of diffusion by activation annealing using rapid heat treatment such as lamp heating. Forming a recessed stacked diffusion layer structure transistor. Poly Si bonding source / drain diffusion layer structure. Formation of Locally stacked source / drain structures and other methods have been attempted.

For example, FIG. 8 shows a process of manufacturing an insulated gate field effect transistor by employing the above.
As shown in FIG. 7A, a gate insulating film 80 and a gate electrode 82 having an oxide film mask 85 are formed on the surface of a Si substrate 81 by a normal process. Etchback is performed to form oxide film sidewalls 83 on both sides of the gate electrode 82. Next, a poly-Si film 86 is deposited thereon, and photolithography is performed to form a resist R in the active regions (regions where source / drain is to be formed) on both sides of the gate electrode 82 as shown in FIG.
1, R1 are provided. As shown in FIG.
1, R1 is used as a mask to perform + etching to form glued poly-Si films 86a and 86a in the active region. Finally, as shown in FIG. 3D, ion implantation is performed substantially perpendicularly to the substrate surface, followed by activation annealing to form source / drain diffusion layers 87 and 87 '.

FIG. 9 shows a process for fabricating an insulated gate field effect transistor by employing the above. As shown in FIG. 9A, a gate insulating film 90 and a gate electrode 93 are formed on a Si substrate 91 by a normal process, and thereafter, oxidation is performed to oxidize the active regions on both sides of the gate electrode 93. The films 92, 92 are formed, and the gate electrode 93 is formed.
Oxide films 95 and 9 on the surface and both side surfaces of
4, 94 are formed. Next, by performing photolithography, resists R2 and R2 are provided in the active regions on both sides of the gate electrode 93 while being separated from the gate electrode 93.
The resists R2 and R2 and the oxide film 9 on the surface of the gate electrode
By using the mask 5 as a mask, the oxide film 92 is etched to form openings Δ and Δ ′ on both sides of the gate electrode 92. continue,
As shown in FIG. 3B, after removing the resists R2 and R2, doped poly-Si (not shown) is deposited on the entire surface, and impurities contained in the doped poly-Si are removed from the openings Δ and Δ. 'And diffuse to the substrate surface by heat treatment. Thereby, on the substrate surface on both sides of the gate electrode 93,
Local shallow junction source / drain diffusion layer 9 for electric field relaxation
6, 96 '. Thereafter, anisotropic etch-back is performed to form a gate electrode 93 (more precisely, oxide films 94, 94).
, Local shallow junction source / drain diffusion layers 96, 9
Form local stacked layer sidewalls 97, 97 in electrical contact with 6 '. Next, as shown in FIG.
Gate electrode 93 and local stacked layer sidewall 9
Using the masks 7 and 97 as masks, impurities are ion-implanted substantially perpendicularly to the substrate surface and deeper than the depths of the local shallow junction source / drain diffusion layers 96 and 96 'to form the local shallow junction source / drain diffusion layers 96 and 96'. Are formed on both sides of the source / drain diffusion layers 98 and 98 '. Finally, Figure (d)
As shown in (1), the heat treatment is performed to activate the implanted impurities.

[0006]

By the way, if the source / drain junction is simply made shallow, the short channel effect can be suppressed, but the resistance of the diffusion layer is increased and the performance of the device is degraded. Further, the following problems arise in making the source / drain junction shallower by the above methods (1) and (2).

First, in the above method, there is a lower limit to the energy that can be controlled by the ion implantation energy, and at low energies, the problem of spreading of impurity ions due to the channeling phenomenon becomes a problem. This limits the depth of the diffusion layer,
The desired shallow junction cannot be achieved.

Although the above method is effective in suppressing diffusion by shortening the diffusion time, when ion implantation is used for impurity implantation, the effect of channeling cannot be avoided as in the above case. For this reason, the depth of the diffusion layer is limited, and the desired shallow junction cannot be achieved.

[0009] Further, the shallow junction by the recess type stacked structure described above forms a diffusion layer above the channel surface,
After removing a portion of the diffusion layer existing in the channel region by recess etching, poly-Si is deposited on the entire surface,
Since the gate electrode is formed by patterning, the channel region and the diffusion layer cannot be formed in a self-aligned manner with the gate electrode. For this reason, problems such as an increase in area due to an alignment margin and variations in characteristics due to misalignment are caused. Also, because of the recessed structure,
The difference from the normal process is large. Further, there are problems such as etching damage of the channel portion and deterioration of flatness of the active region.

In the above method, as shown in FIG. 8, a poly-Si film 86 is attached to a layer above the substrate surface.
a, 86a are formed, and impurities are introduced into the substrate 81 by diffusion from the poly-Si films 86a, 86a to form the source / drain diffusion layers 87, 87 '. Sometimes not affected by channeling, it is extremely effective for shallow junctions. Further, since the process up to the formation of the gate electrode 82 is a normal process, unlike the above method, there is no problem caused by the formation of the recess structure. However, since the poly-Si film 86 deposited on the entire surface after the gate is formed is patterned by performing photolithography, when the gate 82 is miniaturized,
Due to the separation / resolution limit of the source / drain and the misalignment, it is difficult to form the bonding poly-Si films 86a, 86a. In addition, since the bonding poly-Si films 86a and 86a and the gate 82 (and the active region) are not formed in a self-joining manner, variations in characteristics due to misalignment and degradation in integration due to the necessity of an alignment margin pose a problem. Become.

Further, in the above method, as shown in FIG. 9, the junctions 96 and 96 'near the channel are formed by diffusion from a layer above the substrate surface. Effective for formation. In addition, unlike the above method, since the locally stacked layer sidewalls 97 are formed in a self-joining manner with respect to the gate 93, there is no characteristic variation due to misalignment. However, as shown in FIG.
When the thickness of 7,97 (thickness in the direction parallel to the substrate surface) is set smaller than the width of the openings Δ, Δ ′, the locally stacked layer side walls 97,97 by anisotropic etchback
At the time of formation, the surface of the Si substrate 91 is etched by overetching through the openings Δ and Δ ′, causing problems such as leakage due to etching damage and an increase in junction depth. In the worst case, the shallow junction is completely etched, resulting in poor conduction. On the other hand, when the thickness of the local stacked layer side walls 97, 97 is set to be larger than the width of the openings Δ, Δ ′, the widths of the openings Δ, Δ ′ are determined to some extent in consideration of misalignment due to photolithography. Since the width is set to be wide, there is a problem that the degree of freedom in selecting the thickness of the local stacked layer sidewalls 97, 97 is reduced (must be increased). In addition, the local stacked layer sidewalls 97, 97 that are in electrical contact with the shallow junction are also formed on a gate electrode (not shown) on the element isolation region. For this reason, photolithography and etching are separately required in order to remove the sidewall on the element isolation region and secure the source / drain insulation. As a result, the method described above can be applied to the openings Δ,
In addition to the photolithography for forming Δ ', there is a problem that the photolithography is increased twice as compared with the normal process, which complicates the process and increases the cost.

Accordingly, an object of the present invention is to provide a field effect transistor having a local shallow junction source / drain diffusion layer on both sides of a gate electrode by a process having a small difference from a normal MOSFET process while suppressing an increase in the number of steps. Provided is a method of forming a semiconductor device that can be formed in a consistent manner and without etching damage, can suppress a short channel effect without increasing the resistance of a diffusion layer, and can suppress a decrease in current driving force of a device due to a shallow junction. Is to do.

[0013]

In order to achieve the above object, an insulated gate field effect transistor according to the present invention comprises a gate electrode provided on a semiconductor substrate via a gate insulating film, and both sides of the gate electrode. A sidewall insulating film provided on the surface, a source / drain diffusion layer on both sides of the gate electrode, a semiconductor sidewall on a side surface of the sidewall insulating film, and the semiconductor sidewall,
The semiconductor sidewall is a part of a source / drain diffusion layer, and has a silicide layer on the surface of the semiconductor sidewall.

Further, the insulated gate field effect transistor has a source / drain diffusion layer connected to the source / drain diffusion layer on both sides of the semiconductor sidewall and having a deeper junction depth. Is characterized by having a silicide layer on the surface of the source / drain diffusion layer.

Further, according to a method of manufacturing an insulated gate field effect transistor of the present invention, a step of forming a gate electrode provided on a semiconductor substrate with a gate insulating film interposed therebetween, and forming sidewalls on both side surfaces of the gate electrode Forming an insulating film, forming a semiconductor film on a side surface of the sidewall insulating film by depositing and etching a semiconductor film, and depositing a high melting point metal film and performing a heat treatment on the semiconductor. And a step of silicidizing the surface of the side wall film.

Further, in the method of manufacturing an insulated gate field effect transistor, a step of forming a gate electrode provided on a semiconductor substrate with a gate insulating film interposed therebetween, and a step of forming a sidewall insulating film on both side surfaces of the gate electrode Forming a semiconductor film, depositing and etching a semiconductor film to form a semiconductor sidewall film on the side surface of the sidewall insulating film, and connecting to a source / drain diffusion layer on both sides of the semiconductor sidewall, Forming a source / drain diffusion layer having a deep junction depth; and depositing a refractory metal film and heat-treating the surface of the semiconductor sidewall film and the source / drain diffusion layer having a deeper junction depth. Are sequentially performed.

The high melting point metal layer means a metal layer having a melting point higher than that of silicon. For example, Ti.

In this specification, rapid heat treatment refers to so-called rapid thermal annealing (RTA).
Means a heat treatment that is performed rapidly without using an electric furnace. For example, it refers to heat treatment by lamp heating.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for forming a semiconductor device according to the present invention will be described in detail with reference to examples.

FIG. 1 shows a cross-sectional structure of an insulated gate field effect transistor to be manufactured by the forming method according to the first embodiment of the present invention. In FIG. 1, a P-type single crystal Si substrate 1
Is partitioned by element isolation regions 15, and the region surrounded by the element isolation regions 15, 15 is an active region. 2 is a gate insulating film, 3 is a gate electrode, 4 is a first sidewall insulating film 6, is a protective insulating film, 8 is a semiconductor sidewall, 10, 10 'is a local shallow junction source / drain diffusion layer, 11, 11'. Denotes deep junction source / drain diffusion layers. The local shallow junction source / drain diffusion layers 10 and 10 ′ are provided on the surface of the active region on both sides of the gate electrode 3. Deep junction source / drain diffusion layers 11, 1
1 ′ is the local shallow junction source / drain diffusion layer 10, 1
It has a junction depth that is greater than the junction depth of the local shallow junction source / drain diffusion layers 10 and 10 ′.

FIG. 2 shows N as a first embodiment of the present invention.
4 shows a step of forming a channel insulated gate field effect transistor. The present invention is not limited to the N channel,
The same applies to channels. Next, a process of forming the insulated gate field effect transistor will be described with reference to FIG.

As shown in FIG. 2A, first, a gate electrode 3 is formed on a P-type Si substrate 1 by an ordinary MOSFET process.
Advance the process up to formation. That is, an element isolation region 15 is provided on the surface of the Si substrate 1 by a local oxidation method, and a region between the element isolation regions 15 is defined as an active region. After the gate insulating film 2 is formed in the active region, a gate electrode 3 having a substantially rectangular cross section is formed at approximately the center of the active region by photolithography and etching using the interlayer insulating film 16 and a resist (not shown) as a mask. . The gate insulating film 2 has the same pattern as the gate electrode 3. The material of the interlayer insulating film 16 is, for example, SiO ₂ . By leaving the interlayer insulating film 16, the gate electrode 3 can be protected in the subsequent steps.

Thereafter, an insulating film such as SiO ₂ is formed to a thickness of 100 to
The first sidewall insulating films 4 and 4 made of SiO ₂ or the like are formed on both sides of the gate electrode 3 by etch-back.

Next, the first sidewall insulating film 4 is made of a material having a selectivity in isotropic etching such as wet etching, for example, Si ₃ N ₄ or the like with a thickness of 500 to 150.
The first sidewall insulating films 4 and 4 are deposited on the exposed side surfaces by etching back.
₃ to form a second sidewall insulating film 5 and 5 made of N ₄ or the like.

Next, a second side wall insulating film is formed by using a deposition method having poor step coverage such as sputtering, atmospheric pressure CVD (chemical vapor deposition), ozone TEOS (tetraethoxysilane) atmospheric pressure CVD, or the like. The film 5 and the semiconductor film 7 (see FIG.
(d)) SiO ₂ that is selective in etching
Then, a protective insulating film 6 is deposited. As shown in FIG. 3A, the thickness of the step, that is, the thickness of the portion covering the side surface of the second sidewall insulating film 5 is larger than the thickness of the portion covering the flat surface of the insulating film 6 due to the deposition method. It becomes a thin state. The thickness of the insulating film 6 is set in the range of 200 to 2000 ° on a flat surface.

Next, as shown in FIG. 2B, isotropic etching such as wet etching is performed on the insulating film 6 to expose the side surface of the second sidewall insulating film 5 while the insulating film 6 is insulated. A portion of the film 6 on the surface of the gate electrode 3 and on the surface of the substrate is left with a slight thickness. This etching can be performed because the second sidewall insulating film 5 of the insulating film 6 is formed due to the deposition method in the previous step.
This is because the thickness of the portion covering the side surface is thinner than the thickness of the portion covering the flat surface.

Next, as shown in FIG. 2C, the second sidewall insulating film 5 is selectively phosphorized with respect to the first sidewall insulating film 4 and the insulating film 6 remaining on the flat portion. Openings δ, δ for exposing the substrate surface are formed on both sides of the first sidewall insulating film 4 by removing the acid boil or the like by etching. At this time, the substrate surface is not etched through the openings δ, δ.

Next, as shown in FIG.
The semiconductor film 7 is deposited to have a substantially uniform thickness and to fill the openings δ, δ by using a deposition method having a good step coverage such as the above. In this example, the material of the semiconductor film 7 is polySi formed by a CVD method, single crystal Si formed by an epitaxial growth, or the like. The thickness of the semiconductor film 7 is in the range of 700 to 2000 °.

Next, the semiconductor film 7 on the element isolation region 15 is removed by patterning using photolithography and etching such as RIE. This is a completed state,
This is for ensuring insulation of the source and drain for each element.

Next, as shown in FIG.
To anisotropic etchback by RIE etc.
A first side wall insulating film formed of a semiconductor film;
4, and a semiconductor sidewall 8 covering the openings δ, δ is formed. The semiconductor sidewall 7 is formed in a self-aligned manner with the gate electrode 3. Here, even if overetching is performed, the semiconductor sidewall 8 covers the opening δ, and the insulating film 6 has selectivity with the semiconductor sidewall 8 (semiconductor film 7) during etching. Is stopped by the insulating film 6, and the substrate surface in the active region is not etched. The surface of gate electrode 3 is protected by interlayer insulating film 16. The thickness of the semiconductor sidewall 8 in the vertical direction is adjusted within the range of 1000 to 2000 ° by adjusting the etch back amount.

Next, from a direction substantially perpendicular to the substrate surface,
Using the gate electrode 3, the first sidewall insulating films 4, 4 and the semiconductor sidewalls 8, 8 as a mask, ⁷⁵ As ⁺
Ions are implanted under the conditions of an acceleration energy of 40 keV to 200 keV and a dose of 5 to 50 × 10 ¹⁴ cm ⁻² . Source / drain diffusion layers 10, 10 ', 11, 11' by heat treatment
To form Depending on the set value of the acceleration energy, ⁷⁵ As ⁺ ions remain in the mask in the regions where the masks 3, 4, 4, 8, and 8 are present, while ⁷⁵ As ⁺ ions in the active regions on both sides of the semiconductor sidewalls 8 and 8. Reaches the substrate surface through the insulating film 6.

Next, a heat treatment is performed to diffuse ⁷⁵ As implanted into the semiconductor sidewalls into the substrate surface through the openings δ, δ, and to form a local shallow junction source / drain diffusion on both sides of the gate electrode 3. The layers 10 and 10 'are formed, and at the same time, ⁷⁵ As implanted into the substrate surface on both sides of the semiconductor sidewalls 8 and 8 is activated, and the local shallow junction source / drain diffusion layers 10, 10' opposite to the gate electrode 3 are formed. The deep junction source / drain diffusion layers 11 and 11 'having a junction depth larger than the junction depth of the local shallow junction source / drain diffusion layers 10 and 10' are formed.

As described above, in the region where the semiconductor sidewall 8 is formed near the gate electrode 3, impurities are introduced into the substrate surface by diffusion from a layer above the substrate surface (semiconductor sidewall 8), and a local shallow junction source / drain region is formed. Since the diffusion layers 10 and 10 'are formed, unlike the case where the diffusion layers are formed by normal ion implantation, there is no influence of channeling at the time of ion implantation. Moreover, since the junction is formed by diffusion from the upper layer of the substrate surface, an extremely shallow junction can be formed, and thus the short channel effect can be effectively suppressed.

In the active regions on both sides of the semiconductor sidewalls 8, 8, impurities are directly implanted into the substrate through the insulating film 6 during ion implantation and diffused by heat treatment. , 10 ′ can be formed. Thereby, the junction depth can be increased in a region away from the channel (immediately below the gate electrode 3) and relatively less affected by the short channel effect. As a result,
The sheet resistance can be reduced to suppress an increase in parasitic resistance.
In addition, since the semiconductor sidewalls 8, 8 function as a part of the diffusion layers 10, 10 'in the region where the semiconductor sidewalls 8, 8 are formed, an increase in resistance due to a shallow junction can be suppressed.

In the region where the semiconductor sidewall 8 is formed near the gate electrode 3 at the time of ion implantation, impurities are not directly implanted into the substrate due to the offset due to the thickness of the semiconductor sidewall 8, so that the region near the channel is not used. The occurrence of defects can be suppressed, and the reverse short channel effect caused by the occurrence of defects can be suppressed. In addition, as a result of carriers accumulating at the interface of the semiconductor sidewall on the gate electrode side by the gate electric field, the transconductance can be increased. With these effects, a reduction in the current driving force of the element due to the shallow junction can be suppressed, and the element can have a high current driving force.

The process up to the formation of the gate electrode 3 is the same as the usual process for forming an insulated gate type field effect transistor, and the semiconductor sidewalls 8, 8 completely cover the openings δ, δ '. However, there is no problem such as etching damage as in the case of using the conventional recess method (method) and the case of local accumulation (method). Further, the local shallow junction source / drain diffusion layers 10, 10 'and the deep junction source / drain diffusion layers 11, 11' are formed in a self-junction with the gate electrode 3 without patterning using photolithography. Unlike the case (method) of the recess method and the case (method) of the bonded poly-Si, there is no problem such as an increase in area due to an alignment margin and a variation in characteristics due to misalignment.

An MO that simultaneously realizes suppression of a short channel structure and high current driving force by one photolithography increase compared to a normal MOSFET process.
An SFET can be formed. Therefore, the process can be simplified as compared with the case of the conventional local stacking (method).

In the ion implantation step, the substrate
In addition to injection from a direction substantially perpendicular to the surface,
At a large angle (30 to 90 degrees) from a diagonal direction to the surface
And heat treatment may be performed. This oblique direction
The acceleration energy of the ON implantation depends on the ion species of the impurity.³¹P
⁺In the case of 40 to 150 keV, the ionic species of the impurity is⁷⁵As ⁺
In this case, 150 keV to 300 keV is preferable. Injection volume is 1 × 1
0¹⁴cm^-2~ 1 × 10^Fifteencm^-2Is good. Injection, total injection volume
Equally divided (4 to 8 divisions)
Rotate the substrate 1 by the same division as the above division
Injection method (step injection) is used. Or constant speed
Injection method (rotational injection) in which injection is performed while rotating the substrate with
U. The rotation speed is about 2 rps. A place like this
In this case, the entirety of the semiconductor sidewall 8, particularly near the substrate surface,
Impurities can be efficiently implanted into the contacted portions. As a result,
When the semiconductor sidewall 8 can be made n-type at a high concentration,
In addition, a relatively high concentration n
A mold region can be formed. In normal source / drain formation,
Channeling during on-implant and accelerated expansion due to implant damage
It is difficult to obtain a shallow junction due to scattering.
Now, a relatively high concentration n-type region is formed in the Si substrate 1 by thermal diffusion.
So that a shallow junction can be obtained effectively
You. Also, at the time of ion implantation, a semiconductor near the gate electrode 3 is formed.
In the region where the sidewall 8 is formed, the semiconductor sidewall is formed.
Impurities due to the presence of offset due to the thickness of the wall 8
Is not directly injected into the substrate, so that
The occurrence of defects can be suppressed, and the reverse short channel
Effect can be suppressed. Note that the ion implantation
The large tilt angle corresponds to the Faraday cup (dose amount of the injection device).
Is limited to about 60 degrees
is there. In this case, the injection from the above oblique direction is the maximum inclination
Set to 60 degrees. In addition, the ion species is⁷⁵As⁺When ³¹P
⁺Not only¹²²Sb⁺But good.

FIG. 3 shows a second embodiment of the present invention.
4 shows a step of forming a channel insulated gate field effect transistor. The present invention is not limited to the N channel,
The same applies to channels. Next, a process for forming the insulated gate field effect transistor will be described with reference to FIG.

As shown in FIG. 3A, first, the steps until the gate electrode 103 is formed on the P-type Si substrate 101 by a normal MOSFET process. That is, the element isolation region 115 is formed on the surface of the Si substrate 101 by the local oxidation method.
Is provided, and a region between the element isolation regions 115 is defined as an active region. After the gate insulating film 102 is formed in the active region, a gate electrode 103 (thickness: 1000 to 2000 膜厚) having a substantially rectangular cross section is formed by photolithography and etching using a resist (not shown) as a mask. Note that the gate insulating film 102 has the same pattern as the gate electrode 103.

Thereafter, SiO ₂ , Si ₃ N _{4 is formed} by the CVD method.
Depositing an insulating film and the like, and etched back by anisotropic etching, SiO ₂ on both sides of the gate electrode 103,
First sidewall insulating film 10 made of Si ₃ N ₄ or the like
4,104 (thickness: 300 to 1000).

Next, as shown in FIG.
The semiconductor film 10 is formed using a deposition method having a good step coverage such as
7 to a substantially uniform thickness. In this example, the semiconductor film 1
The material of 07 is poly-Si formed by a CVD method, single-crystal Si formed by epitaxial growth, or the like. The thickness of the semiconductor film 107 is in the range of 500 to 2000 °.

Next, the semiconductor film 107 on the element isolation region 115 is removed by patterning using photolithography and etching such as RIE. This is to ensure source / drain insulation for each element in the completed state.

Next, as shown in FIG.
07 is anisotropically etched to obtain the semiconductor film 10.
7, the portions existing on the surface of the gate electrode 103 and on the substrate surface of the active region are made thin (about several hundred degrees), while the side wall insulating film 10 of the semiconductor film 107 is made thin.
The portion in contact with the side surface of 4,104 is left thick. The reason that the substrate surface in the active region is not exposed is that the substrate surface is not damaged.

Next, as shown in FIG.
07 is oxidized or nitrided by about several hundreds of degrees to completely change portions of the semiconductor film 107 on the surface of the gate electrode 103 and on the substrate surface of the active region into the protective insulating film 109, A semiconductor sidewall 108 is formed by leaving a portion of 107 that is in contact with the side surfaces of the sidewall insulating films 104 and 104 with a small thickness.
Here, the insulating film 10 is used for a later ion implantation step.
9 is etched to a thickness of about 100 to 300 °.

Next, as shown in FIG. 3E, using the gate electrode 103, the side wall insulating films 104, 104 and the semiconductor side walls 108, 108 as a mask, a large inclination angle (30 ~ 90 degrees)
Then, an n-type impurity is ion-implanted. The acceleration energy of this oblique ion implantation is such that the ion species of the impurity is ³¹
60 to 150 keV in the case of P ⁺ , the ionic species of the impurity is ⁷⁵ As
^In the case of ⁺ , 150 keV to 200 keV is good. Injection volume is 1 ×
10 ¹⁴ cm ^-2 to 1 × 10 ¹⁵ cm ^-2 is good. The masks 103, 104, 104, and 10 are set according to the set value of the acceleration energy.
In the region where the semiconductor layers 108 and 108 exist, the impurity ions remain in the mask, while in the active regions on both sides of the semiconductor sidewalls 108 and 108, the impurity ions penetrate the insulating film 109 and reach the substrate surface (in FIG. The implanted regions are indicated by 110 and 110 '). Injection
The total injection amount is equally divided (4 to 8 divisions), and each time a single division amount is injected, the circumference of the substrate 1 is divided by the same amount as the above division.
This is performed by an injection method (step injection) in which 01 is rotated. Alternatively, an injection method that performs injection while rotating the substrate at a constant speed
(Rotary injection). The rotation speed is about 2 rps. In this case, the entire semiconductor sidewall 108,
In particular, impurities can be efficiently implanted into a portion close to the substrate surface. As a result, the semiconductor sidewall 108 can be made highly n-type and a relatively high-concentration n-type region can be formed directly below the semiconductor sidewall 108. In normal source / drain formation, it is difficult to obtain a shallow junction due to channeling during ion implantation and accelerated diffusion due to implantation damage. However, in this step, a relatively high concentration n-type region is formed in the Si substrate 101 by thermal diffusion. Since it is formed, a shallow junction can be obtained effectively. Further, at the time of ion implantation, the semiconductor sidewall 10 near the gate electrode 103 is formed.
In the region where 8 is formed, impurities are not directly injected into the substrate due to the presence of an offset due to the thickness of the semiconductor sidewall 108, so that generation of defects near the channel can be suppressed, and the reverse short channel effect due to the generation of defects can be reduced. Can be suppressed. Note that the maximum tilt angle of ion implantation is
It may be limited to about 60 degrees due to the structure of the Faraday cup of the injection device. In this case, the injection from the oblique direction is set at a maximum inclination angle of 60 degrees. Further, the ion species is not limited to ⁷⁵ As ⁺ and ³¹ P ⁺ , but may be ¹²² Sb ⁺ .

Subsequently, as shown in FIG. 3F, the gate electrode 103, the side wall insulating films 104, 104 and the semiconductor side walls 108, 108 are used as masks.
⁷⁵ As ⁺ is ion-implanted from a direction substantially perpendicular to the substrate surface. The acceleration energy is about 40 to 60 keV. Similarly to the case where the implantation is performed from an oblique direction, the masks 103, 104, 104, and 10 are set according to the set value of the acceleration energy.
In the region where the semiconductor layers 108 and 108 exist, the impurity ions remain in the mask, while in the active regions on both sides of the semiconductor sidewalls 108 and 108, the impurity ions penetrate the insulating film 109 and reach the substrate surface (in FIG. The implanted regions are indicated by 111 and 111 '.) The ion species is not limited to ⁷⁵ As ⁺ , but may be ³¹ P ⁺ or ¹²² Sb ⁺ . Further, the injection step from the vertical direction may be performed before the injection step from the oblique direction.

Finally, as shown in FIG. 3 (g), heat treatment is performed to diffuse ⁷⁵ As or the like injected into
3 is formed on both sides of the local shallow junction source / drain diffusion layers 110, 1
10 'and the semiconductor sidewall 10
Activate the ⁷⁵ As implanted into the substrate surface on both sides of each of the local shallow junction source / drain diffusion layers 110 and 11.
The deep junction source / drain diffusion layer 1 connected to the side opposite to the gate electrode 103 of 0 ′ and having a junction depth larger than the junction depth of the local shallow junction source / drain diffusion layers 110 and 110 ′.
11, 111 'are formed.

As described above, in the region where the semiconductor sidewall 108 is formed near the gate electrode 103, the impurity is introduced into the substrate surface by diffusion from a layer above the substrate surface (semiconductor sidewall 108), and the local shallow junction source / drain is formed. Since the diffusion layers 110 and 110 'are formed, unlike the case where the diffusion layers are formed by ordinary ion implantation,
Not affected by channeling during ion implantation. Moreover, since the junction is formed by diffusion from the upper layer of the substrate surface, an extremely shallow junction can be formed, and thus the short channel effect can be effectively suppressed.

The semiconductor sidewalls 108 and 10
In the active regions on both sides of the insulating film 10, the insulating film 10
9, the impurity is directly implanted into the substrate and diffused by heat treatment.
Source / drain diffusion layers 111, 111 'having a junction depth larger than the junction depth of 0,110' can be formed. Thus, the junction depth can be increased in a region relatively short of the short channel effect away from the channel (immediately below the gate electrode 103). As a result, the sheet resistance can be reduced and the increase in the parasitic resistance can be suppressed. In addition, since the semiconductor sidewalls 108, 108 function as a part of the diffusion layers 110, 110 'in the regions where the semiconductor sidewalls 108, 108 are formed, an increase in resistance due to the shallow junction can be suppressed.

Further, at the time of ion implantation, the gate electrode 103
In the region where the semiconductor sidewall 108 is formed in the vicinity, the impurity is not directly implanted into the substrate due to the presence of the offset due to the thickness of the semiconductor sidewall 108, so that the generation of defects near the channel can be suppressed and the generation of the defects can be caused. The reverse short channel effect can be suppressed. In addition, as a result of carriers accumulating at the interface of the semiconductor sidewall on the gate electrode side by the gate electric field, the transconductance can be increased. With these effects, a reduction in the current driving force of the element due to the shallow junction can be suppressed, and the element can have a high current driving force.

The process up to the formation of the gate electrode 103 is the same as the process for forming an ordinary insulated gate field effect transistor.
Since no opening is provided at the point of, the conventional recess method is used (method) or the local stacking method (method)
Such a problem as etching damage does not occur. Further, local shallow junction source / drain diffusion layers 110 and 110 '
And the deep junction source / drain diffusion layers 111 and 111 'are formed in a self-junction with the gate electrode 103 without patterning using photolithography. Unlike the case (method), problems such as an increase in area due to an alignment margin and a variation in characteristics due to misalignment do not occur.

An MO that simultaneously suppresses the short-channel structure and increases the driving current with a single increase in photolithography compared to the normal MOSFET process.
An SFET can be formed. Therefore, the process can be simplified as compared with the case of the conventional local stacking (method).

FIG. 4 shows a third embodiment of the present invention.
4 shows a step of forming a channel insulated gate field effect transistor. The present invention is not limited to the N channel,
The same applies to channels. Next, a process of forming an insulated gate field effect transistor will be described with reference to FIG.

As shown in FIG. 4A, first, the steps until the gate electrode 203 is formed on the P-type Si substrate 201 by a normal MOSFET process. That is, the element isolation region 215 is formed on the surface of the Si substrate 201 by the local oxidation method.
Is provided, and a region between the element isolation regions 215 is defined as an active region. After the gate insulating film 202 is formed in the active region, the gate electrode 2 having a substantially rectangular cross section is formed substantially at the center of the active region by photolithography and etching.
03 (thickness: 1000 to 2000 °). Note that the gate insulating film 202 has the same pattern as the gate electrode 203.

Thereafter, SiO ₂ , Si ₃ N _{4 is formed} by the CVD method.
Is deposited by etching back by anisotropic etching, and SiO ₂ ,
First sidewall insulating film 20 made of Si ₃ N ₄ or the like
4,204 (thickness: 300 to 1000).

Next, as shown in FIG.
The semiconductor film 20 is deposited using a deposition method having a good step coverage such as
7 to a substantially uniform thickness. In this example, the semiconductor film 2
The material of 07 is poly-Si formed by a CVD method, single-crystal Si formed by epitaxial growth, or the like. The thickness of the semiconductor film 207 is in the range of 500 to 1500 °.

Next, the semiconductor film 207 on the element isolation region 215 is removed by patterning using photolithography and etching such as RIE. This is to ensure source / drain insulation for each element in the completed state.

Next, as shown in FIG.
By using a deposition method having a good step coverage such as Si ₃ N _{4, the} insulating film 205 having a property of not being oxidized such as Si ₃ N ₄ is formed to a substantially uniform thickness.
(500-1000 °).

Next, as shown in FIG. 4D, the insulating film 205 is anisotropically etched to form the semiconductor film 2.
A second sidewall insulating film 205 is formed to cover the side surface of the gate electrode 203 via the gate electrode.

Next, as shown in FIG. 4E, the second sidewall insulating film 205 is used as a mask to oxidize, for example, the surface of the gate electrode 203 of the semiconductor film 207 and the substrate surface of the active region. While the upper portion is changed to a protective insulating film 206 made of SiO ₂ , the first sidewall insulating film 204 and the second
207 sandwiched between side wall insulating film 205
The semiconductor sidewall 208 is left with a. Here, for the subsequent ion implantation step, the insulating film 9 is etched to a thickness of about 100 to 300 °.

Next, as shown in FIG. 4F, using the gate electrode 203, the side wall insulating films 204, 204 and the semiconductor side walls 208, 208 as a mask, a large inclination angle (30 ~ 90 degrees)
Then, an n-type impurity is ion-implanted. The acceleration energy of this oblique ion implantation is such that the ion species of the impurity is ³¹
60 to 150 keV in the case of P ⁺ , the ionic species of the impurity is ⁷⁵ As
^In the case of ⁺ , 150 keV to 200 keV is good. Injection volume is 1 ×
10 ¹⁴ cm ^-2 to 1 × 10 ¹⁵ cm ^-2 is good. The masks 203, 204, 204, and 20 are set according to the set value of the acceleration energy.
In the region where 8, 208 exist, the impurity ions remain in the mask, while in the active regions on both sides of the semiconductor sidewalls 208, 208, the impurity ions penetrate the insulating film 206 and reach the substrate surface (in FIG. The implanted regions are indicated by 210 and 210 '). Injection
The total injection amount is equally divided (4 to 8 divisions), and each time a single division amount is injected, the circumference of the substrate 2 is divided by the same division amount as the above division.
This is performed by an injection method (step injection) in which 01 is rotated. Alternatively, an injection method that performs injection while rotating the substrate at a constant speed
(Rotary injection). The rotation speed is about 2 rps. In this case, the entire semiconductor sidewall 208,
In particular, impurities can be efficiently implanted into a portion close to the substrate surface. As a result, the semiconductor sidewall 208 can be made highly n-type and a relatively high-concentration n-type region can be formed directly below the semiconductor sidewall 208. In normal source / drain formation, it is difficult to obtain a shallow junction due to channeling during ion implantation and accelerated diffusion due to implantation damage. However, in this step, a relatively high concentration n-type region is formed in the Si substrate 201 by thermal diffusion. Since it is formed, a shallow junction can be obtained effectively. Further, at the time of ion implantation, the semiconductor sidewall 20 near the gate electrode 203 is formed.
In the region where 8 is formed, impurities are not directly injected into the substrate due to the presence of an offset due to the thickness of the semiconductor sidewall 208, so that generation of defects near the channel can be suppressed, and the reverse short channel effect caused by the generation of defects can be reduced. Can be suppressed. Note that the maximum tilt angle of ion implantation is
It may be limited to about 60 degrees due to the structure of the Faraday cup of the injection device. In this case, the injection from the oblique direction is set at a maximum inclination angle of 60 degrees. The ion species is not limited to ⁷⁵ As and ³¹ P ⁺ , but may be ¹²² Sb ⁺ .

Subsequently, as shown in FIG. 4G, the gate electrode 203, the side wall insulating films 204 and 204, and the semiconductor side walls 208 and 208 are used as masks.
⁷⁵ As ⁺ is ion-implanted from a direction substantially perpendicular to the substrate surface. The acceleration energy is about 40 to 200 keV.
As in the case where the implantation is performed from an oblique direction, the masks 203, 204, 204, and 20 are set according to the set value of the acceleration energy.
In the region where 8, 208 exist, the impurity ions remain in the mask, while in the active regions on both sides of the semiconductor sidewalls 208, 208, the impurity ions penetrate the insulating film 206 and reach the substrate surface (in FIG. The implanted regions are indicated by 211 and 211 '). The ion species is not limited to ⁷⁵ As ⁺ , but may be ³¹ P ⁺ or ¹²² Sb ⁺ . Further, the injection step from the vertical direction may be performed before the injection step from the oblique direction.

[0064] Finally, as shown in FIG. 4 (h), heat treatment is performed by the ⁷⁵ As such injected into the 208, 208 to the semiconductor sidewall diffuse to the substrate surface, a gate electrode 20
3 is formed on both sides of the local shallow junction source / drain diffusion layers 210, 2
10 'and the semiconductor sidewall 20
Activate the ⁷⁵ As implanted into the substrate surface on both sides of 8, 208 to form local shallow junction source / drain diffusion layers 210, 21
Deep junction source / drain diffusion layer 2 connected to the side opposite to gate electrode 203 of 0 ′ and having a junction depth greater than the junction depth of local shallow junction source / drain diffusion layers 210 and 210 ′.
11, 211 'are formed.

As described above, in the region where the semiconductor sidewall 208 is formed near the gate electrode 203, an impurity is introduced into the substrate surface by diffusion from a layer above the substrate surface (semiconductor sidewall 208), so that the local shallow junction source / drain is formed. Since the diffusion layers 210 and 210 'are formed, unlike the case where the diffusion layers are formed by ordinary ion implantation,
Not affected by channeling during ion implantation. Moreover, since the junction is formed by diffusion from the upper layer of the substrate surface, an extremely shallow junction can be formed, and thus the short channel effect can be effectively suppressed.

The semiconductor sidewalls 208 and 20
In the active regions on both sides of the insulating film 8, the insulating film 20
6, impurities are directly implanted into the substrate and are diffused by heat treatment.
Source / drain diffusion layers 211 and 211 'having a junction depth larger than the junction depth of 0,210' can be formed. Accordingly, the junction depth can be increased in a region away from the channel (immediately below the gate electrode 203) and relatively less affected by the short channel effect. As a result, the sheet resistance can be reduced and the increase in the parasitic resistance can be suppressed. In addition, since the semiconductor sidewalls 208, 208 function as a part of the diffusion layers 210, 210 'in the region where the semiconductor sidewalls 208, 208 are formed, an increase in resistance due to a shallow junction can be suppressed.

Further, at the time of ion implantation, the gate electrode 203
In the region where the semiconductor sidewall 208 is formed in the vicinity, the impurity is not directly implanted into the substrate due to the presence of the offset due to the thickness of the semiconductor sidewall 208, so that the generation of defects near the channel can be suppressed, and this is caused by the generation of the defects. The reverse short channel effect can be suppressed. In addition, as a result of carriers accumulating at the interface of the semiconductor sidewall on the gate electrode side by the gate electric field, the transconductance can be increased. With these effects, a reduction in the current driving force of the element due to the shallow junction can be suppressed, and the element can have a high current driving force.

The process up to the formation of the gate electrode 203 is the same as the ordinary process of forming an insulated gate type field effect transistor.
Since no opening is provided at the point of, the conventional recess method is used (method) or the local stacking method (method)
Such a problem as etching damage does not occur. Further, local shallow junction source / drain diffusion layers 210 and 210 '
And the deep junction source / drain diffusion layers 211 and 211 'are formed in a self-junction with the gate electrode 203 without patterning using photolithography. Unlike the case (method), problems such as an increase in area due to an alignment margin and a variation in characteristics due to misalignment do not occur.

An MO that simultaneously realizes suppression of a short channel structure and high current driving force by one photolithography increase as compared with a normal MOSFET process.
An SFET can be formed. Therefore, the process can be simplified as compared with the case of the conventional local stacking (method).

FIG. 5 shows a fourth embodiment of the present invention.
4 shows a step of forming a channel insulated gate field effect transistor. The present invention is not limited to the N channel,
The same applies to channels. Next, a process for forming the insulated gate field effect transistor will be described with reference to FIG.

As shown in FIG. 5A, first, the steps until the gate electrode 303 is formed on the P-type Si substrate 301 by a normal MOSFET process. That is, the element isolation region 315 is formed on the surface of the Si substrate 301 by the local oxidation method.
To define the region between the element isolation regions 315 as an active region. After the gate insulating film 302 is formed in the active region, an interlayer insulating film 305 is formed substantially at the center of the active region.
(Thickness: 500 to 1500 °) and a resist (not shown) as a mask, a gate electrode 303 (thickness: 1000 to 2) having a substantially rectangular cross section is formed by photolithography and etching.
000 °). The material of the interlayer insulating film 305 is, for example, SiO ₂ . By leaving the interlayer insulating film 305, the gate electrode 303 can be protected in the subsequent steps.

Thereafter, an insulating film of SiO ₂ , Si ₃ N ₄ or the like is deposited in a thickness of 100 to 500 °, and is made of SiO ₂ , Si ₃ N ₄ or the like on both side surfaces of the gate electrode 303 by etch back. First sidewall insulating films 304, 304
(Thickness: 300 to 1000 °).

Next, as shown in FIG.
The semiconductor film 30 is formed using a deposition method having a good step coverage such as
7 to a substantially uniform thickness. In this example, the semiconductor film 3
The material 07 is poly Si formed by the CVD method. The single crystal S formed by epitaxial growth
It may be i. The thickness of the semiconductor film 307 is 500 to 20
Within the range of 00 °.

Next, as shown in FIG.
07 is anisotropically etched to obtain a semiconductor film 30.
7, the portions existing on the surface of the gate electrode 303 and on the substrate surface of the active region are made thin (about several hundred degrees), while the side wall insulating film 30 of the semiconductor film 307 is made thin.
The portion in contact with the side surface of 4,304 is left thick. The reason that the substrate surface in the active region is not exposed is that the substrate surface is not damaged.

Next, as shown in FIG. 5D, the semiconductor film 307 on the element isolation region 315 is removed by patterning using photolithography and etching such as RIE. This is to ensure source / drain insulation for each element in the completed state.

Next, as shown in FIG.
07 is oxidized or nitrided by several hundreds of degrees to completely change portions of the semiconductor film 307 on the surface of the gate electrode 303 and on the substrate surface of the active region into the protective insulating film 309, A portion 30 of 307 in contact with the side surfaces of sidewall insulating films 304 and 304
7a, leaving the semiconductor sidewall 308 with a slight thickness.
And

Next, as shown in FIG. 5F, the insulating film 309 formed by the above oxidation or nitridation is removed by isotropic etching such as wet etching, and the side surfaces of the semiconductor sidewalls 308, 308 and After exposing the surface of the substrate in the active region, a high melting point metal film 312 such as Ti is deposited within a thickness range of 200 to 1000 °.

Next, as shown in FIG. 5 (g), as a first rapid heat treatment (RTA), lamp heating was performed at a temperature of 575 ° C. to 625 ° C. in a nitrogen atmosphere for a time of 15 to 30 seconds.
A silicide layer 313 is formed as an alloy layer between the refractory metal film 312 and the side surface of the semiconductor sidewall 308 made of polySi and the substrate surface in the active region. Due to the RTA heat treatment, the crystal structure of the silicide layer 313 is in a metastable state.

Next, as shown in FIG. 5 (h), the gate electrode 303, the side wall insulating films 304, 304 and the semiconductor side walls 308, 308 are used as masks to form a large oblique angle (30 ~ 90 degrees)
Then, an n-type impurity is ion-implanted. The acceleration energy of this oblique ion implantation is such that the ion species of the impurity is ³¹
40 to 200 keV in the case of P ⁺ , the ionic species of the impurity is ⁷⁵ As
^In the case of ⁺ , 60 keV to 400 keV is good. Injection volume is 1 × 1
0 ¹⁴ cm ^-2 to 1 × 10 ¹⁵ cm ^-2 is good. The masks 303, 304, 304, and 30 are set according to the set value of the acceleration energy.
In the regions where the semiconductor sidewalls 8 and 308 exist, the impurity ions remain in the mask, while in the active regions on both sides of the semiconductor sidewalls 308 and 308, the impurity ions penetrate the unreacted refractory metal film 312 and the silicide layer 313 and pass through the substrate. The surface reaches the surface (in this figure, the region into which the impurity is implanted is 31).
0,310 '. ). The injection is performed by an injection method (step injection) in which the total injection amount is equally divided (4 to 8 divisions), and each time one division amount is injected, the circumference of the substrate 301 is rotated by the same division amount as the above division. Alternatively, it is performed by an injection method (rotational injection) in which the injection is performed while rotating the substrate at a constant speed. The rotation speed is about 2 rps. In this case, impurities can be efficiently implanted into the entire semiconductor sidewall 308, particularly, a portion close to the substrate surface. As a result, the semiconductor sidewall 308 can be made highly n-type and a relatively high-concentration n-type region can be formed directly below the semiconductor sidewall 308. In normal source / drain formation, it is difficult to obtain a shallow junction due to channeling during ion implantation and accelerated diffusion due to implantation damage. However, in this step, a relatively high concentration n-type region is formed in the Si substrate 301 by thermal diffusion. Since it is formed, a shallow junction can be obtained effectively. In addition, in the region where the semiconductor sidewall 308 is formed near the gate electrode 303 at the time of ion implantation, impurities are not directly implanted into the substrate due to the offset due to the thickness of the semiconductor sidewall 308. It is possible to suppress the reverse short channel effect caused by the occurrence of the defect. The maximum inclination angle of the ion implantation may be limited to about 60 degrees due to the structure of the Faraday cup of the implantation apparatus. In this case, the injection from the oblique direction is set at a maximum inclination angle of 60 degrees. The ion species are ⁷⁵ As ⁺ and ³¹
Not limited to P ^+, it may be ¹²² Sb ⁺ .

Subsequently, as shown in FIG. 5I, the gate electrode 303, the side wall insulating films 304 and 304, and the semiconductor side walls 308 and 308 are used as masks.
⁷⁵ As ⁺ is ion-implanted from a direction substantially perpendicular to the substrate surface. The acceleration energy is about 50 to 200 keV.
Similarly to the case where the injection is performed from an oblique direction, the masks 303, 304, 304, and 30 are set according to the set value of the acceleration energy.
In the regions where the semiconductor sidewalls 8 and 308 exist, the impurity ions remain in the mask, while in the active regions on both sides of the semiconductor sidewalls 308 and 308, the impurity ions penetrate through the unreacted refractory metal film 312 and the silicide layer 313 and pass through the substrate surface. (In the figure, the region into which the impurity is implanted at this time is 31).
1, 311 '. ). The ion species is ⁷⁵ A
not limited to ^{s +, 31 P +, 122} Sb + any good. Further, the injection step from the vertical direction may be performed before the injection step from the oblique direction.

Next, as shown in FIG. 5 (j), the unreacted high melting point metal film 312 remaining on the substrate 301 is removed by performing wet etching of a boiling sulfuric acid or the like.

Finally, as a second rapid thermal processing (RTA), a temperature of 800 ° C. to 900 ° C. for 15 hours under a nitrogen atmosphere.
Lamp heating is performed for seconds to 30 seconds or at a temperature of 1000 ° C. to 1050 ° C. for a time of 10 seconds to 20 seconds to change the silicide layer 313 into a stable crystal structure. When the RTA conditions are a temperature of 800 ° C. to 900 ° C. and a time of 15 seconds to 30 seconds, heat treatment is further performed. At the same time, by such heat treatment, as shown in FIG. 6 (j), ⁷⁵ As or the like injected into the semiconductor sidewalls 308, 308 is diffused into the substrate surface, and the local shallow junction source is formed on both sides of the gate electrode 303. The drain diffusion layers 310 and 310 'are formed, and at the same time, ⁷⁵ As implanted into the substrate surfaces on both sides of the semiconductor sidewalls 308 and 308 is activated to form the gate electrodes 303 of the local shallow junction source / drain diffusion layers 310 and 310'.
And deep junction source / drain diffusion layers 311, 311 ′ having a junction depth greater than the junction depth of the local shallow junction source / drain diffusion layers 310, 310 ′.

As described above, in the region where the semiconductor sidewall 308 is formed near the gate electrode 303, impurities are introduced into the substrate surface by diffusion from a layer above the substrate surface (semiconductor sidewall 308), and the local shallow junction source / drain is formed. Since the diffusion layers 310 and 310 'are formed, unlike the case where the diffusion layers are formed by ordinary ion implantation,
Not affected by channeling during ion implantation. Moreover, since the junction is formed by diffusion from the upper layer of the substrate surface, an extremely shallow junction can be formed, and thus the short channel effect can be effectively suppressed.

The semiconductor sidewalls 308 and 30
In the active regions on both sides of the substrate 8, impurities are directly implanted into the substrate through the unreacted refractory metal film 312 and the silicide layer 313 during ion implantation and diffused by heat treatment. , 310 '
The source / drain diffusion layers 311 and 311 'having a junction depth deeper than the junction depth of the above can be formed. Thus, the junction depth can be increased in a region away from the channel (immediately below the gate electrode 303) and relatively less affected by the short channel effect. As a result, the sheet resistance can be reduced and the increase in the parasitic resistance can be suppressed. Moreover, the semiconductor sidewall 308,
In the region where the semiconductor sidewall 308 is formed, the semiconductor sidewall 30 is formed.
Since 8,308 serve as a part of the diffusion layers 310,310 ', an increase in resistance due to a shallow junction can be suppressed.

Further, at the time of ion implantation, the gate electrode 303
In the region where the semiconductor sidewall 308 is formed in the vicinity, the impurity is not directly injected into the substrate due to the presence of the offset due to the thickness of the semiconductor sidewall 308. Therefore, the generation of defects near the channel can be suppressed, and this is caused by the generation of defects. The reverse short channel effect can be suppressed. In addition, as a result of carriers accumulating at the interface of the semiconductor sidewall on the gate electrode side by the gate electric field, the transconductance can be increased. With these effects, a reduction in the current driving force of the element due to the shallow junction can be suppressed, and the element can have a high current driving force.

Also, due to the presence of the silicide layer 313,
The sheet resistance of the semiconductor sidewall and the deep junction source / drain diffusion layers 311 and 311 'can be reduced, and the performance of the element can be further improved. Moreover, in the above ion implantation step,
Since the silicide layer 313 exists on the substrate surface,
The range at the time of injection is reduced, and channeling is suppressed. As a result, the deep junction source / drain diffusion layers 311,
311 'can be made shallower to some extent and the short channel effect can be suppressed. At this time, since the surfaces of the deep junction source / drain diffusion layers 311 and 311 'are silicided even if the junctions are made shallow to some extent, deterioration of element performance due to increase in sheet resistance and increase in parasitic resistance does not occur. . Further, by siliciding the semiconductor sidewalls 308 and 308 in the vicinity of the gate electrode 303, the silicide layer 313 can be brought close to the vicinity of the gate electrode 303 and the series resistance can be reduced.

The process up to the formation of the gate electrode 303 is the same as the process for forming a normal insulated gate field effect transistor.
Since no opening is provided at the point of, the conventional recess method is used (method) or the local stacking method (method)
Such a problem as etching damage does not occur. Further, local shallow junction source / drain diffusion layers 310 and 310 '
The deep junction source / drain diffusion layers 311 and 311 ′ are formed in a self-junction manner with the gate electrode 303 without patterning using photolithography. Unlike the case (method), problems such as an increase in area due to an alignment margin and a variation in characteristics due to misalignment do not occur.

In addition, an MO that simultaneously suppresses a short channel structure and achieves a high current driving force can be realized by one photolithography increase as compared with a normal MOSFET process.
An SFET can be formed. Therefore, the process can be simplified as compared with the case of the conventional local stacking (method).

FIG. 6 shows a fifth embodiment of the present invention.
4 shows a process of forming a channel insulated gate field effect transistor. It should be noted that the present invention is applicable not only to the N channel but also to the P channel. Next, a process of forming the insulated gate field effect transistor will be described with reference to FIG.

As shown in FIG. 6A, first, the steps until the gate electrode 403 is formed on the P-type Si substrate 401 by a normal MOSFET process. That is, the element isolation region 415 is formed on the surface of the Si substrate 401 by the local oxidation method.
Is provided, and a region between the element isolation regions 415 is defined as an active region. After the gate insulating film 402 is formed in the active region, an interlayer insulating film 405 is formed substantially at the center of the active region.
(Thickness: 500 to 1500 °) and a resist (not shown) as a mask, photolithography and etching are performed to form a gate electrode 403 having a substantially rectangular cross section (thickness: 1000 to 2Å).
000 °). The gate insulating film 402 has the same pattern as the gate electrode 403. The material of the interlayer insulating film 405 is, for example, SiO ₂ . By leaving the interlayer insulating film 405, the gate electrode 4 can be formed in the subsequent steps.
03 can be protected.

Thereafter, SiO ₂ , Si ₃ N _{4 is formed} by the CVD method.
Depositing an insulating film equal in thickness range of 100 Å to 500 Å, and etched back by anisotropic etching, the first consisting of SiO _2, Si ₃ N ₄ or the like on both sides of the gate electrode 403
Sidewall insulating films 404, 404 (thickness 300 to
1000 °).

Next, as shown in FIG.
The semiconductor film 40 is formed using a deposition method having a good step coverage such as
7 to a substantially uniform thickness. In this example, the semiconductor film 4
The material 07 is poly Si formed by the CVD method. The single crystal S formed by epitaxial growth
It may be i or the like. The thickness of the semiconductor film 407 is 500 to 2
000Å.

Next, as shown in FIG.
07 is anisotropically etched to obtain a semiconductor film 40.
7, the portions existing on the surface of the gate electrode 403 and the active region on the substrate surface are made thin (about several hundred degrees), while the side wall insulating film 40 of the semiconductor film 407 is made thin.
The portion in contact with the side surface of 4,404 is left thick. The reason that the substrate surface in the active region is not exposed is that the substrate surface is not damaged.

Next, as shown in FIG. 6D, the semiconductor film 407 on the element isolation region 415 is removed by patterning using photolithography and etching such as RIE. This is to ensure source / drain insulation for each element in the completed state.

Next, as shown in FIG.
07 is oxidized or nitrided by several hundreds of degrees to completely change portions of the semiconductor film 407 on the surface of the gate electrode 403 and on the substrate surface of the active region into the protective insulating film 409, A semiconductor sidewall 408 is formed by leaving a portion of the sidewall 407 in contact with the side surfaces of the sidewall insulating films 404 and 404 with a small thickness.
Here, the insulating film 40 is used for a later ion implantation step.
9 is etched to a thickness of about 100 to 300 °.

Next, as shown in FIG. 6F, the gate electrode 403, the side wall insulating films 404, 404, and the semiconductor side walls 408, 408 are used as masks to make a large inclination angle (30 ~ 90 degrees)
Then, an n-type impurity is ion-implanted. The acceleration energy of this oblique ion implantation is such that the ion species of the impurity is ³¹
60 to 150 keV in the case of P ⁺ , the ionic species of the impurity is ⁷⁵ As
^In the case of ⁺ , 150 keV to 200 keV is good. Injection volume is 1 ×
10 ¹⁴ cm ^-2 to 1 × 10 ¹⁵ cm ^-2 is good. The masks 403, 404, 404, and 40 are set according to the set value of the acceleration energy.
8 and 408, the impurity ions remain in the mask, while in the active regions on both sides of the semiconductor sidewalls 408, 408, the impurity ions penetrate the insulating film 409 and reach the substrate surface (in FIG. The implanted regions are indicated by 410 and 410 '). Injection
The total injection amount is equally divided (4 to 8 divisions), and each time one division amount is injected, the circumference of the substrate 4 is divided by the same division amount as the above division.
This is performed by an injection method (step injection) in which 01 is rotated. Alternatively, an injection method that performs injection while rotating the substrate at a constant speed
(Rotary injection). The rotation speed is about 2 rps. In this case, the entirety of the semiconductor sidewall 408,
In particular, impurities can be efficiently implanted into a portion close to the substrate surface. As a result, the semiconductor sidewall 408 can be made highly n-type and a relatively high-concentration n-type region can be formed directly below the semiconductor sidewall 408. In normal source / drain formation, it is difficult to obtain a shallow junction due to channeling during ion implantation and accelerated diffusion due to implantation damage. However, in this step, a relatively high concentration n-type region is formed in the Si substrate 401 by thermal diffusion. Since it is formed, a shallow junction can be obtained effectively. Also, at the time of ion implantation, the semiconductor sidewall 40 near the gate electrode 403 is formed.
In the region where the gate electrode 8 is formed, impurities are not directly injected into the substrate due to the presence of the offset due to the thickness of the semiconductor sidewall 408, so that the generation of defects near the channel can be suppressed, and the reverse short channel effect caused by the generation of defects can be reduced. Can be suppressed. Note that the maximum tilt angle of ion implantation is
It may be limited to about 60 degrees due to the structure of the Faraday cup of the injection device. In this case, the injection from the oblique direction is set at a maximum inclination angle of 60 degrees. Further, the ion species is not limited to ⁷⁵ As ⁺ and ³¹ P ⁺ , but may be ¹²² Sb ⁺ .

Subsequently, as shown in FIG. 6G, the gate electrode 403, the sidewall insulating films 404, 404, and the semiconductor sidewalls 408, 408 are used as masks.
⁷⁵ As ⁺ is ion-implanted from a direction substantially perpendicular to the substrate surface. The acceleration energy is about 40 to 60 keV. As in the case where the implantation is performed from an oblique direction, the masks 403, 404, 404, and 40 are set according to the set value of the acceleration energy.
8 and 408, the impurity ions remain in the mask, while in the active regions on both sides of the semiconductor sidewalls 408, 408, the impurity ions penetrate the insulating film 409 and reach the substrate surface (in FIG. The implanted regions are indicated by 411 and 411 '). The ion species is not limited to ⁷⁵ As ⁺ , but may be ³¹ P ⁺ or ¹²² Sb ⁺ . Further, the injection step from the vertical direction may be performed before the injection step from the oblique direction.

[0098] Finally, as shown in FIG. 6 (h), heat treatment is performed by the ⁷⁵ As such injected into the 408, 408 to the semiconductor sidewall diffuse to the surface of the substrate, the gate electrode 40
3 shallow source / drain diffusion layers 410, 4
10 'and the semiconductor sidewall 40
By activating ⁷⁵ As implanted into the substrate surface on both sides of the 8,8,408, the local shallow junction source / drain diffusion layers 410,41
The deep junction source / drain diffusion layer 4 connected to the side opposite to the gate electrode 403 of 0 ′ and having a junction depth greater than the junction depth of the local shallow junction source / drain diffusion layers 410 and 410 ′.
11, 411 'are formed.

As described above, in the region where the semiconductor sidewall 408 is formed near the gate electrode 403, impurities are introduced into the substrate surface by diffusion from a layer above the substrate surface (semiconductor sidewall 408), and a local shallow junction source / drain region is formed. Since the diffusion layers 410 and 410 'are formed, unlike the case where the diffusion layers are formed by ordinary ion implantation,
Not affected by channeling during ion implantation. Moreover, since the junction is formed by diffusion from the upper layer of the substrate surface, an extremely shallow junction can be formed, and thus the short channel effect can be effectively suppressed.

The semiconductor sidewalls 408, 40
8 in the active regions on both sides of the insulating film 40 during ion implantation.
9, the impurity is directly implanted into the substrate and diffused by heat treatment.
Source / drain diffusion layers 411, 411 'having a junction depth larger than the junction depth of 0,410' can be formed. Accordingly, the junction depth can be increased in a region relatively short of the short channel effect away from the channel (immediately below the gate electrode 403). As a result, the sheet resistance can be reduced and the increase in the parasitic resistance can be suppressed. Moreover, since the semiconductor sidewalls 408, 408 function as a part of the diffusion layers 410, 410 'in the region where the semiconductor sidewalls 408, 408 are formed, an increase in resistance due to a shallow junction can be suppressed.

Further, at the time of ion implantation, the gate electrode 403
In the region where the semiconductor sidewall 408 is formed in the vicinity, the impurity is not directly injected into the substrate due to the presence of the offset due to the thickness of the semiconductor sidewall 408. The reverse short channel effect can be suppressed. In addition, as a result of carriers accumulating at the interface of the semiconductor sidewall on the gate electrode side by the gate electric field, the transconductance can be increased. With these effects, a reduction in the current driving force of the element due to the shallow junction can be suppressed, and the element can have a high current driving force.

The process up to the formation of the gate electrode 403 is the same as the process for forming an ordinary insulated gate field effect transistor.
Since no opening is provided at the point of, the conventional recess method is used (method) or the local stacking method (method)
Such a problem as etching damage does not occur. Further, local shallow junction source / drain diffusion layers 410, 410 '
Since the deep junction source / drain diffusion layers 411 and 411 'are formed in a self-junction with the gate electrode 403 without using patterning using photolithography, the conventional recess method (method) or the bonding of Unlike the case (method), problems such as an increase in area due to an alignment margin and a variation in characteristics due to misalignment do not occur.

In addition, an MO that simultaneously suppresses a short channel structure and achieves a high current driving force can be realized by increasing the number of times of photolithography one time as compared with a normal MOSFET process.
An SFET can be formed. Therefore, the process can be simplified as compared with the case of the conventional local stacking (method).

FIG. 7 and Table 1 show the characteristic data of the insulated gate field effect transistors LED and SLED formed according to the fifth and fourth embodiments, respectively. This is shown in comparison with a field effect transistor LDD having a junction source / drain diffusion layer and an SLDD in which the structure is salicided. The parameters and the like for producing each of the above elements were set as follows. For the above LED, a gate insulating film (SiO ₂ )
The film thickness of 402 is 5 nm, and the semiconductor film (poly Si) 40
The deposited film thickness of No. 7 was 15 nm. Further, in the ion implantation step from the oblique direction, the ion species of the impurity was ³¹ P ⁺ , the acceleration energy was 80 KeV, the tilt angle was 60 degrees, and the dose was 8 × 10 ¹⁴ cm ⁻² . In the ion implantation step from a substantially vertical direction, the ion species was set to ⁷⁵ As ⁺ , the implantation conditions were set to an acceleration energy of 40 KeV, and a dose amount of 5 × 10 ¹⁵ cm ^−2.
And As for the SLED, similarly to the LED, the thickness of the gate insulating film (SiO ₂ ) 302 is set to 50 nm,
The deposited film thickness of the semiconductor film (poly Si) 307 was set to 15 nm. Further, the thickness of the refractory metal film (Ti) 312 is set to 5n.
and m, silicide was carried out using a so-called AAS ⁽⁷⁵ As ⁺ implantation-after-silicilytes retardation) method. Further, in the ion implantation step from the oblique direction, the ion species of the impurity is ³¹ P ⁺ , the acceleration energy is 120 KeV, the inclination angle is 60 degrees, and the dose is 8 × 10 ¹⁴ c.
m ^-2 . In the ion implantation step from a substantially vertical direction, the ion species is set to ⁷⁵ As ⁺ and the acceleration energy 15
0 KeV and a dose amount of 5 × 10 ¹⁵ cm ⁻² . LD above
For D and SLDD, the processes other than the process of forming the local stacked layer (semiconductor sidewall) are performed by the above-described LE.
D, the same as SLED. The above LDD, SLD
The local shallow junction source / drain diffusion layer of D was formed under the conditions that the ion species of the impurity was ³¹ P ⁺ , the acceleration energy was 30 KeV, and the dose was 1 × 10 ¹³ cm ⁻² .

FIG. 7A shows the relationship between the threshold voltage Vth of the LED and the LDD and the effective channel length Leff.
When the effective channel length Leff is 0.5 μm or more, the LED
Is equal to the roll-off characteristic of the LDD. Comparison with an effective channel length Leff of 0.5 μm or less could not be performed because the invalid channel length of the LDD became negative. In the LED, the roll-off characteristic is suppressed to 0.3 μm, and the LDD is less than 0.1 μm.
The reverse short channel effect is suppressed more than that. This is because, as described above, at the time of ion implantation, the presence of an offset due to the thickness of the semiconductor sidewall 408 can suppress the generation of a defect near the channel, and can suppress the reverse short channel effect caused by the generation of the defect. it is conceivable that.

Table 1 shows the series resistance (sum of the source-side resistance and the drain-side resistance) of the LED, LDD, SLED, and SLDD. The series resistance of the LED and the SLED is improved over the series resistance of the LDD and the SLDD, respectively. SLD series resistance is SLD
What is greatly improved over the series resistance of D is S
This is probably because in the LED, the silicide layer is closer to the channel than in the SLDD.

FIG. 7B shows the LED, LDD, and SLE.
The saturation transconductance Gms of D and SLDD is shown. Gms of LED and SLED are LDD and S, respectively.
It is improved over Gms of LDD. In particular, the SLED achieved a maximum transconductance of 320 μS / μm when the effective channel length Leff = 0.17 μm.

[0108]

[Table 1]

[0109]

As is clear from the above, in the method for manufacturing a gate insulating field effect transistor of the present invention, since the silicide layer is formed, the sheet resistance between the semiconductor sidewall and the deep junction source / drain diffusion layer can be reduced. In addition, the performance of the device can be further improved.

Further, in the step of forming the source / drain diffusion layer having a deeper junction depth, the range at the time of implantation is reduced by the presence of the silicide layer on the surface of the substrate.
Channeling can be suppressed. As a result, the shallow junction of the deep junction source / drain diffusion layer is reduced to some extent, and the short channel effect is suppressed. At this time, even if the deep junction source / drain diffusion layer has a shallow junction to some extent,
Since the surface is silicided, deterioration of element performance due to an increase in sheet resistance and an increase in parasitic resistance can be suppressed. Further, by siliciding the semiconductor sidewall close to the gate electrode, the silicide layer can be brought close to the vicinity of the gate electrode, and the series resistance can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a cross-sectional structure of a semiconductor device to be manufactured by a forming process according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a process of forming a semiconductor device according to a first embodiment of the present invention.

FIG. 3 is a view showing a step of forming a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a view showing a step of forming a semiconductor device according to a third embodiment of the present invention.

FIG. 5 is a view showing a step of forming a semiconductor device according to a fourth embodiment of the present invention.

FIG. 6 is a view showing a step of forming a semiconductor device according to a fifth embodiment of the present invention.

FIG. 7 is a diagram showing characteristics of the insulated gate field effect transistor manufactured by the forming process of the fifth embodiment and the fourth embodiment.

FIG. 8 is a view showing a process of forming a semiconductor device according to a conventional technique.

FIG. 9 is a view illustrating a process of forming a semiconductor device according to another conventional technique.

[Explanation of symbols]

1, 101, 201, 301, 401 Si substrate 2, 102, 202, 302, 402 Gate insulating film 3, 103, 203, 303, 403 Gate electrode 4, 104, 204, 304, 404 First sidewall insulating film 5,205 Second sidewall insulating film 7,107,207,307,407 Semiconductor film 8,108,208,308,408 Semiconductor sidewall 10,10 ', 110,110', 210,210 ', 31
0,310 ', 410, 410' Local shallow junction source / drain diffusion layers 11, 11 ', 111, 111', 211, 211 ', 31
1, 311 ', 411, 411' deep junction source / drain diffusion layer 16, 305, 405 interlayer insulating film 312 refractory metal film 313 silicide layer

Claims (4)

[Claims] A gate electrode provided on a semiconductor substrate via a gate insulating film; a sidewall insulating film provided on both side surfaces of the gate electrode; and a source / drain diffusion layer on both sides of the gate electrode. A semiconductor sidewall on a side surface of the sidewall insulating film; the semiconductor sidewall being a part of a source / drain diffusion layer; and a silicide layer on a surface of the semiconductor sidewall. Transistor. 2. The semiconductor device according to claim 1, further comprising a source / drain diffusion layer having a deeper junction depth on both sides of the semiconductor sidewall, the source / drain diffusion layer having a deeper junction depth. The insulated gate field effect transistor according to claim 1, further comprising a layer. A step of forming a gate electrode provided on the semiconductor substrate via a gate insulating film; a step of forming a sidewall insulating film on both side surfaces of the gate electrode; A step of forming a semiconductor sidewall film on the side surface of the sidewall insulating film by etching, and a step of depositing a high melting point metal film and silicidizing the surface of the semiconductor sidewall film by heat treatment are sequentially performed. A method for manufacturing an insulated gate field effect transistor, comprising: 4. A step of forming a gate electrode provided on a semiconductor substrate with a gate insulating film interposed therebetween, a step of forming sidewall insulating films on both side surfaces of the gate electrode, and depositing the semiconductor film. Forming a semiconductor sidewall film on the side surface of the sidewall insulating film by etching; forming a source / drain diffusion layer having a deeper junction depth on both sides of the semiconductor sidewall so as to be continuous with the source / drain diffusion layer. A step of depositing a refractory metal film and heat-treating the surface of the semiconductor sidewall film and the surface of the source / drain diffusion layer having a deeper junction depth to form a silicide. A method for manufacturing a field effect transistor.