JP2822593B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device.

2. Description of the Related Art As a conventional method for manufacturing a semiconductor device, for example,
No. 54-44482 (Japanese Patent Application No. 52-110724). FIG. 4 is a sectional view showing the structure of an N-channel MOS transistor using this conventional method for manufacturing a semiconductor device. Polycrystalline silicon 3 is deposited on a P-type silicon substrate 1 via a gate oxide film 2, and the polycrystalline silicon 3 and the gate oxide film 2 are etched using a photoresist as a mask. Next, phosphorus ions or arsenic ions are added to the substrate 1.
The low-concentration diffusion layers 6 and 7 are formed by injecting into the surface. After that, an oxide film is deposited on the surface of the semiconductor device, and the oxide film is etched using an etch-back method to form sidewalls 10 and 11. Next, arsenic ions are implanted into the substrate surface,
The drain diffusion layers 12 and 13 are formed and completed. In this conventional semiconductor device, since the electric field near the source / drain of the MOS transistor is reduced by the low concentration diffusion layer, injection of holes or electrons into the gate oxide film is suppressed, and the transistor due to hot carriers is reduced. Deterioration of characteristics is reduced.

Another conventional method for manufacturing a semiconductor device is disclosed in, for example, Japanese Patent Application Laid-Open No. 61-242468. FIG. 5 is a sectional view showing the structure of an N-channel MOS transistor using the conventional method for manufacturing a semiconductor device. Polycrystalline silicon 3 on a P-type silicon substrate 1 via a gate oxide film 2
Is deposited, and the polysilicon 3 and the gate oxide film 2 are etched using a photoresist as a mask. Next, phosphorus ions or arsenic ions are implanted under the gate by using a large-angle ion implantation to form low-concentration diffusion layers 6 and 7. Thereafter, arsenic ions are implanted into the surface of the semiconductor substrate to form source / drain diffusion layers 10 and 11, thereby completing the process. In the conventional semiconductor device configured as described above, the low concentration diffusion layer 6,
When 7 overlaps the gate, the electric field near the source / drain is further reduced than in the first conventional example, and the reliability of hot carriers is improved. Further, since the low-concentration diffusion layers 6 and 7 are formed under the gate, the gate length is substantially shortened, so that the driving force of the transistor is increased.

However, in the configuration described above, in order to increase the penetration of the low-concentration diffusion layer under the gate and increase the reliability of the hot carrier, the injection angle is further increased,
Although it is necessary to increase the implantation energy, the former is difficult in a highly integrated LSI, and the latter has a problem that the damage to the gate oxide film is increased.

In view of the foregoing, an object of the present invention is to provide a method of manufacturing a semiconductor device that can easily control the amount of a low-concentration diffusion layer entering under a gate by using a conventional process technology.

Means for Solving the Problems The present invention is to deposit a gate electrode film on a semiconductor substrate via a gate oxide film, selectively etch the gate electrode film, the oxide film and the semiconductor substrate, the etching step Forming a low-concentration diffusion layer on the side wall of the projection of the semiconductor substrate by performing tilted ion implantation on the side wall of the projection of the semiconductor substrate to be formed; and forming a coating on the side wall of the projection. The source / drain diffusion layer is formed by ion implantation substantially perpendicular to the semiconductor substrate.

According to the present invention, a low-concentration diffusion layer is formed directly under a gate, not through a plane portion of a silicon substrate, in order to perform ion implantation on a side surface of a projection formed by etching a silicon substrate. Can be formed.

Embodiment (Reference Example) FIG. 1 is a process sectional view showing a method for manufacturing an N-channel MOS transistor. In FIG. 1A, a 10-nm-thick gate oxide film 2 is formed on the surface of a P-type silicon substrate 1 by using dry oxidation or wet oxidation. Next, polycrystalline silicon 3 having a thickness of 300 nm is deposited using a known vapor deposition method.

In FIG. 1 (b), polycrystalline silicon 3, gate oxide film 2 and silicon substrate 1 are formed using photoresist 4 as a mask.
Is selectively etched.

In FIG. 1C, a protective oxide film 5 having a thickness of 30 nm is formed on the surface of the semiconductor device by using dry oxidation or wet oxidation. Next, phosphorus ions are implanted into the side surfaces and the etching surface of the convex portion of the silicon substrate 1 at an implantation energy of 30 KeV and a dose of 2 × 10 ¹³ cm ⁻² at an angle of 70 ° with respect to the silicon substrate surface. The concentration diffusion layers 6 and 7 are formed. The implantation is performed twice so that both side surfaces of the convex portion of the silicon substrate are uniform.

In FIG. 1 (d), arsenic ions are implanted into the surface of the silicon substrate 1 almost perpendicularly to the surface of the silicon substrate 1 under the conditions of an implantation energy of 40 KeV and a dose of 6 × 10 ¹⁵ cm ^−2. -Complete by forming drain diffusions 12 and 13.

FIG. 2 is a schematic view showing the process of FIG. 1 (c) and the state of implanted ions entering just below the gate according to the conventional technology (LATID). FIG. 2A shows by arrows the phosphorus ions (P ions) entering the silicon substrate 1 in the step of FIG. 1C. FIG. 3B shows the state of phosphorus ions entering the silicon substrate 1 by the conventional technology (LATID) indicated by arrows. FIGS. 3A and 3B show that the amount of phosphorus ions entering the low concentration diffusion layer region A is the first. 1C is much more numerous than the LATID because it can be performed without interposing the plane of the silicon substrate 1.

In the N-channel MOS transistor configured as described above, the gate overlap structure can be formed with relatively low implantation energy because the low concentration diffusion layers 6 and 7 are formed on the side surfaces of the convex portion of the silicon substrate. There is no need to perform large angle ion implantation as in the case of technology LATID. Further, the amount of the low-concentration diffusion layer entering under the gate can be easily controlled by the implantation energy.

(Embodiment 1) FIG. 3 shows an N-channel MO according to a first embodiment of the present invention.
FIG. 4 is a process cross-sectional view illustrating a method for manufacturing an S-type transistor,
1A and 1B are sequential diagrams of steps subsequent to the steps of FIGS. 1A to 1C. In FIG. 3A, an implantation energy of 30 KeV and a dose of 1 × 10 ⁻¹⁴ are applied to the surface of the silicon substrate 1.
Under the condition of cm ⁻² , arsenic ions are implanted perpendicularly to the silicon substrate 1 to form medium concentration diffusion layers 8 and 9.

In FIG. 3 (b), an oxide film formed by depositing the surface of the semiconductor device to a thickness of 100 nm by using a well-known vapor deposition method is etched to reach the protective oxide film 5 by using an etch-back method. The side walls 10 and 11 are formed. Next, an implantation energy of 40 KeV and a dose of 6 × 1 were applied to the surface of the silicon substrate 1.
Under the condition of ¹⁵ cm ⁻² , arsenic ions are implanted substantially perpendicularly to the silicon substrate 1 to form source / drain diffusion layers 12 and 13 and complete the process.

In the N-channel MOS transistor of the present embodiment configured as described above, since the low-concentration diffusion layers 6 and 7 are formed on the side surfaces of the convex portion of the silicon substrate, the gate overlap structure is formed with relatively low implantation energy. Can be formed and
There is no need to perform large angle ion implantation as in the case of LATID. Further, the amount of the low-concentration diffusion layer entering under the gate can be easily controlled by the implantation energy. or,
Since the medium-concentration diffusion layers 8, 9 are formed between the low-concentration diffusion layers 6, 7 and the source / drain diffusion layers 12, 13, electric field concentration near the source / drain below the gate can be reduced. Hot carrier reliability is improved.

As described above, according to the present invention, the overlap structure can be easily formed by using the conventional process technology, and the amount of the low-concentration diffusion layer penetrating under the gate can be changed by the implantation energy. Easy to control. Therefore, the reliability of hot carriers of the transistor can be easily improved, and the practical effect is large.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of an N-channel MOS transistor,
FIG. 2 is a schematic view showing the process of FIG. 1 (c) and the state of implanted ions entering just below the gate according to the conventional technique (LATID), and FIG. 3 is an N-channel according to the first embodiment of the present invention.
FIG. 4 shows a manufacturing process of a MOS type transistor.
FIG. 5 is a structural sectional view of an N-channel MOS transistor having an LDD structure, and FIG. 5 is a structural sectional view of an N-channel MOS transistor having a gate overlap structure (LATID), which is one of conventional examples. 1 ... P-type silicon substrate, 2 ... Gate oxide film, 3 ...
Polycrystalline silicon, 4 ... Photoresist, 5 ... Protective oxide film, 6,7 ... Low concentration diffusion layer, 8,9 ... Medium concentration diffusion layer, 1
0,11: Side wall, 12,13: Source / drain diffusion layer.

Claims (1)

(57) [Claims] A step of depositing a gate electrode film on a semiconductor substrate via a gate oxide film; a step of selectively etching the gate electrode film, the oxide film and the semiconductor substrate; and the step of etching. Forming a low-concentration diffusion layer on the side wall of the projection of the semiconductor substrate by performing tilted ion implantation on the side wall of the projection of the semiconductor substrate, and performing ion implantation perpendicular to the surface of the semiconductor substrate. Forming a medium-concentration diffusion layer on the surface of the semiconductor substrate, forming a sidewall on a side wall of a convex portion of the semiconductor substrate, and performing ion implantation perpendicular to the surface of the semiconductor substrate. Forming a source / drain diffusion layer on the surface of the substrate.