JPH0414260A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To easily control the permeation amount of a low concentration diffusion layer into the lower part of a gate, by a method wherein, in order to implant ions in the side surface of a protruding part formed by etching a silicon substrate, a low concentration layer is directly formed under the gate without interposing the silicon substrate. CONSTITUTION:Polycrystalline silicon 3, a gate oxide film 2, and a silicon substrate 1 are etched by using photo resist 4 as a mask. A protecting oxide film 5 of 30nm in thickness is formed on the surface of a semiconductor device by dry oxidation or wet oxidation. Phosphorus ions are implanted in the side surface and the etching surface of the protruding part of the silicon substrate 1 under the following conditions, thereby forming low concentration diffusion layers 6, 7; implantation energy is 30keV, dosage is 2X10<13>cm<-2>, and incident angle to the silicon substrate surface is 70 deg.. In order to make both side surfaces of the protruding part of the silicon substrate uniform, twice rotation implantation is performed. Arsenic ions are implanted vertically to the silicon substrate 1 under the conditions of 40keV implantation energy and 6X10<15>cm<-2> dosage, thereby forming a source diffusion layer 12 and a drain diffusion layer 13 and completing a device.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a method of manufacturing a semiconductor device.

2. Description of the Related Art A conventional method for manufacturing a semiconductor device is disclosed in Japanese Patent Application Laid-open No. 110724/1983.

Figure 4 uses this conventional semiconductor device manufacturing method? Q
1 shows a cross-sectional view of the structure of an N-channel MO3 type transistor. Polycrystalline polysilicon 3 is deposited on P-type silicon substrate 1 with gate oxide film 2 interposed therebetween, and polycrystalline polysilicon 3 and gate oxide film 2 are etched using photoresist as a mask.

Next, phosphorus ions or arsenic ions are implanted into the surface of the substrate 1 to form low concentration diffusion layers 6 and 7. Thereafter, an oxide film is deposited on the surface of the semiconductor device, and the oxide film is etched using an etch-back method to form sidewalls 10 and 11. Next, arsenic ions are implanted into the substrate surface to form source and drain diffusion layers 12 and 13, thereby completing the process. In this conventional semiconductor device, the low concentration diffusion layer relaxes the electric field near the source and drain of the MOS transistor, suppressing the injection of holes or electrons into the gate oxide film, and deteriorating the transistor characteristics due to hot carriers. decreases.

Another conventional method for manufacturing a semiconductor device is shown in Japanese Unexamined Patent Publication No. 61-242468. FIG. 5 shows fQ, N using this conventional method for manufacturing a semiconductor device.
1 shows a structural cross-sectional view of a channel, MOS type transistor. Polycrystalline polysilicon 3 is deposited on P-type silicon substrate 1 with gate oxide film 2 interposed therebetween, and polycrystalline polysilicon 3 and gate oxide film 2 are etched using photoresist as a mask. Next, phosphorus ions or arsenic ions are implanted under the gate using large angle ion implantation to form low concentration diffusion layers 6 and 7. Thereafter, arsenic ions are implanted into the surface of the semiconductor substrate to form source and drain diffusion layers 10 and 11 to complete the process. In the conventional semiconductor device configured as described above, since the low concentration diffusion layer 6.7 overlaps the gate, the electric field near the source and drain is further relaxed than in the first conventional example, thereby improving the reliability of hot carriers. will improve. Furthermore, since the low concentration diffusion layers 6 and 7 are formed under the gate, the actual gate length is shortened, so that the driving power of the transistor is increased.

Problems to be Solved by the Invention However, in the above structure, in order to increase the penetration of the low-concentration diffusion layer under the gate and increase the reliability of hot carriers (Table 1), it is necessary to further increase the injection angle and increase the injection energy. (The former is difficult in highly integrated LSIs, and the latter has the problem of increasing damage to the gate oxide film.The present invention takes into account these points and uses conventional process technology. death\
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can easily control the amount of a low concentration diffusion layer that penetrates under a gate.

Means for Solving the Problems The present invention (Table 1) Depositing a gate electrode metal on a semiconductor substrate via a gate oxide film; A low concentration diffusion layer is formed on the side wall of the convex portion of the semiconductor substrate by performing oblique ion implantation into the side wall of the convex portion of the semiconductor substrate.

According to the present invention, with the above-described structure, a low concentration diffusion layer can be formed directly under the gate without using the silicon substrate to perform ion implantation on the side surface of the convex portion formed by etching the silicon substrate. .

Embodiment (Example 1) FIG. 1 shows the N-channel M in the first embodiment of the present invention.
FIG. 3 is a process cross-sectional view showing a method for manufacturing an O3 type transistor. In FIG. 1(a), a 10 nm thick gate oxide film 2 is formed on the surface of an L P type silicon substrate 1 using dry oxidation or wet oxidation.

Next, a 300 nm thick polycrystalline silicon film 3 is deposited using a well-known vapor phase growth method.

In FIG. 1(b), using the photoresist 4 as a mask, the polycrystalline silicon 3, the gate oxide film 2, and the silicon substrate 1 are
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In FIG. 1C, a 30 nm thick protective oxide film 5 is formed on the surface of the semiconductor device using dry oxidation or wet oxidation. Second implantation energy: 30KeV, dose: 2X10"
Under the condition of cm-2, phosphorus ions are implanted at an angle of 70° to the silicon substrate surface to form low concentration diffusion layers 6 and 7. The implantation is performed twice so that both sides of the convex portion of the silicon substrate are uniform.

In Fig. 1(d), the implantation energy is 40 KeV and the dose is 6X 10" cm-2 on the surface of the silicon substrate 1.
Under these conditions, arsenic ions are implanted vertically into the silicon substrate 1 to form source and drain diffusion layers 11 and 12, and the process is completed.

FIG. 2 is a schematic diagram showing the state of implanted ions entering directly under the gate according to the present invention and the prior art (LATID).

In FIG. 3(a), arrows indicate how phosphorus ions enter the silicon substrate 1 according to the present invention. The figure (b) shows the conventional technology (L
Arrows indicate how phosphorus ions enter the silicon substrate 1 due to ATID. From (a) and (b) in the same figure, the amount of phosphorus ions entering the low concentration diffusion layer region A is smaller in the present invention.
Compared to ATID, much more can be done without using the silicon substrate 1. In the N-channel MOS transistor of this embodiment configured as above, the two-gate overlap structure is formed by relatively low implantation energy in order to form the low concentration diffusion layers 6 and 7 on the sides of the convex portion of the silicon substrate. The amount of penetration of the low concentration diffusion layer under the gate can be easily controlled by the implantation energy.

(Embodiment 2) FIG. 3 shows an N-channel MO in the second embodiment of the present invention.
FIG. 3 is a process cross-sectional view showing a method for manufacturing an S-type transistor.

After the steps in FIGS. 1(a) to (c), in FIG. 3(a), the injection energy is 30 KeV to the surface of the silicon substrate 1.
, arsenic ions are implanted perpendicularly to the silicon substrate 1 under the conditions of a dose of lXl014 cm-2 to form medium concentration diffusion layers 8 and 9.

In FIG. 3(b), the oxide film deposited on the surface of the semiconductor device to a thickness of 1100 nm using the well-known vapor phase growth method is etched down to the protective oxide film 5 using the etch-back method. to, form 11. Next, the surface of the silicon substrate 1 (Mi implantation energy 40Kev,
Arsenic ions are implanted perpendicularly into the silicon substrate 1 at a dose of 6XlO"cm-" to form source and drain diffusion layers 12 and 13, and the process is completed.

In the N-channel MOS transistor of this embodiment configured as described above, in order to form the low concentration diffusion layer 6.7 on the side surface of the convex portion of the silicon substrate, a gate-over-wrap structure is formed with relatively low implantation energy. This eliminates the need for large-angle ion implantation. Furthermore, the amount of penetration of the low concentration diffusion layer under the gate can be easily controlled by the implantation energy. In addition, since the medium concentration diffusion layers 8 and 9 are formed between the low concentration diffusion layer 6.7 and the drain diffusion layer 12.13, the electric field concentration near the drain under the gate can be alleviated. As described in detail, according to the present invention, a gate overlap structure can be easily formed by using conventional process technology, and a low concentration diffusion layer can be formed under the gate. The amount of penetration L can be easily controlled by the injection energy. The hot carrier reliability of transistors can be easily improved, and its practical effects are significant.

[Brief explanation of the drawing]

FIG. 1 shows an N-channel MO in the first embodiment of the present invention.
Figure 2 is a schematic diagram showing the state of implanted ions entering directly under the gate according to the present invention and the conventional technology (LATID). Figure 3 is an N-channel MOS transistor according to the second embodiment of the present invention. Figure 4 is a structural cross-sectional view of an N-channel MOS transistor with an LDD structure, which is one of the conventional examples. Figure 5: An N-channel MOS transistor with a gate overlap structure (LATrD), which is one of the conventional examples. FIG. 2 is a structural cross-sectional view of a transistor. 1...P-type silicon substrate, 2...gate oxide film
3... Polycrystalline polysilicon, 4... Photoresist, 5... Protective oxide film 6, 7... Low concentration diffusion layer 8, 9... Medium concentration diffusion #10.11... Side Wall 11.12... Name of agent for source/drain diffusion layer Patent attorney Shigetaka Awano Figure 1

Claims (2)

[Claims] (1) A step of depositing gate electrode metal on a semiconductor substrate via a gate oxide film, and using a photoresist as a mask.
By etching the gate electrode, the oxide film, and the semiconductor substrate, and performing tilted ion implantation on the sidewalls of the protrusions of the semiconductor substrate formed by the etching process, the sidewalls of the protrusions of the semiconductor substrate are etched. a step of forming a low concentration diffusion layer; and a step of forming a source/drain diffusion layer on the surface of the semiconductor substrate by performing ion implantation perpendicularly to the surface of the semiconductor substrate,
1. A method of manufacturing a semiconductor device, comprising forming a type transistor. (2) A step of depositing gate electrode metal on the semiconductor substrate via a gate oxide film, and using a photoresist as a mask.
By etching the gate electrode, the oxide film, and the semiconductor substrate, and performing tilted ion implantation on the sidewalls of the protrusions of the semiconductor substrate formed by the etching process, the sidewalls of the protrusions of the semiconductor substrate are etched. forming a low concentration diffusion layer; forming a medium concentration diffusion layer on the surface of the semiconductor substrate by performing ion implantation perpendicular to the surface of the semiconductor substrate; and forming a source/drain diffusion layer on the surface of the semiconductor substrate by performing ion implantation perpendicularly to the surface of the semiconductor substrate, forming a MOS transistor. A method for manufacturing a semiconductor device.