JPH0823035A - Semiconductor element and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve an information holding characteristic of DRAM elements by realizing element separation corresponding to refining and preventing an increase in electric field strength. CONSTITUTION:This semiconductor element has a structure (a) having a selective oxide film for element separation where a side near an active region 3 on a silicon substrate 1 is of a thin thickness t1 and a side far from it is of a thick thickness t2. The semiconductor element has also a structure (b) where the depth from the substrate surface of a high-concentration embedded layer 4 under the selective oxide film 2 has two kinds of d1, d2, besides the high- concentration embedded layer 4 near an active region where the source/drain electrodes 16 and the gate electrodes 17 are to be formed, has a deep depth d1 from the substrate surface. Further, the semiconductor device has a structure (c) where a layer under a thin film on the side near the active region of the selective oxide film 2 is a high-concentration embedded layer 5 of relatively low concentration and a layer under a thick film far from the active region of the selective oxide film 2 has a high-concentration embedded layer 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device suitable for a DRAM device having improved information retention characteristics so as to cope with miniaturization and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a device isolation region of a semiconductor device, for example, a device isolation region of a DRAM device has been disclosed in Japanese Patent Laid-Open No. 3-1556.
As disclosed in Japanese Patent Laid-Open No. 64, it was composed of a selective oxide film having one kind of thickness. The high-density buried layer in the element isolation region is described in Tsukamoto et al. “Achieving performance after DRAM / 16 Mbit while reducing two masks” (Nikkei Microdevice, December 1992, pages 110 to 116). As described above, the impurity was ion-implanted through the selective oxide film having one film thickness. At this time, the impurity concentration and depth of the high-concentration buried layer are controlled so that the parasitic MOS transistor operation does not occur under the selective oxide film and the source and drain do not punch through in the active region.

[0003]

However, in the case of the memory cell having the stacked structure as described in the above-mentioned Japanese Patent Laid-Open No. 3-155664, contact processing is required to make contact between the storage electrode and the substrate. However, due to the misalignment of the contact processing, the edge of the selective oxide film may be eroded and the distance between the junction and the high-concentration buried layer may become extremely short. As a result, the electric field strength in the depletion layer of the source / drain junction is further increased, and the junction leak current (specifically, avalanche current or Zener current) that depends on the electric field is rapidly increased, and the information retention time is shortened. There was a problem that became.

Further, in the latter case of the aforementioned DRAM element in which the element isolation region is formed by a selective oxide film having one kind of thickness, the depth of the high-concentration buried layer reflects the shape of the selective oxide film. Since the source / drain region has a structure that is relatively close to the high-concentration buried layer because it changes continuously at the element separation edge, the depletion layer of the source / drain junction becomes very close as the device becomes finer. The electric field strength was high. As a result, the electric field-dependent junction leak current becomes large, and it becomes difficult to keep the information retention time long. Furthermore, variations in the junction leak current increase due to variations in the depth of the source / drain junctions and variations in the concentration and depth of the high-concentration buried layer, which in turn increases the variations in the information retention time, which can be reproduced in DRAM device manufacturing. It was difficult to secure sex.

The influence of the electric field strength as described above becomes a serious problem for semiconductor devices as miniaturization progresses, and becomes a major impediment factor for manufacturing highly integrated DRAM devices. Therefore, there is a demand for a DRAM device having a structure capable of coping with miniaturization and preventing an increase in electric field strength, and a manufacturing method thereof.

Therefore, an object of the present invention is to solve the above-mentioned conventional problems and realize element isolation corresponding to miniaturization to realize DR.
It is an object of the present invention to provide a semiconductor element capable of improving the information holding characteristic suitable for an AM element and a method for manufacturing the same.

[0007]

In order to achieve the above object, a semiconductor element according to the present invention is a semiconductor element having a selective oxide film for element isolation, wherein the selective oxide film has at least two kinds of film thicknesses. In addition, it is characterized in that the film thickness on the side close to the active region where the source / drain region and the gate region of the MOS transistor are formed is thin. That is, if described with reference to FIG. 1 (a), selective oxide film 2 for element isolation formed in the surface of the silicon substrate 1, the film thickness of the thin portion and the thick portion of t ₂ of t ₁ of at least 2 It is a semiconductor element having a kind and a structure having a thin film thickness in a portion closer to an active region 3 where a source / drain region and a gate region of a MOS transistor are formed.

Further, the semiconductor element according to the present invention is a semiconductor element element having a high-concentration buried layer and a selective oxide film for element isolation, and the portion below the selective oxide film of the high-concentration buried layer is from the substrate surface. It is preferable that the depth is at least two kinds and the depth on the side close to the active region where the source / drain region and the gate region of the MOS transistor are formed is deep. That is, referring to FIG. 1B, a high-concentration buried layer 4 having at least two kinds of depths d ₁ and d ₂ is formed under the selective oxide film 2, and the selective oxide film 2 is formed. A semiconductor element A having a structure in which the depth d ₁ from the surface of the substrate 1 under the active region 3 under 2 is deeper. 1 (a) to 1 (c), the same reference numerals indicate the same components, and reference numeral 17
Is a gate electrode, 40 is a gate oxide film, and 41 is a low concentration source / drain region.

In the above semiconductor device, it is preferable that the high-concentration buried layer has a conductivity type opposite to that of the source / drain regions of the MOS transistor. In particular, the semiconductor element is preferably a DRAM element.

Alternatively, the semiconductor element according to the present invention is a semiconductor element having a high-concentration buried layer and a selective oxide film for element isolation, wherein the selective oxide film has at least two types of film thickness, and the source of the MOS transistor is / The thickness of the side close to the active region where the drain region and the gate region are formed is thin, and the portion below the selective oxide film of the high-concentration buried layer is the depth of the high-concentration buried layer from the substrate surface. May have at least two types of depths, and the concentration of the high-concentration buried layer may be lower on the thin side than on the thick side of the selective oxide film. That is, to explain with reference to FIG. 1C, below the selective oxide film 2 having at least two kinds of film thickness,
It has at least two types of high-concentration buried layers 5 and 6, and the high-concentration buried layer 5 under the thin selective oxide film 2 closer to the active region 3 side has a low concentration and is separated from the active region 3. The semiconductor element B has a structure in which the high-concentration buried layer 6 below the thick selective oxide film 2 has a high concentration.

In the method of manufacturing a semiconductor device according to the present invention, in order to form a selective oxide film for element isolation, a first selective oxidation is performed by using a silicon nitride film as a mask and a selective oxidation of a first thickness is performed. Step 1 of forming a film, and then Step 2 of forming a silicon nitride film on the sidewall of the silicon nitride film
And a step 3 in which the second selective oxidation is performed again using the silicon nitride film as a mask to form a selective oxide film having a second thickness which is thicker than the first thickness, and the steps 2 and 3 are performed. It is characterized in that it is performed at least once in order.

It is also preferable to have a step of forming a high-concentration buried layer by implanting impurity ions through a selective oxide film having at least two types of film thickness formed by the method for manufacturing a semiconductor element. Furthermore, the impurity ion implantation can be performed with at least two types of implantation energy and at least two types of implantation amounts. In particular, in the method of manufacturing a semiconductor device described above, the semiconductor device is a DRAM.
It is suitable as an element.

That is, the method of manufacturing a semiconductor device according to the present invention will be described below with reference to FIG. As shown in FIG. 3A, first, a thin silicon oxide film 8 is formed on the surface of the silicon substrate 7, a silicon nitride film 9 for selective oxidation is deposited, and after this is processed, the silicon nitride film 9 is removed. Using the mask as a mask, the selective oxide film 10 having a small thickness t ₁ , that is, the first thickness is formed, and then, as shown in FIG. 2B, a silicon nitride film 11 is formed on the side wall of the silicon nitride film 9. Then, as shown in FIG. 3C, the silicon nitride films 9 and 11 are used as a mask to form a thick specification of the film thickness t ₂ , that is, the selective oxide film 12 having the second thickness. Here, by repeating the steps (b) and (c) in the process order at least once, it is possible to form the selective oxide film having two or more kinds of film thickness. Further, as shown in FIG. 3D, after removing the silicon nitride films 9 and 11, at least two kinds of selective oxide films 10 having film thicknesses t ₁ and t ₂ are formed as shown in FIG. 1
Impurity ion implantation is performed through 2 to form the high-concentration buried layer 13 used for the former semiconductor element A.
At this time, as shown in FIG. 3, if at least two types of implantation energy are used to implant impurity ions through at least two types of selective oxide films 10 and 12 with at least two types of implantation energy, The latter semiconductor device B
The high-concentration buried layers 14 and 15 used for the can be formed. next,
As shown in FIG. 2F, the gate oxide film 21, the gate electrode 22, the source / drain layer 24, the silicon oxide film 2
3, 25, and source / drain layers 26 are formed to form MO
After manufacturing the S-transistor, for example, a DRAM element may be manufactured according to a normal manufacturing process.

[0014]

According to the semiconductor element of the present invention, the selective oxide film has at least two kinds of film thickness, and the film thickness of the selective oxide film is smaller on the side closer to the active region, and the selective oxide film is more distant from the active region. By making the thickness of the selective oxide film thick, element isolation performance can be secured by the thick selective oxide film portion, and the reduction of the active area due to the extension of the bird's beak during the selective oxidation is prevented by the thin selective oxide film portion. it can.

In the portion formed under the selective oxide film of the high concentration buried layer, the depth of the high concentration buried layer is 2 from the substrate surface.
There are more than one type, and the source / drain layer formed in the active region and the high-concentration buried region are formed by forming the depth from the substrate deeper on the side closer to the active region and shallower on the part farther from the active region. Since the distance from the layer is large, the electric field strength of the depletion layer of the junction can be reduced, and since the high concentration portion of the buried layer contacts under the thick selective oxide film, the parasitic MOS can be made difficult to operate.

Further, there are two or more high-concentration buried layers under the selective oxide film having two or more kinds of film thickness, and the concentration of the high-concentration buried layer is under the thin selective oxide film near the active region. Is relatively low, and the high-concentration buried layer under the thick selective oxide film on the side away from the active region has a high concentration. Is low, the electric field strength of the depletion layer formed between the source / drain layers can be kept low, and the high-concentration buried layer under the thick selective oxide film has a high concentration to prevent parasitic MOS operation. Ensure element isolation performance. The high-concentration buried layer under the thick selective oxide film is set to a concentration such that the source and drain are not electrically connected even if a voltage is applied to the gate electrode wired on the thin selective oxide film. There is a need.

The semiconductor device having the above structure can simultaneously promote miniaturization, low electric field, and improvement of parasitic device operation resistance. In particular, this feature is useful for improving the information retention characteristics of the DRAM device.

According to the method of manufacturing a semiconductor device of the present invention, the first selective oxidation is performed by using the silicon nitride film as a mask to form the selective oxide film having the first thickness, and then the above step is performed. Step 2 of forming a silicon nitride film on the side wall of the silicon nitride film, and step of forming a selective oxide film of a second thickness thicker than the first thickness by performing second selective oxidation again using the silicon nitride film as a mask. 3, the step 2 and the step 3 are performed at least once in the order of the steps, so that the selective oxidation has at least two kinds of film thicknesses in a self-aligning manner and has a small film thickness on the side close to the active region. A film can be formed.

Further, by including a step of implanting impurity ions through a selective oxide film having at least two kinds of film thickness formed by the above-mentioned method for manufacturing a semiconductor element to form a high-concentration buried layer, the selective oxide film is formed below the selective oxide film. It is possible to form a high-concentration buried layer that has at least two types of depths from the surface of the substrate and that has a depth deeper on the side closer to the active region and is shallower in a portion distant from the active region in a self-aligned manner.

Furthermore, by performing the above-described impurity ion implantation with at least two types of implantation energy and at least two types of implantation amounts, a relatively low concentration buried layer is formed under the thin selective oxide film near the active region. A high-concentration buried layer can be formed in a self-aligned manner under the selective oxide film apart from the active region.

As described above, according to the method of manufacturing a semiconductor device of the present invention, a high performance DRAM device can be manufactured by simple steps. This is because as the miniaturization progresses,
The element structure and the manufacturing method exhibit the effect.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described in detail below with reference to the accompanying drawings.

<Embodiment 1> FIG. 2 is a view showing an embodiment of a method of manufacturing a semiconductor device according to the present invention, in which (a)-
(F) is sectional drawing which showed the main manufacturing process in order of process.
First, a method of manufacturing a selective oxide film having a plurality of film thicknesses will be described with reference to FIG.

As shown in FIG. 2A, the boron concentration is 5
A silicon oxide film 8 having a thickness of 15 nm is formed on the surface of the p-type silicon substrate 7 having a (100) plane orientation at a ^density of × 10 ¹⁶ cm ^-3 by a thermal oxidation method, and then a chemical vapor deposition method
A silicon nitride film 9 having a thickness of 50 nm was deposited. Here, after the silicon nitride film 9 is processed by a normal photo-etching process, a silicon oxide film having a film thickness t ₁ of 300 nm, that is, a selective oxide film 10 is formed by a selective oxidation method in which the silicon nitride film 9 is used as a mask for oxidation. did.

Next, as shown in FIG. 2B, a 100 nm-thick silicon nitride film 11 is deposited by chemical vapor deposition, and anisotropic dry etching is performed to etch the film thickness (in this case). , 100 nm) and processed so that the silicon nitride film 11 remains only on the side wall of the silicon nitride film 9.

After that, as shown in FIG. 2C, the selective oxidation film 10 having a thickness of 300 nm is again formed by the selective oxidation method.
Was further oxidized to form a silicon oxide film having a thickness t ₂ of 400 nm, that is, a selective oxide film 12. In addition,
By repeating FIG. 2B and FIG. 2C, a selective oxide film having two or more kinds of film thickness can be formed. In this way, the selective oxide film is divided into a thin portion 10 and a thick portion 12,
In addition, since the thin portion is on the active region side, the reduction of the active region due to the elongation of the bird's beak can be reduced as compared with the conventional case where one kind of thick selective oxide film is formed from the beginning.

After that, as shown in FIG. 2D, the silicon nitride films 9 and 11 were removed by etching in hot phosphoric acid.
Here, an example of a plan view at that time is shown in FIG. Reference numeral 18 is an active region in which a source / drain region and a gate region of the MOS transistor are formed, and is a region where the surface of the silicon substrate is exposed. The arrangement of the selective oxide film 10 having a film thickness t ₁ of 300 nm near the active region 18 and the selective oxide film 12 having a film thickness t ₂ of 400 nm near the active region 18 is as shown in FIG. ing.

Next, as shown in FIG. 2 (e), boron ions are accelerated to 200 keV, ion implantation of 1 × 10 ¹³ cm ^-2 is performed, and boron is electrically treated by heat treatment at 1000 ° C. for 10 minutes. After activation to form the high-concentration buried layer 13, the 15 nm silicon oxide film 8 was removed.

Further, in FIG. 2F, a 10 nm silicon oxide film 21 to be a gate oxide film is formed by using a thermal oxidation method.
After the formation of phosphorus, the phosphorus content is 2 × 10 ²⁰ cm ⁻³ by the chemical vapor deposition method.
The introduced polycrystalline silicon film 2 having a thickness of 200 nm
A silicon oxide film 23 having a thickness of 2 and 200 nm was deposited. Then, the silicon oxide film 23 and the polycrystalline silicon film 22 are processed by a normal photoetching process,
A gate electrode of the polycrystalline silicon film 22 having an upper portion covered with the silicon oxide film 23 was formed. Then, add phosphorus ions to 20
By accelerating to keV, ion implantation of 1 × 10 ¹⁴ cm ⁻² , and phosphorus being electrically activated by heat treatment at 1000 ° C. for 5 seconds, a low concentration n-type source / drain layer 24 so-called LDD (Lightly Doped) Drain) layer was formed. Next, after depositing a silicon oxide film having a thickness of 100 nm by the chemical vapor deposition method, etching is performed by a film thickness (100 nm in this case) by the anisotropic dry etching method to obtain the silicon oxide film 23 and the polycrystalline silicon. The processing was performed so that the silicon oxide film 25 remained only on the side surface of the film 22. Further, arsenic ions are accelerated to 25 keV and ion implantation of 1 × 10 ¹⁵ cm ⁻² is performed, and arsenic is electrically activated by a heat treatment at 1000 ° C. for 5 seconds, so that the n-type source / drain layer 2
6 was formed.

After that, as shown in the sectional view of FIG. 5, a DRAM element, that is, a DRAM memory cell was manufactured by the following steps. In FIG. 5, unlike in FIG. 2, the MOS is formed in one island separated by the selective oxide films 10 and 12.
A figure in which two transistors are formed is shown. First, a 100 nm-thickness silicon oxide film 27 was deposited by the chemical vapor deposition method, and the silicon oxide film 27 was processed by a normal photoetching process to open a contact hole. After that, by a chemical vapor deposition method, phosphorus is 2 × 10 ²⁰ c
A 400 nm-thick polycrystalline silicon film having m ⁻³ introduced therein was deposited, and this polycrystalline silicon film was processed by a normal photoetching process to form a storage electrode 28. Next, a silicon nitride film having a thickness of 5 nm was deposited by chemical vapor deposition, and thermal oxidation was performed at 900 ° C. for 20 minutes to form a capacitor insulating film 29 of a silicon oxynitride film. At this time, phosphorus is also diffused from the polycrystalline silicon film of the storage electrode 28 in the source / drain layer 26 formed by ion implantation of arsenic shown in FIG.
At the same time that an ohmic contact with the n-type source / drain layer 26a is formed. By thus forming the n-type source / drain layer 26a containing arsenic and phosphorus as impurities, the current driving capability of the MOS transistor of the DRAM memory cell is increased as compared with the case of the n-type source / drain layer containing only phosphorus.

After that, phosphorus is 2 × by a chemical vapor deposition method.
A 100 nm-thick polycrystalline silicon film having a thickness of 10 ²⁰ cm ⁻³ was deposited, and the polycrystalline silicon film and the capacitor insulating film 29 were processed by a normal photoetching process to form a plate electrode 30. Next, by a chemical vapor deposition method, a glass film 31 having a thickness of 400 nm and containing 16 mol% of phosphorus and 8 mol% of boron is deposited,
After heat treatment was performed at 900 ° C. for 10 minutes to flatten the glass film 31, the glass film 31 was processed by a normal photoetching process to open a contact hole.

Finally, 300 nm is formed by chemical vapor deposition.
A tungsten film having a thickness of 1 was deposited, and the tungsten film was processed by a normal photoetching process to form the bit wiring 32. After this, there is a wiring forming step, but since it is a normal step, it is omitted in the description of this embodiment.

In the DRAM device according to this embodiment manufactured as described above, the selective oxide film on the side close to the active region is thin and the side remote from the active region is thick, so that the active region due to the extension of the bird's beak during the selective oxidation is formed. Is suppressed, and since the distance between the source / drain layer and the high-concentration buried layer is increased, the electric field is alleviated, which is more suitable for device miniaturization than in the past. Furthermore, as a result of the reduction of the junction leakage current due to the relaxation of the electric field between the source / drain layer and the high-concentration buried layer, the information retention time of the DRAM element is the same as that of the conventional structure in which the selective oxide film is one type having a thickness of 400 nm. As compared with the case, the length could be increased to 3 to 5 times as shown in FIG. Note that FIG. 6 is a histogram of information retention time when the environmental temperature is constant at 70 ° C.
The distribution of the information holding time of the bit having the shortest information holding time of the M element is shown.

<Embodiment 2> Next, another embodiment of the semiconductor element and the manufacturing method thereof according to the present invention will be described. FIG. 7 is a sectional view showing the structure of the DRAM device according to the present embodiment. The manufacturing method of this DRAM element is the same up to the selective oxide film forming step shown in FIG. 2D of the manufacturing method of the first embodiment. That is, after a silicon oxide film 8 having a thickness of 15 nm is formed on a p-type silicon substrate 7, a silicon nitride film 9 is deposited and processed by a photoetching process,
This silicon nitride film 9 is used as a mask to perform oxidation to 300 nm
Forming a selective oxide film 10 having a thickness of. After that, a silicon nitride film is deposited again and anisotropic etching is performed to leave the silicon nitride film 11 only on the sidewalls of the silicon nitride film 9, and selective oxidation is performed again to form a selective oxide film 12 having a thickness of 400 nm. The process up to the steps of removing 9 and 11 is the same as that of the first embodiment.

After that, boron ions are accelerated to 150 keV, ion implantation of 1 × 10 ¹² cm ^-2 is performed, and boron ions are further accelerated to 200 keV to 5 × 10 ¹² cm.
After ion implantation of ^-2 , boron is heated at 1000 ° C for 1
Two kinds of high-concentration buried layers 33 and 34 were formed by being electrically activated by heat treatment for 0 minutes.

In the subsequent steps, the MOS transistor may be formed again in the same manner as in the first embodiment. However, in the present embodiment, the arsenic implantation performed in the first embodiment is not performed to form the n-type source / drain layer. this is,
During the arsenic ion implantation step, the silicon oxide film 25 formed on the side surface of the polycrystalline silicon film 22 is removed, so that the low concentration source / drain layer 24 and the high concentration source / drain layer 2 are removed.
It is suitable when strict accuracy is required such that the deviation from 6 becomes a problem. In this case, the n-type source / drain layer 19 is formed by phosphorus diffusion from the polycrystalline silicon film of the storage electrode 28, and the n-type diffusion layer 20 that makes ohmic contact with the bit line 32 is the contact hole of the glass film 31. After processing, phosphorous ions are accelerated to 60 keV and 5 × 1
After ion implantation of 0 ¹⁵ cm ^-2 , it was formed by heat treatment at 900 ° C. for 10 minutes.

The DRA produced in this way in this way
The M element has the same effect as that of the first embodiment, and further the DRAM
Since the high-concentration buried layer can be optimized for the information retention time of the element, FIG. 6 shows the results of Example 1 in comparison with the case of the conventional structure in which the thickness of the selective oxide film is 400 nm. Thus, it was possible to increase the length to 5 to 10 times.

The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above embodiments, and it is needless to say that various design changes can be made without departing from the spirit of the present invention. Therefore, for example, when applied to the selective oxide film and the high-concentration buried layer of the flash memory, the electric field between the source and the high-concentration buried layer to which the electric field is strongly applied at the time of erasing is relaxed to reduce the leak current of the source. Therefore, the erase operation can be surely performed.

[0039]

According to the present invention, by reducing the thickness of the selective oxide film near the active region side and increasing the film thickness away from the active region side, the reduction of the active region due to bird's beak can be prevented. it can.

Further, the thickness of the selective oxide film is made thinner at the portion close to the active region side and thicker at the distant side, and the portion under the selective oxide film from the substrate surface of the high-concentration buried layer is formed. By increasing the depth on the side close to the active region, it is effective for miniaturization of the semiconductor element, low electric field, and improvement of parasitic element operation resistance. In particular, by forming the concentration of the high-concentration buried layer below the selective oxide film lower on the thin side than on the thick side of the selective oxide film, miniaturization of semiconductor elements, low electric field, and improvement of parasitic element resistance can be achieved. It can be further improved.

When the present invention is applied to a DRAM device, it is effective in improving the miniaturization, the low electric field, and the operation resistance of the parasitic device, and at the same time, the information holding time. Therefore, a high performance DRAM device can be provided. DRAM
In the element, the misalignment in the contact hole processing before forming the storage electrode becomes more remarkable as the miniaturization progresses. According to the present invention, the selective oxide film and the high-concentration buried layer are provided so that the misalignment can be allowed. Since they are arranged, the more the miniaturization progresses, the more the effect of improving the low electric field and the information retention characteristic appears.

[Brief description of drawings]

1A and 1B are cross-sectional views showing a basic structure of a semiconductor device according to the present invention, FIG. 1A is a cross-sectional view showing a structure having selective oxide films having different thicknesses, and FIG. 1B is a selective oxide film having different thicknesses. And (c) is a sectional view having a high-concentration buried layer having a different depth, and (c) is a sectional view having a high-concentration buried layer having a different depth and a different concentration.

FIG. 2 is a process diagram showing a cross-sectional structure of one embodiment of the method for manufacturing a semiconductor device according to the present invention shown in FIGS.

FIG. 3 is a cross-sectional view showing an intermediate step of another embodiment of the method of manufacturing the semiconductor device according to the present invention shown in FIG. 1 (c).

FIG. 4 is a plan view showing a pattern arrangement example of a selective oxide film in the manufacturing process of FIG.

5 is a cross-sectional view of a DRAM device to which the basic structure of the semiconductor device shown in FIG. 1B according to the present invention is applied.

FIG. 6 is a histogram showing information retention time characteristics when the present invention is applied to a DRAM device, compared with a conventional example.

7 is a sectional view of a DRAM device to which the basic structure of the semiconductor device shown in FIG. 1C according to the present invention is applied.

[Explanation of symbols]

1, 7 ... Silicon substrate, 2, 10, 12 ... Selective oxide film, 3, 18 ... Active region, 4, 5, 6, 13, 14, 15 ... High-concentration buried layer, 8, 21, 23, 25, 27 ... Silicon oxide film, 9, 11 ... Silicon nitride film, 16, 19, 20, 26, 26a ... Source / drain region, 17 ... Gate electrode 22, 28, 30 ... Polycrystalline silicon film, 24, 41 ... Low concentration Source / drain regions, 29 ... Capacitor insulating film (silicon oxynitride film), 31 ... Glass film, 32 ... Bit wiring, 33, 34 ... High-concentration buried layer, 40 ... Gate oxide film.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Osamu Okura 1-280 Higashi Koikeku, Kokubunji, Tokyo Metropolitan Research Center, Hitachi Ltd. (72) Takashi Nishida 1-280 Higashi Koikeku, Kokubunji, Tokyo Hitachi Co., Ltd. Central Research Center

Claims (9)

[Claims] 1. In a semiconductor device having a selective oxide film for device isolation, the selective oxide film has at least two kinds of film thickness and is close to an active region where a source / drain region and a gate region of a MOS transistor are formed. A semiconductor element having a thin side film. 2. In a semiconductor element having a high-concentration buried layer and a selective oxide film for element isolation, a portion below the selective oxide film of the high-concentration buried layer has a depth of at least two kinds from a substrate surface. And a deeper depth on the side closer to the active region where the source / drain region and gate region of the MOS transistor are formed. 3. A semiconductor device having a high-concentration buried layer and a selective oxide film for device isolation, wherein the selective oxide film is at least 2.
Part of the high-concentration buried layer under the selective oxide film, which has different kinds of film thickness, and is formed thin on the side close to the active region where the source / drain region and gate region of the MOS transistor are formed. Has a depth of at least two kinds of the high-concentration buried layer from the substrate surface, and the concentration of the high-concentration buried layer is formed lower on the thin side than on the thick side of the selective oxide film. A semiconductor device characterized in that 4. The semiconductor device according to claim 2, wherein the conductivity type of the high-concentration buried layer is opposite to the conductivity type of the source / drain regions of the MOS transistor. 5. The semiconductor device according to claim 1, wherein the semiconductor device is a DRAM device. 6. A method of manufacturing a semiconductor device, comprising a step of selectively oxidizing a silicon nitride film as a mask to form a selective oxide film for element isolation, wherein a first selective oxidation is performed by using the silicon nitride film as a mask. Step 1 of forming a selective oxide film having a thickness of 1 and then Step 2 of forming a silicon nitride film on the side wall of the silicon nitride film, and second selective oxidation by again using the silicon nitride film as a mask. And a step 3 of forming a selective oxide film having a second thickness larger than the above thickness, and the steps 2 and 3 are performed at least once in the order of steps. 7. A method further comprising the step of implanting impurity ions through a selective oxide film having at least two different film thicknesses formed by the method for manufacturing a semiconductor device according to claim 6 to form a high-concentration buried layer. A method for manufacturing a characteristic semiconductor device. 8. The method of manufacturing a semiconductor element according to claim 7, wherein the impurity ion implantation is performed with at least two types of implantation energy and at least two types of implantation amount. 9. The method of manufacturing a semiconductor device according to claim 6, wherein the semiconductor device is a DRAM device.