JPH1065116A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a leakage current from a p-n junction by forming the source region and the drain region of a MOS transistor on the surface of a silicon semiconductor substrate to be lower than the surface of the silicon semiconductor substrate directly beneath the bottom of side walls. SOLUTION: Boron ions are implanted by ion implantation to form a p-type impurity diffusion region 4 for threshold voltage control. Etching is performed to form recesses 1A, 1B which extend from the surface of exposed portions extending form the n-type source region 8 and the n-type drain region 9 in an LDD structure to the silicon semiconductor substrate 1 beyond the p-type impurity diffusion region 4. The p-type impurity diffusion region 4 for threshold voltage control is removed, except for a channel region required for the transistor operation. Thus the impurity concentration in a p-n junction is reduced to facilitate the extension of a depletion layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic random access memory (dynamic) in which a leakage current in a pn junction is reduced and charge retention characteristics are improved.
random access memory: DRA
M) and a method of manufacturing the same.

In a DRAM, the electric charge stored in a storage capacitor is stored as information. Therefore, it is important to prevent the electric charge from dissipating and to keep the electric charge as long as possible. Provides one way to meet that need.

[0003]

2. Description of the Related Art In general, there are a plurality of paths for escaping charges stored in a storage capacitor in a DRAM. The main paths are, for example, a leakage current of a pn junction and a sub-threshold in a transistor. • Leakage current from the source to the drain called leakage, leakage current in the storage capacitor, etc.

A normal n-channel MOS (metal O)
xide semiconductor) FET (fi
The leak current of the pn junction in the eld effect transistor is a p-type impurity diffusion region for controlling the threshold voltage and an LDD (lightly doped).
This corresponds to a leakage current of a pn junction generated by an n-type impurity diffusion region which is a source region and a drain region including a drain structure.

Generally, in the pn junction, LDD
Although the n-type impurity diffusion region including the structural portion has a higher impurity concentration and a shallower impurity distribution,
The distribution of impurities in the p-type impurity diffusion region for controlling the threshold voltage is deep.

From the distribution of impurities as described above, M
The leakage current at the pn junction of the OSFET is governed by the p-type impurity concentration.

[0007]

In the conventional MOSFET, the p-type impurity for controlling the threshold voltage is introduced over the entire active region, so that the impurity is introduced into regions other than the channel and the leakage current is reduced. Was difficult to reduce.

Further, in order to miniaturize the element dimensions, it is necessary to suppress the short channel effect.
It is necessary to increase the ion implantation dose for controlling the threshold voltage, and therefore, there is a problem that the impurity concentration increases and the leak current further increases.

According to the present invention, the impurity for controlling the threshold voltage is introduced only into the channel region by a simple means of adding only one etching step, and the leakage current from the pn junction is reduced. To be.

[0010]

According to the present invention, there is provided a MOSFE.
When manufacturing T, it is fundamental to remove unnecessary threshold voltage controlling impurities by etching a silicon layer after forming a sidewall of a gate.

As described above, in the semiconductor device according to the present invention, (1) one conductivity type impurity diffusion region for controlling the threshold voltage (for example, p-type impurity diffusion region 4 for controlling the threshold voltage); ) For removing the silicon semiconductor substrate (for example, the p-type silicon semiconductor substrate 1) under the gate insulating film (for example, the gate insulating film 5). A MOS transistor having a source region (for example, an n-type intrinsic source region 8A) and a drain region (for example, an n-type intrinsic drain region 9A) formed on a surface of a substrate (also a p-type silicon semiconductor substrate 1). Or,
Or

(2) In the above (1), the surface of the silicon semiconductor substrate on which the source region and the drain region are formed is formed by silicon immediately below the bottom surface of a side wall (eg, the side wall 10) formed on the side surface of the gate. Characterized by being lower than the surface of the semiconductor substrate,
Or

(3) After forming the gate (eg, gate insulating film 5, gate electrode 7, etc.) of the MOS transistor,
One conductivity type impurity diffusion region for controlling the threshold voltage (for example, a p-type impurity diffusion region for controlling the threshold voltage) on the surface of the silicon semiconductor substrate exposed to the portion where the source region is to be formed and the portion where the drain region is to be formed Removing step 4) to form recesses (eg, recesses 1A and 1B); or

(4) A side wall (for example, side wall 1) is formed on the side surface at the gate of the MOS transistor.
After the formation of (0), the one conductivity type impurity diffusion region for controlling the threshold voltage on the surface of the silicon semiconductor substrate exposed at the portion where the source region is to be formed and the portion where the drain region is to be formed is removed to form a recess. Characterized in that it comprises the step of

(5) In the above (3) or (4),
The removal of the one conductivity type impurity diffusion region for controlling the threshold voltage is performed by etching the silicon semiconductor substrate, or

(6) In the above (3) or (4),
Or removing the one conductivity type impurity diffusion region for controlling the threshold voltage by performing thermal oxidation of the silicon semiconductor substrate and removal of the generated thermal oxide film, or

(7) In any one of the above (3) to (6), the one conductivity type impurity diffusion region for controlling the threshold voltage is removed to form a recess, and then the intrinsic region is formed by ion implantation. Source region, intrinsic drain region and the like (for example, n-type intrinsic source region 8A, n-type intrinsic drain region 9A, and n-type source region 8 and n-type drain region 9 having an LDD structure)
Or an impurity-introduced region that connects

(8) In any one of the above (3) to (6), after forming the recess by removing the one conductivity type impurity diffusion region for controlling the threshold voltage, an electrode is formed in at least the recess. Forming an impurity-containing conductive film that also serves as an impurity to diffuse the inner wall, or

(9) In any one of the above (3) to (8), after forming a recess by removing the one conductivity type impurity diffusion region for controlling the threshold voltage, at least the inside of the recess is heated. It is characterized by being oxidized.

By adopting the above means, the impurity for controlling the threshold voltage exists only in the channel region and is removed from the source region and the drain region, so that the leakage current at the pn junction is extremely small. In other words, the retention characteristic of the stored charge, which is information in the DRAM, is improved, and the configuration is easily obtained because only one additional etching step is required.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 to 3 are cutaway side views showing a main part of a semiconductor device in a process step for explaining a first embodiment of the present invention. The description will be made with reference to the drawings such as FIG.

[0022] FIG 1 (A) refer to 1- (1) forming an oxidation-resistant mask film made of the pad film and Si ₃ N ₄ consisting of SiO ₂ in the p-type silicon semiconductor substrate 1 in the in the active region generates scheduled on portions So-called selective thermal oxidation (thermal oxidation)
By applying the non-silicon (LOCOS) method, the thickness of SiO 2 is, for example, 200 [nm].
₂ is formed.

1- (2) After removing the oxidation-resistant mask film and the like and exposing the active region of the p-type silicon semiconductor substrate 1, the thickness is, for example, 5 [mm] by applying a thermal oxidation method. The thickness of the sacrificial oxide film 3 made of SiO ₂ is formed.

1- (3) By applying the ion implantation method, the dose is set to, for example, 1 × 10 ¹³ [cm ⁻² ], the implantation energy is set to, for example, 20 [keV], and the implantation of boron ions is performed. Then, a p-type impurity diffusion region 4 for controlling the threshold voltage is formed.

1 (B) 1- (4) After removing the sacrificial oxide film 3, a gate insulating layer made of SiO ₂ having a thickness of, for example, 4 [nm] is obtained by applying a thermal oxidation method. A film 5 is formed.

1- (5) Chemical vapor deposition
A polycrystalline silicon film having a thickness of, for example, 150 [nm] is formed by applying an oxidation (position: CVD) method.

1- (6) By applying the ion implantation method, the dose is set to, for example, 1 × 10 ¹⁵ [cm ⁻² ], and the implantation energy is set to, for example, 20 [keV]. Of phosphorus (P) ions for making the semiconductor conductive.

Note that this ion implantation step can be omitted by adding impurities during the formation of the polycrystalline silicon film.

1- (7) A cap insulating film 6 having a thickness of, for example, 20 [nm] is formed on the polycrystalline silicon film by applying the thermal oxidation method.

1- (8) The resist process in the lithography technique and the etching gas are CHF ₃ + CF ₄ (SiO
₂ ) and HBr (for polycrystalline silicon) reactive ion etching (reactive ion etc)
The shing (RIE) method is used to etch the cap insulating film 6, the polycrystalline silicon film, and the gate insulating film 5 into a gate pattern.

After this step, the polycrystalline silicon film is gate-patterned.

2 (A) 2- (1) By applying the ion implantation method, the dose is set to, for example, 1 × 10 ¹⁴ [cm ⁻² ], and the implantation energy is set to 10
As [keV], As ions are implanted,
An n-type source region 8 and an n-type drain region 9 in the LDD structure are formed.

2 (B) 2- (2) The thickness is, for example, 30 [n] by applying the CVD method.
m], an insulating film made of SiO ₂ is formed.

2- (3) The side wall 10 is formed by performing anisotropic etching of the SiO ₂ insulating film by applying the RIE method using CHF ₃ + CF ₄ as an etching gas. .

3 (A) 3- (1) The LD on the p-type silicon semiconductor substrate 1 is obtained by applying the RIE method using HBr as an etching gas.
Etching is performed to reach the silicon semiconductor substrate 1 from the surface of the portion exposed as the extending portion of the n-type source region 8 and the n-type drain region 9 in the D structure, beyond the p-type impurity diffusion region 4, and The recesses 1A and 1B having a thickness of, for example, 50 [nm] are formed.

3 (B) 3- (2) By applying the ion implantation method, the dose is set to, for example, 1 × 10 ¹⁴ [cm ⁻² ], and the ion acceleration energy is set to 10 [keV]. By implanting As ions, an n-type intrinsic source region 8A and an n-type intrinsic drain region 9A are formed.

Here, the n-type intrinsic source region 8A is a bit line contact region and the n-type intrinsic drain region 9A
Function as memory capacitor contact areas, respectively.

The connection between the n-type source region 8 and the n-type intrinsic source region 8A having the LDD structure or the connection between the n-type drain region 9 and the n-type intrinsic drain region 9A having the LDD structure are respectively formed by the recesses 1A and 1B. This is performed by the impurity introduction region formed on the side wall.

When the n-type intrinsic source region 8A and the n-type intrinsic drain region 9A are formed, the impurity introduction region is easily formed by performing ion implantation obliquely to the wafer surface and rotating the wafer. be able to.

Instead of the ion implantation method, an impurity-containing polycrystalline silicon film serving as an electrode may be formed, and then heat treatment may be performed to form an impurity introduction region by a solid-solid diffusion method.

Thereafter, the semiconductor device is completed through normal steps, for example, formation of a memory capacitor, formation of a bit line, formation of a metal wiring, and the like.

In the semiconductor device completed as described above, the p-type impurity diffusion region 4 for controlling the threshold voltage formed in the step 1- (3) is replaced by the step 3- (1).
And leave only the channel region necessary for transistor operation,
Others are removed, so that the impurity concentration at the pn junction is reduced and the depletion layer is easily extended, so that the leakage current can be reduced.

In the present invention, without being limited to the above-described embodiment, many other modifications can be realized.

For example, in the first embodiment described above, after forming the side walls 10, the silicon semiconductor substrate 1 is etched to form the recesses 1A and 1B.
Is formed, but this etching may be performed before forming the side wall 10.

FIGS. 4 to 6 are cutaway side views showing a main part of a semiconductor device in a process key point for explaining a second embodiment of the present invention. And the same symbol as the same symbol represent the same part or have the same meaning.

Referring to FIG. 4A, 4- (1) SiO ₂ having a thickness of, for example, 200 [nm] is obtained by applying the LOCOS method to the p-type silicon semiconductor substrate 1.
A field insulating film 2 is formed.

4- (2) After removing the oxidation-resistant mask film and the like to expose the active region of the p-type silicon semiconductor substrate 1, the thickness is, for example, 5 [mm] by applying the thermal oxidation method. The thickness of the sacrificial oxide film 3 made of SiO ₂ is formed.

4- (3) By applying the ion implantation method, the dose is set to, for example, 1 × 10 ¹³ [cm ⁻² ], the implantation energy is set to, for example, 20 [keV], and boron ions are implanted. Then, a p-type impurity diffusion region 4 for controlling the threshold voltage is formed.

4 (B) 4- (4) After removing the sacrificial oxide film 3, a gate insulating layer made of SiO ₂ having a thickness of, for example, 4 [nm] is obtained by applying a thermal oxidation method. A film 5 is formed.

4- (5) The thickness is, for example, 150 by applying the CVD method.
[Nm] polycrystalline silicon film is formed.

4- (6) By applying the ion implantation method, the dose is set to, for example, 1 × 10 ¹⁵ [cm ⁻² ] and the implantation energy is set to, for example, 20 [keV]. Of phosphorus (P) ions for making the semiconductor conductive.

Note that this ion implantation step can be omitted by including impurities during the formation of the polycrystalline silicon film.

4- (7) A cap insulating film 6 having a thickness of, for example, 20 nm is formed on the polycrystalline silicon film by applying the thermal oxidation method.

4- (8) The resist process in the lithography technique and the etching gas are CHF ₃ + CF ₄ (SiO
₂ ) and HBr (for polycrystalline silicon), the cap insulating film 6, the polycrystalline silicon film, and the gate insulating film 5 are etched into a gate pattern.

After this step, the polycrystalline silicon film is gate-patterned.

Referring to FIG. 5A, 5- (1) p-type for controlling the threshold voltage on the p-type silicon semiconductor substrate 1 by applying the RIE method using HBr as an etching gas. From the surface of the portion exposed as the extending portion of impurity diffusion region 4, p-type impurity diffusion region 4
To reach the silicon semiconductor substrate 1 to form the recesses 1A and 1B having a depth of, for example, 50 [nm].

5 (B) 5- (2) By applying the ion implantation method, the dose is set to, for example, 1 × 10 ¹⁴ [cm ⁻² ], and the implantation energy is set to 10
As [keV], As ions are implanted,
An n-type source region 8 and an n-type drain region 9 in the LDD structure are formed.

In this case, the impurity introduction is also performed on the side wall of the recess 1A or 1B, as is apparent from the figure. This is because the n-type source region 8 and the n-type drain region 9 are formed.
Can be easily formed by performing ion implantation obliquely with respect to the wafer surface and rotating the wafer.

Instead of the ion implantation method, a heat treatment is performed after forming an impurity-containing polycrystalline silicon film acting as an electrode, and the n-type source region 8 and the n-type drain region 9 are formed by a solid-solid diffusion method. It may be formed.

6 (A) 6- (1) The thickness is, for example, 30 [n] by applying the CVD method.
m], an insulating film made of SiO ₂ is formed.

6- (2) Anisotropic etching of the SiO ₂ insulating film is performed to form the side walls 10 by applying the RIE method using CHF ₃ + CF ₄ as an etching gas. .

6 (B) 6- (3) By applying the ion implantation method, the dose is set to, for example, 1 × 10 ¹⁴ [cm ⁻² ], and the ion acceleration energy is set to 10 [keV]. By implanting As ions, an n-type intrinsic source region 8A and an n-type intrinsic drain region 9A are formed.

Here, the n-type intrinsic source region 8A is a bit line contact region and the n-type intrinsic drain region 9A
Function as memory capacitor contact areas, respectively.

Thereafter, the semiconductor device is completed through normal steps, for example, formation of a memory capacitor, formation of a bit line, formation of a metal wiring, and the like.

In the semiconductor device completed as described above, the p-type impurity diffusion region 4 for controlling the threshold voltage formed in the step 4- (3) is replaced by the step 5- (1).
And leave only the channel region necessary for transistor operation,
Others are removed, so that the impurity concentration at the pn junction is reduced and the depletion layer is easily extended, so that the leakage current can be reduced.

In the second embodiment, the formation of the gate electrode 7 is completed in the step 4- (8) described with reference to FIG. 4B, and the sidewall 10 is formed in the next stage. Instead, the feature is that the silicon semiconductor substrate 1 is etched to form the recesses 1A and 1B.

In this case, the p-type impurity diffusion region 4 for controlling the threshold voltage is removed to the vicinity of the channel region, so that the effect of reducing the pn junction leakage current is enhanced.

However, in this case, defects and contamination due to the etching of the silicon semiconductor substrate 1 tend to affect the reliability of the transistor. To avoid this, if a sacrificial oxidation technique described later is introduced, good.

In the first and second embodiments, the recess 1
The depths of A and 1B are set to 50 [nm], which is suitable for the p-type impurity diffusion region 4 formed under the ion implantation conditions for controlling the threshold voltage required for the semiconductor device. Therefore, it must be appropriately determined in consideration of the ion implantation conditions, the value of the leak current, and the like.

As mentioned above, generally, when a silicon semiconductor substrate is etched, there is a high possibility that contamination or a defect may enter the etched surface. The case where the recesses 1A and 1B are formed by etching is no exception.

To avoid this, in the first embodiment, after etching the silicon semiconductor substrate 1 in the step 3- (1), or in the step 3- (2), the n-type intrinsic source may be used. After forming the region 8A and the n-type intrinsic drain region 9A, a step of applying a thermal oxidation method to form a thin oxide film (sacrificial oxide film) on the surface of the silicon semiconductor substrate 1 and then removing the thin oxide film is introduced. It is good to remove contamination and defects together with the film.

The technique of using the sacrificial oxide film can of course be employed in the second embodiment described with reference to FIGS. 4 to 6, and in that case, the process 4 After forming the gate electrode 7 in (8), the side electrode
Step 5-(1) without forming the wall 10
In step 5, the silicon semiconductor substrate 1 is etched to form the recesses 1A and 1B, and then the sacrificial oxide film is formed and removed immediately, or the LD is formed in the step 5- (2).
After the formation of the n-type source region 8 and the n-type drain region 9 in the D structure, the formation and removal of the sacrificial oxide film are performed.

Regarding the removal of the sacrificial oxide film,
It is not necessary to set a process for this, and it may be removed later by using an etching process for forming an electrode contact hole.

In any of the above embodiments, the silicon semiconductor substrate 1 is etched when the p-type impurity diffusion region 4 for controlling the threshold voltage is selectively removed. If the impurity diffusion region 4 is formed shallowly, or if the impurity concentration is rapidly reduced in the depth direction from the surface, it depends on the thermal oxide film forming step and the thermal oxide film removing step. Thus, an effect equivalent to the etching of the silicon semiconductor substrate 1 can be equivalently obtained.

In each of the above embodiments, a DRAM in which the leakage current of the pn junction has a large effect has been described. However, when the present invention is applied to a logic device, the capacitance of the pn junction is reduced. As a result, power consumption can be reduced, and high-speed operability can be improved.

[0076]

In the semiconductor device and the method of manufacturing the same according to the present invention, a recess for removing the one conductivity type impurity diffusion region for controlling the threshold voltage is formed, and the surface of the silicon semiconductor substrate under the gate insulating film is formed. Alternatively, the source region and the drain region of the MOS transistor are formed on the surface of the silicon semiconductor substrate which is lower than the surface of the silicon semiconductor substrate immediately below the bottom surface of the side wall formed on the side surface of the gate.

According to the above configuration, the impurity for controlling the threshold voltage exists only in the channel region and is removed from the source region and the drain region. Therefore, the leakage current at the pn junction is extremely small. In other words, the retention characteristic of the stored charge, which is information in the DRAM, is improved, and the configuration is easily obtained because only one additional etching step is required.

[Brief description of the drawings]

FIG. 1 is a cutaway side view showing a main part of a semiconductor device in a process key point for explaining a first embodiment of the present invention.

FIG. 2 is a fragmentary side view showing a semiconductor device in a process key point for explaining a first embodiment of the present invention;

FIG. 3 is a fragmentary side elevational view showing a semiconductor device at a key step in the process for explaining the first embodiment of the present invention;

FIG. 4 is a fragmentary sectional side view showing a semiconductor device in a process key point for explaining a second embodiment of the present invention;

FIG. 5 is a fragmentary side view showing a semiconductor device at a key point in a process for explaining a second embodiment of the present invention;

FIG. 6 is a fragmentary side view showing a semiconductor device in a process key point for describing a second embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 silicon semiconductor substrate 1A recess 1B recess 2 field insulating film 3 sacrificial oxide film 4 p-type impurity diffusion region for controlling threshold voltage 5 gate insulating film 6 cap insulating film 7 gate electrode 8 n-type source region 8A n-type intrinsic source Region 9 N-type drain region 9A N-type intrinsic drain region 10 Side wall

Claims (9)

[Claims] A source region is formed on a surface of a silicon semiconductor substrate lower than a surface of a silicon semiconductor substrate under a gate insulating film, wherein a recess is formed to remove one conductivity type impurity diffusion region for controlling a threshold voltage. And a MOS transistor having a drain region formed therein. 2. The method according to claim 1, wherein the surface of the silicon semiconductor substrate on which the source region and the drain region are formed is lower than the surface of the silicon semiconductor substrate immediately below the bottom surface of the side wall formed on the side surface of the gate. The semiconductor device according to claim 1, wherein: 3. A one-conductivity-type impurity diffusion region for controlling a threshold voltage on a surface of a silicon semiconductor substrate exposed at a portion where a source region is to be formed and a portion where a drain region is to be formed after a gate of a MOS transistor is formed. A step of forming a recess by removing the semiconductor device. 4. A method of controlling a threshold voltage on a surface of a silicon semiconductor substrate exposed at a portion where a source region is to be formed and a portion where a drain region is to be formed after forming a side wall on a side surface of a gate of a MOS transistor. Forming a recess by removing an impurity diffusion region of one conductivity type for use in a semiconductor device. 5. The method according to claim 3, wherein the one conductivity type impurity diffusion region for controlling the threshold voltage is removed by etching the silicon semiconductor substrate. 6. The method according to claim 3, wherein the one conductivity type impurity diffusion region for controlling the threshold voltage is removed by thermal oxidation of the silicon semiconductor substrate and removal of the generated thermal oxide film. The manufacturing method of the semiconductor device described in the above. 7. A conductive region such as an intrinsic source region and an intrinsic drain region is formed by ion implantation after forming a recess by removing an impurity diffusion region of one conductivity type for controlling a threshold voltage. 7. The method for manufacturing a semiconductor device according to claim 3, wherein: 8. An impurity-conducting conductive film serving also as an electrode is formed in at least the recess, and the impurity is diffused into the inner wall at least in the recess after removing the impurity diffusion region of one conductivity type for controlling the threshold voltage. The method of manufacturing a semiconductor device according to claim 3, wherein: 9. The method according to claim 3, wherein after forming the recess by removing the one conductivity type impurity diffusion region for controlling the threshold voltage, at least the inside of the recess is thermally oxidized. Of manufacturing a semiconductor device.