JPS62208661A - Dynamic random access memory - Google Patents

Abstract

PURPOSE:To prevent capacity from reduction in a storage capacitor by a method wherein a substrate in a trench MOS structure serves as a counter electrode and a conductive layer buried in the trench through the intermediary of a dielectric layer serves as an accumulating electrode. CONSTITUTION:A p<+> type polycrystalline Si layer covering the internal surface of a trench 4 provided in a substrate 1 constitutes a region of high impurity concentration, with its potential same as that of the substrate 1, which serves as a cell plate (counter electrode) 5. The cell plate 5 is attached to an SiO2 insulating layer 21 defining the side walls of the trench 4 and prevents impurity atoms implanted in the cell plate 5 from loss due to diffusion into the substrate 1 during heat treatment in later manufacturing processes. In this way, high impurity concentration is maintained in the p<+> type polycrystalline Si layer that is the cell plate 5, which, when used as an electrode to counter an accumulating electrode 7 of a storage capacitor 20, prevents accumulating capacity from reduction in the presence of a depletion layer.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Embodiment Schematic diagram of the first embodiment (first embodiment) Figure) Process diagram of the first manufacturing method example (Figure 2) Schematic diagram of the second embodiment (Figure 3) Process diagram of the second manufacturing method example (Figure 4) Schematic diagram of the conventional structure example ( (Fig. 5) Effects of the invention [Summary] In a dynamic random access memory (hereinafter abbreviated as DRAM) cell having a trench capacitor, the substrate S side in the trench MO3 structure is used as a counter electrode, and the trench is connected to the trench through a dielectric layer. The manufacturing process starts with a highly impurity-concentrated conductive layer for a counter electrode formed on the inner surface of the trench, with the buried conductive layer M side used as a storage electrode to prevent interference and soft errors between capacitors, and an insulating layer interposed on the side surface of the trench. This prevents impurities from dissipating around the trench due to the thermal history inside, thereby preventing the capacitor capacity from decreasing.

[Industrial application field]

The present invention relates to the structure of a highly integrated and high performance DRAM cell.

A trench capacitor has an MO3 structure in which the capacitor part is configured three-dimensionally (trench-like), and can have a larger effective capacitor area than the Brenna type cell, which has been commonly used up to 256 DRAMs. Because of this, it is characterized by its small size and large storage capacity.

However, trench capacitors have the following problems, and there is a need for a structure that is smaller, has a large storage capacity, and does not cause punch-through even when highly integrated.

[Conventional technology]

FIG. 5 is a schematic side sectional view showing a conventional example of a trench capacitor cell.

In the figure, 51 is a semiconductor substrate made of p-type silicon (p-3i).
The substrate, 52 is a field insulating layer that defines a cell region and is a silicon dioxide (SiO□) layer, 53 is a storage electrode for electrons forming an inversion layer, 54 is a dielectric layer, and 55 is a polycrystalline silicon (polySi) layer. An inversion layer 53, a dielectric layer 54, and a cell plate 55 constitute a storage capacitor.

56 is a gate insulating layer, 57 is a word line made of polySt, and 58A and 58B are regions into which high concentration impurities are introduced, which are n-type source/drain (S/D) regions. The S
/D jl areas 58A, 58B and the word line 57 are used as gates to form an old S transistor (PET).

Then, it is in contact with the S/D region 58A, and is placed on the substrate in a direction perpendicular to the word line 57, such as aluminum (
8l) A bit line 59 is formed.

In this case, the connection between the storage capacitor and the MIS transistor is made between the SlDeM region 58B and the inversion layer 53, and therefore the inversion layer 53 on the substrate side becomes a storage electrode that stores information charges.

As shown on the right side of the figure, in the DRAM cell, storage capacitors of adjacent cells are formed in the vicinity with a field insulating film 52 in between. The dotted line represents the tip of the depletion layer that has spread into the substrate, and the figure shows a state in which adjacent capacitors punch through each other.

Although such conventional trench capacitor cells are advantageous in achieving higher integration than planar cells, they have the following drawbacks.

■ Since the write voltage loss storage capacitor uses the capacitance between the MO3 structure inversion layer 53 formed in the trench and the cell plate 55,
It is possible to write only up to a voltage that is lower than the voltage of the cell plate 55 by the dark value voltage for forming the inversion layer 53, and the power supply voltage cannot be used effectively.

■ Punch-through between capacitors In order to reduce the voltage loss mentioned above, the impurity concentration of the substrate must be lowered, but if it is too low, the depletion layer expands and punch-through occurs between the trench capacitors of adjacent cells, as shown in the figure. This causes electrical coupling between capacitors and impairs the reliability of stored information.

In addition, if a so-called old-C capacitor structure is used, in which a region of conductivity type opposite to that of the substrate is formed along the surface of the trench, the problem of voltage loss will be eliminated. The spacing between trench capacitors has become smaller, increasing the risk of punch-through.

Furthermore, at this time, the process of introducing impurities into the side walls of the trench cannot be performed by ion implantation, making manufacturing extremely difficult.

(2) Soft error The depletion layer spreads widely in the substrate due to the storage electrode (inversion layer) 53, and it is easy to capture minority carriers generated in the substrate, making it easy to cause soft errors due to incidence of alpha rays, for example.

The above drawbacks have been a major obstacle to the practical use of trench capacitors.

[Problem that the invention seeks to solve]

The problem to be solved by the present invention is the trench MO5 applied to the conventional trench capacitor as described above.
These problems are the problem of punch-through between adjacent storage capacitors, the problem of soft errors, the problem of a reduction in the degree of integration due to the arrangement of cell plates, and the problem of securing a large storage capacitance.

[Means for solving problems]

The above problem consists of a groove formed in a semiconductor substrate, an insulating layer formed on the inner surface of the line groove and having an opening at the bottom, and a film formed on the insulating layer including the inside of the opening. a first conductive layer ohmically connected to the semiconductor substrate at the opening; a dielectric layer formed on the first electrically sensitive layer; and an insulating layer.
a storage capacitor constituted by a first conductive layer and a second conductive layer embedded in the structure via a dielectric layer; and an MIS transistor formed on the semiconductor substrate surface; A dynamic random access memory according to the invention is solved in which the second conductive layer of the storage capacitor is ohmically connected to one source/drain region of the MIS transistor by a third conductive layer.

[For production]

That is, the DI of the present invention? The AM cell uses the substrate S side in the trench MO3 structure as a counter electrode and the conductive layer M side embedded in the trench via a dielectric layer as a storage electrode to prevent interference between capacitors and soft errors, thereby preventing DR.
Achieve higher performance and higher integration of AFI cells.

Furthermore, impurities are dissipated around the trench due to heat history during the manufacturing process from the highly impurity-concentrated conductive layer for the counter electrode formed on the inner surface of the trench with an insulating layer interposed on the side surface of the trench. By suppressing the impurity concentration of the conductive layer from decreasing and ensuring a high impurity concentration in the conductive layer for the counter electrode, the generation of a depletion layer in the conductive layer for the counter electrode is suppressed, thereby preventing the capacitance from decreasing. To prevent.

(Example〕 The present invention will be specifically explained below with reference to illustrated embodiments.

FIG. 1 is a plan view ta+ and a side sectional view (te) schematically showing a trench capacitor cell according to a first embodiment of the present invention.
1, FIG. 2 (al~(fl is a process plan view and a process sectional view showing the manufacturing method according to the first embodiment, and FIG. 3 schematically shows a trench capacitor cell according to the second embodiment of the present invention. Plan view ta) and side sectional view fbl shown in Fig. 4(a) -
(fl is a process plan view and a process cross-sectional view showing the manufacturing method according to the second example.

Identical objects are indicated by the same reference numerals throughout the figures.

In FIG. 1 (al and fb), 1 is a semiconductor substrate, which is a p-3i substrate, 3 is a field insulating layer that defines a cell region, which is a SiO□ layer, and 4 is a trench formed including the field region.
, 21 has a thickness of 100 to 50 mm formed on the side surface of the trench.
0 5iOz insulating layer for capacitor definition of large size, 5 is 1
A cell plate made of p+ type polySt, which is a first conductive layer that is in contact with the substrate at the bottom of the trench and is formed on the entire inner surface of the trench having the capacitor-defining SiO□ insulating layer except for the region near the opening of the trench. (Counter electrode), 6 is a dielectric layer mainly made of silicon nitride (Si, N4), 7 is a second conductive layer buried in the trench via the dielectric layer, and is an accumulation made of n-type poly-Si. It is an electrode.

A storage capacitor is constituted by the cell plate 5, the dielectric layer 6, and the storage electrode 7 in the trench 4 whose periphery is defined by the SiO□ insulating layer 21.

8 is a gate insulating layer and is a SiO□ layer, 9A and 9B are n゛゛source/drain (S/D)
In the w4 region, 9C is an n-type region 10^ formed at the same time as the source/drain region, which is the word line (gate electrode) of the own cell made of a titanium silicide (TiS+2) layer, etc., and 10B is the word line of the adjacent cell. It is.

p-3i substrate 1, gate insulating layer 8, n-type S/D region 9
A, 9B, and word line 10Δ constitute a transistor (cell transistor) of the memory cell.

11 is a SiO□ insulating layer, 128 is a third conductive layer made of an n-type polySt layer, 12
B is a third conductive layer, which is an n-type poly-Si layer that electrically connects the 5ZDN region of the transistor, for example 9B, and the storage electrode 7 of the storage capacitor.

The third conductive layer 12B connects the storage capacitor and cell 1
- transistors are connected to form a DRAM cell.

13 is an interlayer insulating layer, 14 is a wiring contact window, and 15 is in contact with the S/D region 98 via the third conductive layer 98, and extends on the interlayer insulating layer in a direction perpendicular to the word line. A bit line made of aluminum (A1) is shown.

As shown in the figure, in the trench capacitor cell according to the present invention, the S/09M region 9B of the transistor
The electrical connection between the storage electrode 7 of the storage capacitor and the storage electrode 7 of the storage capacitor is made by the third conductive layer 12 (12B).

Therefore, the second conductive layer 7 in the trench 4 becomes a storage electrode for accumulating information charges, and the first conductive layer 5 on the substrate side becomes a cell plate (counter electrode), which is the opposite of the conventional structure.

This prevents the depletion layer from expanding to the substrate side, thereby eliminating coupling (interference) between adjacent capacitors and reducing soft errors.

Then, a third conductive layer, that is, n
The type poly-Si layer 12 (12B) is the word line 10A.

By performing selective vapor phase growth on the Si surface exposed between 105 and 105, it is formed in self-alignment with the word line without using a mask process.

This allows cells to be miniaturized and highly integrated.

Furthermore, in the structure of the present invention, since the insulation @21 defining the periphery of the capacitor is provided on the side surface of the trench, S
In the heat treatment process performed in subsequent manufacturing processes such as the formation of the '/D regions 9A and 9B, a highly impurity-concentrated cell plate (counter electrode) 10 is formed on the inner surface of the trench.
From the p-type poly-Si layer (first conductive layer) 5 having a high impurity concentration of about 19 cm -3 to the p-
The diffusion of impurities into the 3i substrate 1 and the decrease in the impurity concentration are suppressed, thereby preventing the p-type poly-Si layer (
A decrease in the storage capacity of the capacitor due to the formation of a depletion layer at the interface with the dielectric N6 in the first conductive layer 5 is prevented.

Note that in the above structure, the first conductive layer (cell plate) 5
For example, Si for capacitor definition formed at the bottom of the trench.
It makes ohmic contact with the substrate 1 at the opening 22 of the O□ insulating layer 21, and is kept at the same potential as the substrate 1.

Next, the outline of the method for manufacturing the trench capacitor cell according to the above embodiment will be explained with reference to the process plan view and process cross-sectional view shown in FIGS. 2 (ta) to tf) and FIG. 1.

First, as an oxidation-resistant film for selective oxidation, for example, a 5i3Na layer (or Si3N
A composite layer 2 of 4 and SiO□ is formed, and using this as a mask, the Si substrate 1 is oxidized to form a SiO□ layer 3 with a thickness of 4000 nm as a field insulating layer.

FIG. 2 (see BL) Then, using conventional lamination and active ion etching (RIE), a trench 4 having a depth of, for example, 3 to 4 pm is formed on the oxidation-resistant head, including a part of the field insulating layer 3. .

Next, thermal oxidation is performed to give the inner surface of the trench 4 a thickness of, for example, 3.
A 5i02 insulating layer 21 for capacitor definition is formed to have a thickness of about 0.00 mm. There are no particular restrictions on this thickness, but if it is too thick, the effective dimensions of the trench will become small, so it should be 1000 Å.
The following are desirable.

Next, the 5i02 insulating layer 21 at the bottom of the l-wrench 4 is selectively removed by an anisotropic etching method that is predominant in the direction perpendicular to the substrate surface, such as active ion etching (RIE), and the 1st surface of the p-3i substrate is etched in this area. Opening 22 that exposes
form.

Figure 2 (see C1) Next, the entire surface of the substrate including the inner surface of the trench 4 is doped with boron at a high concentration by CVD to a thickness of about 1000.
A p-type poly-Si layer 5 is formed and isotropically etched (plasma etching) to leave the p-type poly-Si layer 5 only on the inner surface of the trench 4.

The p1 type poly-Si layer 5 is connected to the S at the bottom of the trench 4.
It contacts the p-3i substrate 1 through the opening 22 of the iO□ layer 21 and is electrically connected.

The purpose of forming this p'' type poly-Si layer 5 is to create a region with high impurity concentration at the same potential as the substrate 1 on the inner surface of the trench 4, so that the substrate portion can be used as a cell plate (counter electrode). Since this p-type poly-Si layer 5 is deposited on the SiO□ insulating layer 21 that defines the periphery of the trench 4 on the side surface of the trench 4, it is doped by heat treatment in the subsequent manufacturing process. This prevents impurity atoms (here, boron, arsenic or phosphorus when an n-type substrate is used) from being diffused into the substrate 1 and dissipated. Since the region is maintained as a high impurity concentration region, the storage capacitance is prevented from decreasing due to the generation of a depletion layer when used as an electrode of a storage capacitor.

Next, after removing the oxidation-resistant film 2 used in the selective oxidation, a dielectric layer is formed on the entire surface including the inner surface of the trench 4 having the p+ type poly-Si layer 5 to a thickness of, for example, about 100 mm.
3N4 layer (or Si02 layer, or a composite layer of these 5
6 is formed by oxidation or growth.

It is known that the dielectric strength of this layer can be improved by annealing it in an oxygen atmosphere.

FIG. 2 (see dl) Next, on the substrate 1 including the inside of the trench 4, a layer of n''' type polypolymer 934 doped with a high concentration of arsenic or phosphorus is formed to a thickness sufficient to fill the trench, and then isotropically The poly-Si layer 7 on the substrate is selectively removed by etching means to form an n-type poly-Si layer 7 that completely fills the trench 4 with the dielectric layer 6 interposed therebetween. Poly S
The i-layer 7, ie, the second conductive layer, functions as a storage electrode.

FIG. 2 (see el) Next, the dielectric layer 6 exposed outside the trench 4 is removed and the Si
After exposing the surface of the substrate 1, the surface of the substrate 1 is oxidized according to the usual method for forming MO5 transistors, and the M of the memory cell is
OS) Gate of transistors and peripheral circuits O3) SiO with a thickness of about 280 mm as the gate insulating layer of transistors
□ Form layer 8. At this time, if oxidation is performed at a low temperature of about 900'c, 50% of the surface of the p+ type bo'JSi layer (storage electrode) 7 is
i02 layer 8 has a thickness of about 600 layers.

Next, a material to be a gate material such as titanium silicide (TiSiz) is deposited on the main surface to a thickness of about 4000 mm, and then a material to be a gate material such as titanium silicide (TiSiz) is deposited on the main surface to a thickness of about 1000 mm.
Layer 11A is deposited and patterned to form a Ti5iz word line pattern with SiO□ layer 11A on top, and then about 1500 SiO2 layers are deposited again on the main surface.
A layer 11B is formed, and an SiO□ layer 1. Leaving the IA or SiO□ layer 11B (the above known techniques),
5i02 layer 11 (11A, 11B) whose surface becomes an insulating layer
Word line 10A, IO made of TiSi2 covered with
Form B etc. At this time, the surface of the Si substrate 1 not covered by the word line and the surface of the poly-Si layer 7 buried in the trench 4 are exposed.

Next, using the word line (gate electrode) 108 as a mask, arsenic is selectively ion-implanted to form n+ type source/drain regions 9A and 9B using a conventional method. At this time, an n-type impurity doped region 9C is also formed in the n-type polySt layer 7 buried in the trench 4.

Refer to FIG. 2(f). Next, a film with a thickness of 40 mm is deposited on the substrate by selective vapor growth means.
An n-type poly-Si layer doped with a high concentration of arsenic or phosphorus is selectively grown.

At this time, no poly-Si layer is grown on the SiO□ layers 11 and 3, and the source/drain regions 9A and 9B where the Si plane is exposed.
And third conductive layers 12A and 12B made of n'' type poly Si are formed on the n'' type poly Si layer 7, that is, the n1lf region 9C on the upper surface of the storage electrode. Although the n-type poly-Si layer does not grow on the layer end 1 of the SiO□ layer 21 for the purpose, since its thickness is less than 200 Å and the spacing is extremely narrow, the source/drain region 9B
The upper poly-Si layer and the poly-Si layer on the storage electrode 7 form a continuous third conductive layer 12B, so that the source/train region 9B and the storage electrode 7 are electrically connected.

FIG. 1 (see al and (bl), and hereinafter, an interlayer insulating layer 1 is applied over the entire surface of the substrate by a conventional method.
3 and the source/bit line contacts the cell.
A contact window 14 is opened on the drain region 9A, and a bit line 15 made of ^1 etc. is formed.

The memory cell according to the present invention completed as described above is
It has the following characteristics.

■ The counter electrode of the storage capacitor, that is, the cell plate, is deposited on the substrate itself, more specifically on the insulating layer provided on the side surface of the I-wrench, contacts the substrate at the bottom of the trench, and supplies power to the same potential as the substrate through the contact portion. conductive layer. Therefore, if the substrate is grounded, the potential of the counter electrode is extremely stable, and a reduction in operating margin and malfunction due to so-called voltage bumps are less likely to occur.

■ The substrate is one large equipotential electrode plate, and no matter how close the capacitors are, there is no interference between them.

This interference is caused by charge leakage due to bunch-through between capacitors, and when capacitors are in contact with each other through a depletion layer, potential changes due to charging and discharging that occur in one capacitor extend to the other capacitor due to capacitive coupling. This modulates the amount of accumulated charge.

■ The storage electrode is surrounded by an insulating layer (dielectric layer), and a depletion layer does not spread within the substrate, so soft errors are less likely to occur.

■ Storage capacitor consists of n-type polyst layer ~ dielectric layer ~ p
Since it has a structure of a type poly-Si layer and does not use an inversion layer, there is no write voltage loss.

■ Due to the structure of the memory cell, a capacitor is buried under the source/drain region of the Mis) transistor, so the memory cell itself is approximately the size of one transistor. Since it is significantly smaller than conventional cells and there is no cell plate that is formed on the substrate in conventional cells, there is no need to provide a dimensional margin for alignment between the cell plate and the capacitor and transistor, making the memory cell even more compact. Becomes smaller.

■ The counter electrode of the storage capacitor is a poly-Si layer with a high impurity concentration deposited on the inner surface of a trench formed in the substrate.
Since this poly-Si layer is selectively brought into contact with the substrate via a thin insulating layer at the side surfaces of the trench, it is electrically maintained at the same potential as the substrate; The impurity concentration of the poly-Si layer hardly decreases even after heat treatment during the manufacturing process.

In a capacitor with an n+ type semiconductor ~ dielectric layer ~ p+ type semiconductor structure, when a voltage is applied to the storage electrode, a depletion layer is generated on the semiconductor side, and when the concentration of n+ and p+ is low, the depletion layer becomes the dielectric layer. However, in the structure of the present invention, the impurity concentration of the counter electrode can be reduced as described above. Therefore, a decrease in storage capacity due to the generation of a depletion layer is prevented.

In addition, in the memory cell of the present invention, the substrate side is the cell plate, and since no cell plate is specifically formed on the substrate, the word line running next to the word line of the cell is equivalent to the gate oxide film. Since it is in contact with the storage electrode portion of the cell through the thin oxide film, capacitive coupling occurs here.

In DRAM, when a word line is selected, the adjacent word line is basically clamped to the ground potential, so the capacitive coupling capacitance slightly increases the storage capacity of the cell. This effect also occurs.

FIG. 3 is a plan view (a) and a side sectional view (bl) schematically showing a trench capacitor cell according to a second embodiment of the present invention.
It is.

In this structure, the memory cells are embedded in n-conyl on a p-substrate.

In the figure, 16 is an n-type well, and 107 is a second well buried in the trench via a dielectric layer.
A storage electrode made of p-type poly-Si with a conductive layer.

1098, 109B is a p+ type S/D region, and 109C is a p+ type region 112A formed together with the S/D region.
The third conductive layer 112B is a p-type poly-Si layer that electrically connects the S/D region of the transistor, for example 109B, and the storage electrode 107 of the storage capacitor. , other symbols indicate the same objects as in FIG.

Note that this structure is also applied when using a semiconductor substrate having a p-type well on an n-type substrate. However, in this case, the conductivity types of each conductive layer, S/D region, etc. are opposite to those in FIG. 3.

The method for manufacturing the trench capacitor cell according to the second embodiment is roughly as follows.

Figure 4 (see al.) By the usual method, a depth of 2 μm, for example, is applied to one surface of the p-5i substrate.
Using a semiconductor substrate having an n-well 16 formed therein, the n-well 16 is formed by a method similar to that described in FIG.
A Si:+L layer 2 is formed on the element formation region of the surface, and using this as a mask, a 0-field SiO□ layer 3 with a thickness of about 4,000 layers is formed by thermal oxidation.

Referring to FIG. 4(b), the oxidation-resistant region including a part of the field insulating layer 3 is then coated with a p-p bottom by using, for example, RIE treatment as in the previous embodiment.
-3i A trench 4 having a depth of, for example, 3 to 4 μm reaching inside the substrate 1 is formed.

Next, thermal oxidation is performed to give the inner surface of the trench 4 a thickness of, for example, 3.
A SiO□ insulating layer 21 for capacitor definition is formed to have a thickness of about 0.000 mm.

Next, by RIE processing, the Sin and insulating layer 21 at the bottom of the trench 4 are selectively removed, and an opening 22 exposing the surface of the p-3i substrate 1 is formed in this portion.

Refer to FIG. 4(C) Next, as in the first embodiment, the inner surface of the trench 4 is made of 0p type polyester with a thickness of about 1000 doped with boron at a high concentration.
Form layer 5. The p" type poly-Si layer 5 is formed at the bottom of the trench 4 through the opening 22 of the Sin2 layer 21.
It is electrically connected to the i-board 1.

Next, by the same method as in the first example, the above p type poly S
A Si3N4 layer (or SiO□ layer, or a composite layer thereof) 6 having a thickness of, for example, about 100 layers is formed as a dielectric layer over the entire surface including the inner surface of the trench 4 having the i-layer 5 by oxidation or growth.

Refer to FIG. 4 (dl) Then, by the same method as in the first embodiment, a p-type poly-Si layer 107 is formed, which completely fills the inside of the trench 4 with the dielectric layer 6 interposed therebetween and functions as a storage electrode.

FIG. 4 (see el) Next, after removing the dielectric layer 6 exposed outside the trench 4 and exposing the surface of the n-well 16, the normal M
OS) 340g layer 8 is formed on the n-well 16 surface according to the transistor formation method, and the gate Sin□ layer 8 is
5iOz layer IH11a, 11b whose surface is an insulating layer on top
) covered with a word line 10A made of TiSi2, for example.
, IOB, etc. are formed, and then boron ions are implanted into the exposed surface of the n-well 16 using the word line (gate electrode) 10^ etc. as a mask to form p° type source/drain regions 1098 and 109B. At this time, a p'' type impurity doped region 109C is also formed in the p'' type poly-Si layer 107 buried in the trench 4.

Refer to FIG. 4 ffl Next, as in the first embodiment, a selective vapor growth method is used to form a p
Third W conductive layer 112A and 112 made of type 1 poly-Si
Form B. At this time, as described above, the poly-Si layer on the source/drain region 109B and the poly-Si layer on the storage electrode 107 become a continuous third conductive layer 112B,
The source/drain region 109B and the storage electrode 107 are electrically connected.

Refer to FIGS. 1(a) and (bl) and thereafter apply an interlayer insulating layer 1 over the entire surface of the substrate by a conventional method.
3 and the source/bit line contacts the cell.
A contact window 14 is opened on the drain region 109A, and
A bit line 15 made of 1st grade is formed.

The memory cell according to the second embodiment completed as described above has the following features (advantages) in addition to the advantages of the structure according to the first embodiment described above.

■ Normally, a potential is supplied to the well by a bias generator or the like, so the potential tends to become unstable. Therefore, when the counter electrode of the capacitor is fixed to the well, the potential of the storage electrode of the capacitor fluctuates with the well potential, causing a problem that the reliability of the stored information decreases. The counter electrode is fixed to the substrate to which a stable potential is supplied.

Therefore, the potential of the storage electrode of the capacitor is less susceptible to fluctuations due to disturbances, and the reliability of stored information is improved.

■ Since the counter electrode and the storage electrode are formed of the same conductivity type, no depletion layer is generated within the counter electrode, and the effective storage capacity does not decrease.

It should be noted that the present invention is of course applied to a DRAM cell of a conductivity type opposite to that of the above embodiment.

〔Effect of the invention〕

As explained below, according to the present invention, highly stable
DR with trench capacitor structure that eliminates interference between capacitors, has high capacitor breakdown voltage, and allows for miniaturization and high integration.
An AM cell is obtained, and the impurity concentration of the opposing electrode of the capacitor is reduced due to the heat treatment during the manufacturing process, thereby preventing the storage capacity of the capacitor from decreasing and improving the reliability of stored information.

[Brief explanation of drawings]

FIG. 1 is a plan view (a) and a side sectional view (bl) schematically showing a trench capacitor cell according to a first embodiment of the present invention.
, FIG. 2 (al to (fl) are process plan views and process cross-sectional views showing the manufacturing method according to the first embodiment, and FIG. 3 schematically shows a trench capacitor cell according to the second embodiment of the present invention. Plan view (al) and partial plan view (bl)
, FIG. 4 (al~(rl) is a process plan view and a process sectional view showing the manufacturing method according to the second embodiment, and FIG. 5 is a schematic side sectional view of a conventional structure. In the figure, (2) is a semiconductor substrate. 2 is a p-3i substrate, 2 is an oxidation-resistant film, 3 is a field insulating layer, 5i02 layer, 4 is a trench, 5 is a first conductive layer, and is a cell plate (counter electrode) made of p'' type poly-Si. , 6 is a dielectric layer made of silicon nitride (SiJJ), and 7 is a second dielectric layer.
The conductive layer is a storage electrode made of n1 type poly-Si, 8 is a gate insulating layer, which is a 5i02 layer, and 9^, 9R are n° type source/drain 7 (S/D)? J
area, 9C is an n" type region, 10A is a word line (gate electrode), and 10B is a word line 11 of an adjacent cell, which is SiO□
Insulating layer, 12A, 12B is a third conductive layer consisting of n''' type polypolymer 934 layer, 13 is an interlayer insulating layer, 14 is a wiring contact window, 15 is a bit line 16 is an n-well, 21 is SiO□ insulation for capacitor measurement 22 is an opening, 107 is a second conductive layer and a storage electrode made of p type poly-Si, 1098, 109B is a p9 type source/drain (S/D) region, and 109C is a p type source/drain (S/D) region.
"type region, 1128, 112B is a third region made of p'" type polySt layer.
A conductive layer of , is shown.

Claims (1)

[Claims] 1. A groove formed in a semiconductor substrate; an insulating layer formed on the inner surface of the groove and having an opening at the bottom; and a film formed on the insulating layer including the inside of the opening. a first conductive layer that is ohmically connected to the semiconductor substrate at the opening, a dielectric layer formed on the first conductive layer, and the insulating layer;
a storage capacitor configured by a first conductive layer and a second conductive layer embedded in the trench via a dielectric layer; and an MIS transistor formed on the semiconductor substrate surface; A dynamic random access memory characterized in that the second conductive layer of the storage capacitor is ohmically connected to one source/drain region of the MIS transistor by a third conductive layer. 2. The dynamic random access memory according to claim 1, wherein the semiconductor substrate is an integral semiconductor substrate. 3. The semiconductor substrate is made of a semiconductor substrate of one conductivity type having a semiconductor layer of an opposite conductivity type on the upper part, the groove reaches the semiconductor substrate of one conductivity type, and the first conductive layer is connected to the semiconductor substrate through the opening. The dynamic random access memory according to claim 1, wherein the dynamic random access memory is ohmically connected to a semiconductor substrate of one conductivity type.