JP2010073859A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device (longitudinal SGT) that facilitates manufacture thereof, and increases an on-current without increasing an off-current while suppressing a short channel effect. <P>SOLUTION: The semiconductor device adopted includes a semiconductor body 4 formed in a hollow cylindrical shape, a first area 3 formed in the lower part of the body 4 and being the one of the source area and the drain area, a second area 5 formed in the upper part of the body 4 and being the other of the source area and the drain area, a channel area 4a formed in the area sandwiched between the source area and the drain area of the body 4, a gate electrode 7 formed so as to cover the inner circumference face and outer circumference face of the channel area 4a via a gate insulation film, and a third area 3a formed in the lower part of the body 4 so as to touch the first area and composed of a semiconductor layer having the same conductivity type as the first area. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, in particular, a vertical SGT (Surround Gate Transistor) and a method for manufacturing the same.

  In conventional planar MOS transistors, with the progress of miniaturization, it is difficult to suppress leakage current due to the short channel effect, and vertical SGT (Surround Gate Transistor) is being developed as an alternative transistor. (Patent Documents 1 and 2).

  FIG. 27 shows a cross-sectional view of a conventional vertical SGT. Reference numeral 100 denotes a silicon substrate, and a cylindrical (pillar-shaped) body region 101 is formed by etching silicon. A gate electrode 102 is formed on the surface of the body region 101 so as to surround a side surface portion of the body region with a gate insulating film 105 interposed therebetween. A source region (or drain region) 104 in which an N-type impurity is introduced into the silicon substrate 100 is formed on the outer periphery of the gate electrode 102. A drain region (or source region) 103 into which an N-type impurity is introduced is formed on the body region.

  In the conventional vertical SGT, in order to improve the on-current, the size of the body region 101 (cylinder diameter) may be increased. However, the threshold voltage greatly varies and the area occupied by the transistor also increases. There was a point. Further, as the size of the body region 101 is increased, the control of the gate electrode 102 in the central portion of the body region becomes weak, so that there is a problem that the off current increases.

Therefore, a vertical SGT has been proposed in which the body region has a hollow shape and a gate electrode and one of a source region and a drain region are formed in an inner region (Patent Document 3).
However, the vertical SGT of Patent Document 3 has a problem that the structure is complicated and it is not easy to manufacture.
Japanese Patent Laid-Open No. 10-326879 JP 2005-197704 A Japanese Patent Application Laid-Open No. 06-021467

As described above, in the conventional technique, when the size of the body region (cylinder diameter) is increased, there is a problem that the variation of the threshold voltage increases and the area occupied by the transistor increases. Further, as the size of the body region is increased, the control of the gate electrode in the center of the body region becomes weak, and there is a problem that the off current increases.
Furthermore, the vertical SGT in which the body region has a hollow shape and one of the gate electrode and the source region or the drain region is formed in the inner region has a problem that the structure is complicated and the manufacture is not easy.

The semiconductor device of the present invention includes a semiconductor body portion formed in a hollow cylindrical shape, a first region formed at a lower portion of the body portion and serving as one of a source region and a drain region, and an upper portion of the body portion. A second region that is the other of the source and drain regions, a channel region formed in a region sandwiched between the first region and the second region of the body portion, and an inner periphery of the channel region A gate electrode formed so as to cover a surface and an outer peripheral surface through a gate insulating film, and a semiconductor having the same conductivity type as that of the first region, formed below the body portion so as to be in contact with the first region And a third region composed of layers.
The method for manufacturing a semiconductor device of the present invention includes a first step of forming a first semiconductor layer of a first conductivity type on a semiconductor substrate and a second conductivity type of a first semiconductor layer on the first semiconductor layer. A second step of forming a second semiconductor layer, a third step of forming a third semiconductor layer of the first conductivity type on the second semiconductor layer, and a part of the first semiconductor layer. A fourth step of etching the remaining portion of the first semiconductor layer and the second and third semiconductor layers to form a hollow cylindrical body portion, and at least the second semiconductor of the body portion. A fifth step of forming a gate insulating film so as to cover an inner peripheral surface and an outer peripheral surface of the layer, and a sixth step of forming a gate electrode in the hollow portion and the outer peripheral portion of the body portion. Features.
Further, the method of manufacturing a semiconductor device of the present invention includes a step of forming a hollow cylindrical second conductive type semiconductor body so as to protrude from the main surface of the semiconductor substrate, and a first portion on the body portion. Introducing a first conductivity type impurity into the main surface of the semiconductor substrate not covered with the body portion simultaneously with introducing the conductivity type impurity; and a first conductivity type introduced into the main surface of the semiconductor substrate. And a step of forming a first conductivity type impurity region under the body portion, and a step of forming a gate electrode through a gate insulating film in the hollow portion and the outer peripheral portion of the body portion; Is provided.

  The semiconductor device (vertical SGT) of the present invention is easy to manufacture, can suppress the short channel effect, and can increase the on-current without increasing the off-current. Since the body region can be easily depleted, leakage ionization in the off state can be kept small.

[Basic form of the present invention]
FIG. 1 is a longitudinal sectional view showing a basic configuration of a semiconductor device of the present invention, and FIG. 2 is a transverse sectional view corresponding to the AA ′ portion of FIG. The semiconductor device shown in FIGS. 1 and 2 includes a semiconductor substrate 1, a hollow cylindrical body portion 4 that protrudes from the main surface 1a of the semiconductor substrate 1 and has at least a channel region 4a, and a semiconductor substrate of the channel region 4a. The first region 3 formed on one side, the lead portion 3a (third region) made of a semiconductor layer connected to the first region 3, and the channel region 4a formed on the opposite side of the semiconductor substrate 1 The gate insulating film 7 formed on the outer peripheral surface 4b and the inner peripheral surface 4c of the hollow cylindrical body portion 4 including the channel region 4a, and the channel region 4a via the gate insulating film 7 And a gate electrode 8 formed so as to face each other.
The first region 3 and the second region 5 are made of a semiconductor doped with impurities, and are impurity diffusion regions that function as a source region or a drain region of a transistor.

  A semiconductor substrate 1 is provided with a buried oxide film 2 having an STI structure, and a body portion 4 from which a part of the semiconductor substrate 1 protrudes is formed in a portion other than a region where the buried oxide film 2 is formed. ing. As shown in FIGS. 1 and 2, the body portion 4 is formed of a cylindrical semiconductor (for example, silicon) having a hollow portion 4d at the center. An interlayer insulating film 6 is formed on the main surface 1 a of the semiconductor substrate 1.

The body portion 4 has a first region 3 formed in the lower portion thereof, and a second region 5 formed in the upper portion thereof. A portion sandwiched between the first and second regions 3 and 5 is a channel region 4a. In this way, the body portion 4 shown in FIG. 1 includes the channel region 4a and the first and second regions 3 and 5.
The first and second regions 3 and 5 serve as a source region or a drain region in the transistor. Further, a lead portion (third region) 3 a made of a semiconductor layer is formed on the semiconductor substrate 1 so as to be connected to the first region 3. The third region 3 a is provided so as to extend outside the outer periphery of the body portion 4.
The channel region 4a is exposed on the outer peripheral surface 4b and the inner peripheral surface 4c of the body portion 4, and a gate insulating film 7 is formed so as to cover the exposed channel region 4a. The gate insulating film 7 is formed so as to cover the entire hollow body portion 4.

  A gate electrode 8 is formed on the semiconductor substrate 1 so as to face the channel region 4a with the gate insulating film 7 interposed therebetween. The gate electrode 8 is also formed inside the hollow portion 4d, and is opposed to the channel region 4 via the gate insulating film 7 formed in the hollow portion 4d. That is, the gate electrode 8 includes an inner gate electrode 8a formed in the hollow portion 4d that is the inside of the body portion 4, and an outer gate electrode 8b formed outside the body portion 4, and each gate electrode 8a , 8b can be applied with the same or different gate voltages.

  As shown in FIG. 2, the body 4 of the semiconductor device shown in FIG. 1 has a hollow cylindrical shape, but the shape of the body 4 is not limited to a circle. For example, as shown in FIG. Moreover, as shown in FIG.26 (b), it can also be set as a triangle shape. Further, the outer shape of the gate electrode 8 located on the outer peripheral side of the body portion 4 may not be similar to the body portion 4.

According to the semiconductor device described above, the gate electrode 8 is disposed not only on the outer peripheral surface 4b of the body portion 4 but also on the inner peripheral surface 2c with the gate insulating film 7 interposed therebetween. The variation in threshold voltage can be reduced without increasing the diameter), and the area occupied by the transistor does not increase. In addition, the control of the inner gate electrode 8a provided in the hollow portion 4d of the body portion 4 has a structure in which contacts are connected as will be described later. Can be reduced.
Further, since the potential is supplied to the first region 3 located below the body portion 4 through a lead portion 3a (third region) made of a semiconductor layer as will be described later, a contact for potential supply is provided. The plug can be easily formed.

[First Embodiment]
A method for manufacturing a semiconductor device (vertical SGT) and a manufactured semiconductor device according to the first embodiment of the present invention will be described below.
In the following description, the gate length is 45 nm, the gate width (periphery of the body part) is 220 nm, the silicon layer constituting the channel region 4a of the body part is 20 nm thick, and a 5 nm thick silicon oxide film is used as the gate insulating film. An example of a semiconductor device provided will be described. The P-type impurity concentration in the channel region is 3 × 10 ¹⁸ atoms / cm ³ , and the N-type impurity concentration in the first and second regions is 2 × 10 ²⁰ atoms / cm ³ .

  In FIG. 3, a P-type silicon substrate (semiconductor substrate) 1 is prepared, a buried insulating film 2 is formed by an STI (Shallow Trench Isolation) method or the like, and an element isolation region is formed. Expose. Thereafter, one transistor is formed in the inner region partitioned by the element isolation region made of the buried oxide film 2.

Next, in FIG. 4, on the silicon substrate 1, the first conductivity type silicon layer 13 (first semiconductor layer) that becomes the first region 3 and the lead portion 3 a and the second conductivity type that becomes the channel region 4. The silicon layer 14 (second semiconductor layer) and the other first conductivity type silicon layer 15 (third semiconductor layer) to be the second region 5 are sequentially stacked. The first and second first conductivity type silicon layers 13 and 15 contain N type impurities at a concentration of 1 × 10 ¹⁵ to 1 × 10 ²² atoms / cm ³ , and the second conductivity type silicon layer 14 includes P type impurities. Is contained at a concentration of 1 × 10 ¹⁵ to 1 × 10 ²² atoms / cm ³ . Each of the silicon layers 13 to 15 is formed by crystal growth of silicon in an exposed region on the surface of the silicon substrate 1. At the time of silicon formation, silicon is crystal-grown while mixing raw material gas containing impurities of the corresponding conductivity type. Each impurity concentration may be set in accordance with desired transistor characteristics.

Specifically, first, in order to remove the natural oxide film on the silicon substrate 1, it is heated to 1200 ° C. or higher in a vacuum chamber to expose a clean silicon atom surface. Then, after setting the crystal growth temperature to around 1100 ° C., raw materials SiH ₄ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl _4, etc. are supplied to the silicon substrate 1, and silicon is exposed to the exposed portion of the silicon surface by the CVD method. Crystallize the layer. The first conductivity is obtained by mixing at the same time as the growth of the silicon crystal using PH ₃ , AsH ₃ or the like as the N-type impurity during the crystal growth and using a raw material gas such as B ₂ H ₆ as the P-type impurity. A silicon layer of type (N type) or second conductivity type (P type) is obtained. The film thickness from the surface of the silicon substrate 1 to the upper surface of the other second conductivity type silicon layer 15 is set to about 50 nm.

  As another crystal growth method, after removing the natural oxide film by heating, the silicon can be grown by MBE (molecular beam epitaxy) method using a solid source of silicon. Similarly, during this crystallization, phosphorus (P), arsenic (As), boron (B), or the like is used as an N-type or P-type impurity. In addition to the above, the natural oxide film may be removed by etching with a multi-chamber or the like.

  Next, in FIG. 5, while leaving a part 13a of one first conductivity type silicon layer 13, the remaining part of one first conductivity type silicon layer 13, the second conductivity type silicon layer 14, and the other first conductivity type. By etching the silicon layer 15, the hollow cylindrical body portion 4 is formed. Specifically, a photoresist film is first applied on the other first conductivity type silicon layer 15 and then exposed using a desired mask, and a photoresist film pattern (on the other first conductivity type silicon layer 15 ( (Not shown). Thereafter, anisotropic dry etching is performed using the photoresist film as a mask to remove the other first conductivity type silicon layer 15 and the second conductivity type silicon layer 14, and further to the first conductivity of the third layer. The mold silicon layer 13 is removed leaving a thickness of about 10 nm. In the present embodiment, the other first conductive silicon layer 15 and second conductive silicon layer 14 are formed to have a hollow cylindrical shape. In this way, the hollow cylindrical body portion 4 having the outer peripheral surface 4b and the inner peripheral surface 4c provided along with the formation of the hollow portion 4d is formed. Further, a part 13a (third region) of one first conductivity type layer 13 remains over the entire region partitioned by the buried oxide film 2 (element isolation region).

  Instead of anisotropic dry etching, it may be formed as follows. First, the surface of the other second conductivity type silicon layer 15 is annealed at a high temperature to form a silicon oxide film thicker than the natural oxide film, thereby forming a hard mask layer. Next, after applying a photoresist film on the hard mask layer, exposure is performed using a desired photo mask to form a pattern of the photoresist film on the hard mask layer. Thereafter, using this photoresist film pattern as a mask, the hard mask layer made of a silicon oxide film is removed by dry etching. Next, anisotropic wet etching is performed with an alkaline solution such as TMAH (Tetra Methyl Ammonium Hydroxide), and the other first conductive silicon layer 15, second conductive silicon layer 14, and one first conductive silicon. Remove except about 10 nm below the bottom of layer 13. Also by doing in this way, the hollow cylindrical body part 4 which has the outer peripheral surface 4b and the inner peripheral surface 4c provided with formation of the hollow part 4d can be formed.

  Next, in FIG. 6, an interlayer insulating film 6 such as a silicon oxide film is formed so as to cover the entire surface of the silicon substrate 1. Specifically, it is deposited by a CVD method using a gas source of silicon oxide such as TEOS (Tetra ethoxysilane). Alternatively, a low dielectric constant Low-K material or the like may be formed by a method such as SOG (Spin On Glass).

Next, in FIG. 7, the unevenness on the upper surface of the interlayer insulating film 6 is polished and planarized by CMP (Chemical Mechanical Polishing), and then etching is performed. At this time, the upper surface of the interlayer insulating film 6 is positioned so as to be lowered by about 3 to 7 nm toward the semiconductor substrate 1 from the boundary between the second conductivity type silicon layer 14 and the first conductivity type N type silicon layer 13. Etching is controlled.

Next, in FIG. 8, a gate insulating film 7 is provided on the entire surface of the body portion 4 exposed from the interlayer insulating film 6 by forming a silicon oxide film having a thickness of 1 to 10 nm by CVD or annealing in an oxidizing atmosphere. As the gate insulating film 7, a High-K film such as HfO ₂ which is a high dielectric constant material may be formed. Alternatively, a stacked film including a plurality of films containing nitrogen or the like may be formed.

  Next, as shown in FIG. 9, a polysilicon film 8a into which an impurity such as phosphorus is introduced is laminated on the interlayer insulating film 6 and the gate insulating film 7, and then the surface is planarized by CMP. The polysilicon film 8a is also filled in the hollow portion 4d.

  Next, as shown in FIG. 10, the polysilicon film 8a is etched back so that the upper surface of the polysilicon film 8a extends from the boundary between the second conductivity type silicon layer 14 and the other first conductivity type silicon layer 15 to the other. After being positioned at a height of about 3 to 7 nm on the first conductivity type silicon layer 15 side, dry etching is performed using the patterned photoresist film as a mask to form the gate electrode 8. The outer shape of the gate electrode 8 does not necessarily have to be similar to the silicon cylinder on which the body portion 4 is formed. The gate electrode 8 includes an inner gate electrode 8 a formed in the hollow portion 4 d that is inside the body portion 4 and an outer gate electrode 8 b formed outside the body portion 4.

  Next, as shown in FIG. 11, an interlayer insulating film 9 is formed using a silicon oxide film or the like so as to cover the gate electrode 8, the interlayer insulating film 6 and the body portion 4. A Low-K film (low dielectric constant film) or the like may be used instead of the silicon oxide film. The upper surface of the interlayer insulating film 9 is planarized by CMP.

  Next, as shown in FIG. 12, after an opening (through hole) is formed in the interlayer insulating film 9, a contact plug connected to each electrode of the transistor is formed by filling polysilicon or the like into which impurities are introduced. . That is, the plug 10 is connected to the lead portion 3a (the remaining portion 13a of one first conductive silicon layer 13) of the first region 3, and the second region (the other first conductive silicon layer 15) 5 is connected. A plug 11, a plug 12 connected to the inner gate electrode 8a in the hollow portion 4d, and a plug 13 connected to the outer gate electrode 8b of the body portion 4 are formed. Note that tungsten (W) or the like may be buried instead of polysilicon to form a contact plug.

  Thereafter, a wiring layer for connecting each contact plug is formed using aluminum (Al), copper (Cu), tungsten, or the like, thereby completing the semiconductor device (vertical SGT) of the present invention. The threshold voltage of the transistor can be set to a desired value by adjusting the impurity concentration of the second conductivity type silicon layer 14. In this way, the semiconductor device 1 of the present embodiment is obtained.

  The semiconductor device shown in FIG. 12 includes a semiconductor substrate 1, a hollow cylindrical body portion 4 that protrudes from the semiconductor substrate 1 and has at least a channel region 4a, and a lower portion of the body portion 4 (the semiconductor with respect to the channel region 4a). A first region 3 formed on the substrate 1 side, a second region 5 formed on the upper portion of the body portion 4 (on the side opposite to the semiconductor substrate 1 with respect to the channel region 4a), and a first region And a gate insulating film 7 formed on the outer peripheral surface 4b and the inner peripheral surface 4c of the hollow cylindrical body portion 4 including the channel region 4a. And a gate electrode 8 formed so as to face the channel region 4a with the gate insulating film 7 interposed therebetween.

  A semiconductor substrate 1 is provided with a buried oxide film 2 having an STI structure, and a body portion 4 from which a part of the semiconductor substrate 1 protrudes is formed in a portion other than the formation region of the buried oxide film 2. Has been. As shown in FIG. 2, the body part 4 is composed of a cylindrical silicon pillar having a hollow part 4d at the center.

  The body part 4 has a second region 5 formed in the upper part thereof, and a first region 3 formed in the lower part thereof. Impurities in the lead portion 3a connected to the first region 3 may be diffused to the semiconductor substrate 1 side. A portion sandwiched between the first and second regions 3 and 5 is a channel region 4a. Thus, the body part 4 shown in FIG. 12 includes the channel region 4a and the first and second regions 3 and 5. The channel region 4a is exposed on the outer peripheral surface 4b and the inner peripheral surface 4c of the body portion 4, and a gate insulating film 7 is formed so as to cover the exposed channel region 4a. The gate insulating film 7 is formed so as to cover the entire hollow body portion 4.

  A gate electrode 8 is formed on the semiconductor substrate 1 so as to face the channel region 4a with the gate insulating film 7 interposed therebetween. The gate electrode 8 is also formed inside the hollow portion 4d, and is opposed to the channel region 4 via the gate insulating film 7 formed in the hollow portion 4d. That is, the gate electrode 8 includes an inner gate electrode 8a formed in the hollow portion 4d that is the inside of the body portion 4, and an outer gate electrode 8b formed outside the body portion 4, and each gate electrode 8a , 8b can be applied with the same or different gate voltages.

  In the semiconductor device of this embodiment, since the gate electrode 8 is provided inside and outside the body portion 4, it is possible to increase the on-current while suppressing the short channel effect. Further, by reducing the thickness of the channel region 4a (the distance between the inner and outer gate electrodes 8a and 8b) of the body portion 4, the channel region 4a can be easily depleted in the off state. Leak ionization in the state can be kept low. In addition, since the lead portion 3a connected to one of the first conductivity type silicon layers 13 (source / drain regions 3) in the lower layer portion of the body portion 4 extends from the lower portion of the transistor to the outside, Thus, it is possible to easily take out an electrode for supplying a potential to one region 3. Further, since only the gate insulating film 7 and the inner gate electrode 8a are formed in the hollow portion 4d of the body portion 4, the manufacture is very easy even when the miniaturization progresses.

[Second Embodiment]
Next, a method for manufacturing a semiconductor device (vertical SGT) and a manufactured semiconductor device according to the second embodiment of the present invention will be described. In addition, the description of the part which overlaps with description of 1st Embodiment may be abbreviate | omitted.
As shown in FIG. 13, after preparing a P-type silicon substrate 1 (semiconductor substrate) and forming an element isolation region having an STI structure using a buried insulating film 2, a second substrate such as phosphorus is formed using an ion implantation method. One conductivity type impurity (N-type impurity) is introduced to form one first conductivity type impurity region 20. The concentration of the N-type impurity is set to be about 1 × 10 ¹⁵ to 1 × 10 ²² atoms / cm ³ . Thereafter, the surface of the silicon substrate 1 is exposed.

Next, as shown in FIG. 14, a second conductivity type silicon layer 21 containing a P type impurity (concentration 1 × 10 ¹⁵ to 1 × 10 ²² atoms / cm ³ ) such as boron is formed as the second conductivity type impurity. After that, the second conductivity type silicon layer 21 and a part of the silicon substrate 1 are patterned into a hollow cylindrical shape. Thereby, the body part 4 is formed. At this time, the etching is controlled so that a part of the lower first conductivity type impurity region 20 remains.

Next, as shown in FIG. 15, an N-type impurity (first conductivity type impurity) such as phosphorus is introduced into the upper portion of the second conductivity type silicon layer 21 by ion implantation, and the other first conductivity type impurity is introduced. Region (N-type impurity region) 22 is formed. The concentration of the N-type impurity is set to be about 1 × 10 ¹⁵ to 1 × 10 ²² atoms / cm ³ . At this time, an N-type impurity (first conductivity type impurity) is also implanted into one of the first conductivity type impurity regions 20 not covered with the element isolation region 2, so that a new N type impurity region 23 is formed. The In FIG. 15, for the sake of explanation, a boundary line is shown between the regions 20 and 23. However, in reality, the boundary is not clear, and both are integrated.

  Note that the first conductivity type impurity region 22 may be formed by ion implantation before patterning the body portion shown in FIG. Further, ion implantation for forming the N-type impurity region 23 may be performed in a process different from the formation of the first conductivity-type impurity region 22. By separating the formation process of the first conductivity type impurity region 22 and the N type impurity region 23, the impurity concentration of each layer can be set optimally. That is, by increasing only the concentration of the N-type impurity region 23, it is possible to reduce the wiring resistance of the lead portion (3a) without affecting the transistor characteristics.

  Next, as shown in FIG. 16, an interlayer insulating film 24 is formed on the semiconductor substrate 1 by depositing a silicon oxide film and then etching back the silicon oxide film. Etching is performed so that the upper surface of the interlayer insulating film 24 is positioned about 3 to 7 nm from the boundary between the second conductivity type silicon layer 21 and one first conductivity type impurity region 20 to the first conductivity type impurity region 20 side. Take control.

  Next, as shown in FIG. 17, the gate insulating film 25 and the gate electrode 26 are formed in the same manner as in the first embodiment.

  Next, as shown in FIG. 18, after forming the interlayer insulating film 27 using a silicon oxide film or the like, contact plugs 28, 29, 30, and 31 connected to the respective electrodes of the transistor are formed. Thereafter, if a wiring layer to be connected to each contact plug is formed, the semiconductor device of this embodiment is completed.

  The semiconductor device shown in FIG. 18 includes a semiconductor substrate 1, a hollow cylindrical body portion 4 that protrudes from the semiconductor substrate 1 and has at least a channel region 4 a (second conductivity type silicon layer 21), and the body portion 4. The first region 3 (one first conductivity type impurity region 20) formed in the lower part (on the side of the semiconductor substrate 1 with respect to the channel region 4a) and the upper part of the body part 4 (the semiconductor substrate 1 with respect to the channel region 4a). A hollow cylindrical shape including a second region 5 (the other first conductivity type impurity region 22) formed on the opposite side of the first region 3, a lead portion 3a connected to the first region 3, and a channel region 4a. A gate insulating film 25 formed on the outer peripheral surface 4b and the inner peripheral surface 4c of the body portion 4 and a gate electrode 26 formed so as to face the channel region 4a through the gate insulating film 25. Has been.

The body part 4 has a second region 5 formed in the upper part thereof, and a first region 3 formed in the lower part thereof. The first region 3 is connected to the lead portion 3a. A portion sandwiched between the first and second regions 3 and 5 is a channel region 4a. In this way, the body portion 4 shown in FIG. 18 includes the channel region 4a and the first and second regions 3 and 5. The channel region 4a is exposed on the outer peripheral surface 4b and the inner peripheral surface 4c of the body portion 4, and a gate insulating film 25 is formed so as to cover the exposed channel region 4a. The gate insulating film 25 is formed so as to cover the entire hollow body portion 4.
Further, the lead portion 3 a (third region) is formed of a fourth region 3 b located immediately below the body portion 4 and a fifth region 3 c located other than directly below the body portion 4. And the thickness of the semiconductor layer which comprises the 5th area | region 3c is larger than the thickness of the semiconductor layer which comprises the 4th area | region 3b.

A gate electrode 26 is formed on the semiconductor substrate 1 so as to face the channel region 4a with a gate insulating film 25 interposed therebetween. The gate electrode 26 is also formed inside the hollow portion 4d, and is opposed to the channel region 4 via the gate insulating film 25 formed in the hollow portion 4d. That is, the gate electrode 26 includes an inner gate electrode 26a formed in the hollow portion 4d that is inside the body portion 4, and an outer gate electrode 26b formed outside the body portion 4, and each gate electrode 26a 26b can be applied with the same or different gate voltages.
A potential can be supplied to the first region 3 of the semiconductor device via a contact plug 28 connected to the lead portion 3a.

[Third Embodiment]
Next, a semiconductor device manufacturing method according to the third embodiment of the present invention will be described with reference to FIGS. In addition, the description of the part which overlaps with description of 1st Embodiment may be abbreviate | omitted.
First, as shown in FIG. 19, a P-type silicon substrate 1 is prepared, an element isolation region having an STI structure is formed using the buried insulating film 2, and then the surface of the silicon substrate 1 is exposed. Thereafter, a second conductive silicon layer 30 (P-type silicon layer) containing P-type impurities (concentration 1 × 10 ¹⁵ to 1 × 10 ²² atoms / cm ³ ) is formed and patterned into a cylindrical shape. Thus, the body part 4 is formed. At this time, the etching is controlled to end when the surface of the underlying silicon substrate 1 is exposed.

Next, as shown in FIG. 20, an N-type impurity such as phosphorus is introduced by using an ion implantation method, and one first conductivity type impurity region 31 (N Type impurity region). The concentration of the N-type impurity is set to be about 1 × 10 ¹⁵ to 1 × 10 ²² atoms / cm ³ . At this time, impurities are also introduced into the surface of the silicon substrate 1 that is not covered with the second conductivity type silicon layer 30 and the buried oxide film 2, and a lead portion (third region) connected to the first region and A second conductivity type impurity region 31a is formed.

  Next, as shown in FIG. 21, N-type impurities are diffused from the second conductivity type impurity region 31a by annealing in a high-temperature nitrogen atmosphere of about 600 to 900.degree. When the P-type impurity concentration of the second conductivity type silicon layer 30 (P-type silicon layer) and the silicon substrate 1 is lower than the impurity concentration of the second conductivity-type impurity region 31a (N-type impurity region), the N-type region Diffusion of impurities proceeds in the direction in which the film expands. An N-type silicon region newly formed by diffusion is indicated by 32. Due to the diffusion of the N-type impurity, a new N-type silicon region 32 is also formed between the adjacent N-type silicon regions 31 a (below the body portion 4), and the second conductivity-type (P-type) silicon layer 30 is formed under the second conductive type (P-type) silicon layer 30. 1 region 32 is formed. At this time, the N-type impurity in the N-type silicon region 31 a is diffused toward the upper portion of the body portion 4. Therefore, the boundary between the second conductivity type silicon layer 30 and the N type silicon layer in the lower part of the body part 4 is located above the main surface 1 a of the semiconductor substrate 1. The second conductivity type silicon layer 30 sandwiched between the newly formed N-type silicon region 32 becomes a channel region.

  Next, as shown in FIG. 22, after forming an interlayer insulating film 34 on the surface of the silicon substrate 1, a gate insulating film 35 and a gate electrode 36 are formed in the same manner as in the first embodiment.

  Next, as shown in FIG. 23, after forming an interlayer insulating film 37 using a silicon oxide film or the like, contact plugs 38, 39, 40, and 41 connected to the respective electrodes of the transistor are formed. Thereafter, if a wiring layer to be connected to each contact plug is formed, the transistor of this embodiment is completed.

  The semiconductor device shown in FIG. 23 includes a semiconductor substrate 1, a hollow cylindrical body portion 4 that protrudes from the semiconductor substrate 1 and has at least a channel region 4a, and a lower portion of the body portion 4 (the semiconductor with respect to the channel region 4a). A first region 3 formed on the substrate 1 side, a second region 5 formed on the upper portion of the body portion 4 (on the side opposite to the semiconductor substrate 1 with respect to the channel region 4a), and a first region 3, a gate insulating film 35 formed on the outer peripheral surface 4 b and the inner peripheral surface 4 c of the hollow cylindrical body portion 4 including the channel region 4 a, and a gate insulating film 35. And a gate electrode 36 formed so as to face the channel region 4a. The lead portion 31a is formed below the main surface 1a of the semiconductor substrate 1 (inside the semiconductor substrate 1).

  The body part 4 has a second region 5 formed in the upper part thereof. A portion sandwiched between the first and second regions 3 and 5 is a channel region 4a. In this way, the body portion 4 shown in FIG. 23 includes the channel region 4a and the first and second regions 3 and 5. The channel region 4a is exposed on the outer peripheral surface 4b and the inner peripheral surface 4c of the body portion 4, and a gate insulating film 35 is formed so as to cover the exposed channel region 4a. The gate insulating film 35 is formed so as to cover the entire hollow body portion 4.

  A gate electrode 36 is formed on the semiconductor substrate 1 so as to face the channel region 4a with a gate insulating film 35 interposed therebetween. The gate electrode 36 is also formed inside the hollow portion 4d, and is opposed to the channel region 4 through the gate insulating film 35 formed in the hollow portion 4d. That is, the gate electrode 36 is composed of an inner gate electrode 36a formed in the hollow portion 4d that is inside the body portion 4, and an outer gate electrode 36b formed outside the body portion 4, and each gate electrode 8a , 8b can be applied with the same or different gate voltages.

The operation characteristics of the semiconductor device according to the present invention described above will be described below.
FIG. 24 shows the electrical characteristics of the drain current (vertical axis) with respect to the voltage (horizontal axis) applied to the outer gate electrode. The drain voltage was set to 1.2V. The gate voltage (InGate) applied to the inner gate electrode is changed from -1.5V to + 1.5V. In the off state, for example, when both the inner and outer gate electrodes are set to 0 V, the drain current (off current) can be 0.1 pA or less.

  FIG. 25 shows the electrical characteristics of the drain current (vertical axis) when the drain voltage (horizontal axis) is applied from 0 to 5V. FIG. 25A shows a case where a gate voltage of 0.5 to 3 V is applied only to the outer gate electrode while the inner gate electrode is fixed at 0V. FIG. 25B shows a case where a gate voltage of 0.5 to 3 V is applied to both the inner gate electrode and the outer gate electrode. Comparing FIG. 25, it can be seen that by applying a voltage to the inner and outer gate electrodes at the same time, a drain current (on-current) that is about twice that of the case where a voltage is applied only to the outer gate electrode flows.

  In the present invention, by controlling the inner and outer gate electrodes, it is possible to easily improve the on-current while keeping the off-current small.

  For memory cells, multiple semiconductor devices such as integrated circuits, power devices, PRAM (phase change memory) memory cells that require a large amount of on-current, and DRAM memory cells that take advantage of the excellent off-current characteristics are arranged. Utilizing the excellent heat dissipation characteristics of vertical SGTs, such as ultra-high-speed integrated circuits, CPUs operating at a clock frequency of 10 GHz or higher, taking advantage of the ability to maintain on / off characteristics even with ultra-short channel selection transistors Integrated circuits that can handle even harsh conditions. These are integrated circuits for controlling automobile engines, integrated circuits for satellites for space, and the like.

FIG. 1 is a schematic cross-sectional view illustrating a basic form of a semiconductor device of the present invention. FIG. 2 is a schematic cross-sectional view corresponding to the line A-A ′ of FIG. 1. FIG. 3 is a schematic cross-sectional view for explaining the method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 4 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 5 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 7 is a schematic cross-sectional view for explaining the method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 8 is a schematic cross-sectional view for explaining the method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 9 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 10 is a schematic cross-sectional view for explaining the method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 11 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 12 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 13 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 14 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 15 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 16 is a schematic cross-sectional view for explaining the method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 17 is a schematic cross-sectional view for explaining the method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 18 is a schematic cross-sectional view for explaining the method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 19 is a schematic cross-sectional view for explaining the method for manufacturing a semiconductor device according to the third embodiment of the present invention. FIG. 20 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to the third embodiment of the present invention. FIG. 21 is a schematic cross-sectional view for explaining the method for manufacturing a semiconductor device according to the third embodiment of the present invention. FIG. 22 is a schematic cross-sectional view for explaining the method for manufacturing a semiconductor device according to the third embodiment of the present invention. FIG. 23 is a schematic cross-sectional view for explaining the method for manufacturing a semiconductor device according to the third embodiment of the present invention. FIG. 24 is a graph showing the electrical characteristics of the semiconductor device of the present invention, showing the electrical characteristics of the drain current (vertical axis) with respect to the voltage (horizontal axis) applied to the outer gate electrode. FIG. 25 is a graph showing electrical characteristics of the semiconductor device of the present invention. FIG. 25A shows a case where a gate voltage of 0.5 to 3 V is applied only to the outer gate electrode while the inner gate electrode is fixed to 0 V. (B) is a graph showing the electrical characteristics when a gate voltage of 0.5 to 3 V is applied to both the inner gate electrode and the outer gate electrode. FIG. 26 is a schematic cross-sectional view showing a modification of the semiconductor device shown in FIG. FIG. 27 is a schematic cross-sectional view showing a conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Embedded insulating film 3, 5, 20, 22, 31, 32 ... 1st area | region 3a ... Lead-out part (3rd area | region)
4, 21, 30 ... body part 4a ... channel region 5 ... second regions 6, 9, 27 ... interlayer insulating films 24, 34 ... interlayer insulating films 7, 25, 35 ... gate insulating films 8, 26, 36 ... gates Electrode 8a ... polysilicon layer 10, 11, 12, 13, 28, 29, 30, 31, 38, 39, 40, 41 ... contact plug

Claims (9)

A semiconductor body formed in a hollow cylindrical shape;
A first region formed under the body portion and serving as one of a source and drain region;
A second region formed on the body portion and serving as the other of the source and drain regions;
A channel region formed in a region sandwiched between the first region and the second region of the body portion;
A gate electrode formed so as to cover an inner peripheral surface and an outer peripheral surface of the channel region via a gate insulating film;
A semiconductor device, comprising: a third region formed below the body portion so as to be in contact with the first region and made of a semiconductor layer having the same conductivity type as that of the first region.   The semiconductor device according to claim 1, wherein the third region is provided so as to extend outward from an outer periphery of the body portion.   The semiconductor device according to claim 1, wherein a potential is supplied to the first region via the third region. The third region is formed of a fourth region located immediately below the body portion and a fifth region located other than directly below the body portion;
4. The semiconductor device according to claim 1, wherein a thickness of the semiconductor layer in the fifth region is larger than a thickness of the semiconductor layer in the fourth region. 5.   5. The semiconductor device according to claim 1, wherein the third region is formed below a main surface of the semiconductor substrate. On the semiconductor substrate,
A first step of forming a first semiconductor layer of a first conductivity type;
A second step of forming a second semiconductor layer of a second conductivity type on the first semiconductor layer;
Forming a third semiconductor layer of the first conductivity type on the second semiconductor layer;
A fourth step of etching the remaining portion of the first semiconductor layer and the second and third semiconductor layers to form a hollow cylindrical body portion while leaving a part of the first semiconductor layer; A fifth step of forming a gate insulating film so as to cover at least the inner peripheral surface and the outer peripheral surface of the second semiconductor layer of the body portion;
A sixth step of forming a gate electrode in the hollow portion and the outer peripheral portion of the body portion;
A method for manufacturing a semiconductor device, comprising:   7. The first, second, and third semiconductor layers are formed by crystal growth of a silicon layer while mixing a raw material gas containing impurities of a corresponding conductivity type, respectively. Semiconductor device manufacturing method.   The method of manufacturing a semiconductor device according to claim 6, wherein the first semiconductor layer is formed by ion-implanting a first conductivity type impurity into a surface of the semiconductor substrate. Forming a hollow conductive cylindrical body portion of the second conductivity type so as to protrude from the main surface of the semiconductor substrate;
Introducing a first conductivity type impurity into the main surface of the semiconductor substrate not covered with the body portion simultaneously with introducing a first conductivity type impurity into the upper portion of the body portion;
A step of thermally diffusing a first conductivity type impurity introduced into the main surface of the semiconductor substrate to form a first conductivity type impurity region under the body portion;
Forming a gate electrode on a hollow portion and an outer peripheral portion of the body portion with a gate insulating film interposed therebetween, and a method for manufacturing a semiconductor device.

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