JP5551350B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor integrated circuit of SOI (S ilicon O n I nsulator ) structure, particularly in the semiconductor substrate (bulk wafer), the ease of manufacturing process, low cost distortion of increased electron and hole mobility An SOI substrate is formed, and on this strained SOI substrate, not only a semiconductor integrated circuit consisting of a single MIS field effect transistor (MISFET) but also a CMOS (complementary MOS) type consisting of N channel and P channel MIS field effect transistors. The present invention relates to the formation of a semiconductor integrated circuit including a high-speed, low-power, high-performance, high-reliability, and highly-integrated short channel MIS field effect transistor that can be completely compatible with the above-described semiconductor integrated circuit.

Figure 38 is a schematic side sectional view of a conventional semiconductor device, SIMOX (S eparation by Im planted Ox ygen) Method semiconductor CMOS type consisting of N-channel and P-channel MIS field effect transistor of the strained SOI structure formed using 1 shows a part of an integrated circuit, 51 is a p-type Si substrate, 52 is a p-type SiGe layer, 53 is an n-type SiGe layer, 54 is a buried oxide film (SiO ₂ ), and 55 is an element isolation region ( SiO ₂ ), 56 is a p-type strained Si layer, 57 is an n-type strained Si layer, 58 is an n ⁺ type source / drain region, 59 is an n type source / drain region, 60 is a p ⁺ type source / drain region, 61 is Gate oxide film (SiO ₂ ), 62 is a gate electrode (WSi / polySi), 63 is a sidewall (SiO ₂ ), 64 is a PSG film, 65 is a barrier metal (Ti / TiN), 66 is a conductive plug (W), 67 represents a barrier metal (Ti / TiN), 68 represents an Al wiring, and 69 represents a barrier metal (Ti / TiN).
In the figure, an element is inserted through a buried oxide film 54 (SIMOX method) formed by high-temperature heat treatment by implanting oxygen ions into a p-type SiGe layer 52 laminated on a p-type silicon substrate 51. A p-type strained SOI substrate composed of a p-type strained Si layer 56 on a p-type SiGe layer 52 isolated in an island shape by an isolation region (SiO ₂ ) 55 and an n-type on an n-type SiGe layer 53 An n-type strained SOI substrate composed of a strained Si layer 57 is formed, and an n-type source / drain region 59 self-aligned on the gate electrode 62 and self-aligned on the sidewall 63 are formed on the p-type strained SOI substrate. n ⁺ -type source drain region consisting of 58 n-channel LDD (L ightly D oped D rain ) MIS field effect transistor structure is formed, the n-type strained SOI substrate of the self-aligned formed in the gate electrode 62 side was Self-aligned to wall 63 MIS field effect transistor of the formed p ⁺ -type source and drain regions consisting of 60 P-channel LDD structure are formed. Further, the n ⁺ -type source / drain region 58 and the p ⁺ -type source / drain region 60 are respectively provided with a barrier metal (Ti / TiN) (67, 67) up and down via a barrier metal (Ti / TiN) 65 and a conductive Bragg (W) 66, respectively. 69) and is connected to an Al wiring 68 having a desired voltage.
Therefore, the junction capacitance can be reduced by forming a source / drain region surrounded by an insulating film, the depletion layer capacitance can be reduced by completely depleting a thin-film strained SOI substrate, the breakdown voltage of the source / drain region can be improved, and the subthreshold characteristics can be achieved. Compared to CMOS consisting of MIS field-effect transistors formed on a normal bulk wafer by reducing threshold voltage due to improvement, removal of contact region to strained SOI substrate, etc., higher speed, lower power and higher integration are possible Become.
In addition, since a MIS field-effect transistor can be formed on a strained SOI substrate in which a strained Si layer is stacked on a SiGe layer, strain can be formed in the Si layer due to tensile stress caused by the SiGe layer having a large lattice constant, thereby increasing mobility. Therefore, the speed can be increased.
However, since the ground voltage is applied to the conductor (p-type silicon substrate) under the SOI substrate, the back channel of the N-channel MIS field effect transistor formed on the p-type SOI substrate is maintained in the off state. Since the back channel of the P-channel MIS field effect transistor formed on the type SOI substrate is always turned on, in the N-channel MIS field effect transistor, even if the voltage applied to the gate electrode is the ground voltage, the power supply voltage However, although the P-channel MIS field effect transistor operates normally, current flows through the front channel and the back channel at the ground voltage, and the front channel is off (no current flows) at the power supply voltage. There is a drawback that the channel has a minute current leak and it is inevitable that it malfunctions. It was.
In addition, since both the N-channel MIS field-effect transistor and the P-channel MIS field-effect transistor are formed on a strained SOI substrate in which a strained Si layer is stacked on a SiGe layer, improvement in electron and hole mobility can be achieved. Although the speed is high, the mobility of electrons and holes is inherently more than doubled, so there is a disadvantage that the switching speed on / off is not well balanced. The channel width of the MIS field effect transistor has to be widened, making it difficult to achieve high integration.
Also, by forming a conventional LDD structure as a means of improving the deterioration of transfer conductor cis over the lifetime due to the hot carrier effect caused by the strong electric field near the drain, which is peculiar to the N channel MIS field effect transistor, Since the short channel MIS field effect transistor is formed, a low concentration region is formed also in an unnecessary source region, and the resistance of the source region cannot be reduced, and the source / drain region is self-aligned with the gate electrode. Therefore, a high-temperature heat treatment is required for activating the source / drain region, so that a low-melting point metal gate electrode having a low resistance cannot be formed. there were.
In addition, since the channel length that determines various characteristics of the MIS field effect transistor depends on the control of the gate length by photolithography technology, it is very difficult to control the manufacturing variation in a large-diameter wafer, and the characteristics of the MIS field effect transistor are Since it is difficult to control within an allowable range, there is a drawback that it is difficult to achieve high speed and high performance.
In addition, since the SIMOX method is used as a means for creating an SOI structure, it is necessary to purchase an extremely expensive high-dose ion implantation machine, and a long-time manufacturing process for implanting high-dose oxygen ions. The problem of high cost due to the need for high-density wafers, the problem of instability of characteristics due to the repair of crystal defects by oxygen ion implantation in the use of large-diameter wafers of 10 to 12 inches, and the thick embedding even when ion implantation of high dose oxygen There are also disadvantages such as the problem that it is difficult to reduce the capacitance with the lower layer region because an oxide film cannot be obtained.

The problem to be solved by the present invention is to form a MIS field effect transistor on a fully-depleted thin film strained SOI substrate as shown in the prior art, so that the junction capacitance can be reduced, but the resistance of the source region In addition, the high speed could not be achieved despite the fact that the resistance of the gate electrode could not be reduced, and a voltage different from the voltage applied to the gate electrode was applied when forming the CMOS or under the SOI substrate. High reliability due to the inability to prevent back channel leakage when a conductive material (a silicon substrate in the conventional example) is present, and when a CMOS is formed, a strain in which a strained Si layer is stacked on a SiGe layer Since N-channel and P-channel MIS field-effect transistors having almost the same structure are formed on the SOI substrate, the mobility of electrons and holes can be reduced. Although the above can be achieved and the speed is increased, the on-off characteristics of the switching speed cannot be improved, and the channel length that determines various characteristics of the MIS field effect transistor is set to the gate length by photolithography technology. Because it depends on the control, the controllability of the manufacturing variation in the large-diameter wafer is poor, and it is difficult to achieve high speed and high performance due to the difficulty in obtaining the MIS field effect transistor having stable characteristics. Since the SOI substrate is formed by the SIMOX method in order to form the structure, the cost is considerably high. Therefore, it can be used only for products with high added value and can be applied to inexpensive general-purpose products. That was scarce.

The object is to provide a semiconductor substrate, an insulating film provided on the semiconductor substrate, and a first lateral epitaxial film selectively provided on the insulating film in a direction parallel to the main surface of the semiconductor substrate. A semiconductor layer, a longitudinal epitaxial semiconductor layer selectively provided on the first lateral epitaxial semiconductor layer in a direction perpendicular to a main surface of the semiconductor substrate, and an epitaxial semiconductor layer in the longitudinal direction. Second lateral strained epitaxial semiconductor layers having different lattice constants provided around the side surfaces, and drain regions provided above the longitudinal epitaxial semiconductor layers and the second lateral strained epitaxial semiconductor layers (Or source region) and the vertical epitaxy relative to the drain region (or source region) spaced from the drain region (or source region). A source region (or drain region) provided under the first semiconductor layer and the second lateral strained epitaxial semiconductor layer, and the longitudinal epitaxial semiconductor layer and the second lateral strained epitaxial semiconductor layer. A source region (or drain region) provided in the first lateral epitaxial semiconductor layer in contact with a source region (or drain region) provided in a lower portion; and a second lateral strained epitaxial semiconductor layer. This is solved by the semiconductor device of the present invention comprising a vertical (vertical operation) MIS field-effect transistor having a strained SOI structure comprising a gate electrode provided on a side surface through a gate insulating film.

As described above, according to the present invention, a lateral direction selectively formed on an insulating film by an easy technique using a normal semiconductor substrate without using a strained SOI substrate formed by the SIMOX method. In addition, a strained SOI substrate can be formed by using a vertical epitaxial semiconductor layer, and a drain region, a channel region, and a source region can be formed on the strained SOI substrate, so that a fully depleted strained SOI structure can be easily formed. The threshold voltage can be reduced by reducing the junction capacitance of the drain region (substantially zero), reducing the depletion layer capacitance, improving the breakdown voltage of the source / drain region, and improving the subthreshold characteristics.
In addition, since a Si layer that has a side-by-side structure or a stacked structure can be formed by simple technology and is in contact with the SiGe layer, a strained Si layer can be formed by the tensile stress caused by the SiGe layer having a large lattice constant, thereby increasing mobility. Can be speeded up.
Further, the channel length for determining various characteristics of the MIS field effect transistor can be determined by the growth thickness of the epitaxial semiconductor layer having good controllability and the diffusion of impurities by heat treatment without depending on the control of the gate length by the photolithography technique. In addition, a MIS field effect transistor having stable characteristics can be obtained even in a large-diameter wafer.
Further, since the channel region can be completely surrounded by the gate electrode, the back channel effect that is inevitably generated in either the N-channel MIS field-effect transistor or the P-channel MIS field-effect transistor, which is peculiar to the SOI structure CMOS, is completely achieved. It is possible to obtain a highly integrated MIS field effect transistor with an increased channel width because it has a high performance and high reliability with extremely excellent leakage characteristics, and the entire periphery can be made into a channel region. Can do.
Also, when forming a CMOS, the P-channel MIS field-effect transistor and the N-channel MIS field-effect transistor are different from each other while maintaining high integration so as to further improve the hole mobility and approach the electron mobility. Since the structure can be formed, a high switching speed with good on / off characteristics can be obtained.
Further, a low concentration region formed as a means for improving the deterioration of transfer conductance over the lifetime due to the hot carrier effect generated due to the strong electric field in the vicinity of the drain region peculiar to the N channel MIS field effect transistor is formed only in the drain region. Since it can be formed without being provided in the region, the resistance of the source region can be reduced, and the channel length can be made fine without degrading the breakdown voltage.
In addition, Ta ₂ O ₅ with a high dielectric constant can be used as the gate oxide film, so the gate oxide film can be made thicker, minimizing current leakage between the gate electrode and the strained Si layer, and reducing the gate capacitance. It is.
In addition, the source / drain regions that require high-temperature heat treatment to activate the impurity regions can be formed in a self-aligned manner before forming the gate electrode, so that low resistance, low melting point metal can be used without using polycrystalline silicon (semiconductor layer). Since the gate electrode made of (Al) can be formed, the resistance of the gate electrode wiring can be reduced and the depletion layer capacitance at the gate electrode can be removed, so that the power can be reduced by reducing the threshold voltage.
Further, each element (low concentration and high concentration drain region, high concentration source region, gate oxide film and gate electrode) can be finely formed in a self-aligned manner with the vertical epitaxial semiconductor layer.
Further, since the lower layer wiring can be formed before the strained SOI substrate is formed, the degree of freedom of the wiring can be increased, thereby enabling further higher integration.
That is, without using an expensive semiconductor substrate having a strained SOI structure (a semiconductor substrate formed by bonding two semiconductor substrates or a semiconductor substrate formed by the SIMOX method), an easy process (details are given in the manufacturing method). By using the strained SOI substrate formed by the lateral and vertical epitaxial semiconductor layers formed in the description), it has a channel surrounding type low resistance metal gate electrode having high speed, low power, high reliability, high performance and high integration. A vertical (vertical operation) MIS field effect transistor having a strained SOI structure or a strained SOI structure (horizontal operation) MIS field effect transistor having a low-resistance metal gate electrode can be obtained.
The present inventors named the art selective composite epitaxial growth method and (S elective C omplex E pitaxy) , abbreviated as hereinafter SCE.

The semiconductor device of the present invention is formed in the following form.
An opening is selectively provided in the insulating film provided on the semiconductor substrate, and a first vertical epitaxial semiconductor layer with a part of the side surface exposed is provided in the opening, and the first vertical semiconductor layer is provided. A first lateral epitaxial semiconductor layer is provided on the exposed portion of the side surface of the epitaxial semiconductor layer in the direction, the first vertical epitaxial semiconductor layer is removed, and an insulating film is embedded to be converted into an element isolation region . A second longitudinal epitaxial semiconductor layer is selectively provided on the first lateral epitaxial semiconductor layer, and a second lateral direction having a different lattice constant is formed on a side surface of the second longitudinal epitaxial semiconductor layer. A strained epitaxial semiconductor layer is provided, and a strained SOI substrate composed of a first lateral epitaxial semiconductor layer, a second longitudinal epitaxial semiconductor layer, and a second lateral strained epitaxial semiconductor layer is formed. High-concentration and low-concentration drain regions are provided above the second longitudinal epitaxial semiconductor layer and the second lateral strained epitaxial semiconductor layer, and the entire first lateral epitaxial semiconductor layer, A high-concentration source region is provided below the vertical epitaxial semiconductor layer and the second lateral strained epitaxial semiconductor layer, spaced from the drain region, and on the side surface of the second lateral strained epitaxial semiconductor layer. A vertical gate of a strained SOI structure in which a gate electrode is provided through a gate insulating film, and a wiring body having a barrier metal is connected to the drain region, the source region, and the gate electrode through a conductive plug having a barrier metal. A semiconductor integrated circuit composed of a type (vertical operation) MIS field effect transistor is formed.

Hereinafter, the present invention will be specifically described with reference to the illustrated embodiments.
Throughout the drawings, the same object is denoted by the same reference numeral. However, the diagonal lines in the side cross-sectional view are shown only on the main insulating film, the wiring is drawn including a misalignment of the front and rear, and the size in the horizontal and vertical directions is shown to show the main part of the invention. The exact dimensions are not shown.
FIG. 1 is a schematic sectional side view of a first embodiment of the semiconductor device of the present invention, and FIGS. 2 to 13 are process sectional views of the manufacturing method of the first embodiment of the semiconductor device of the present invention.
FIG. 1 shows a strained SOI substrate comprising a lateral (horizontal) epitaxial SiGe layer, a longitudinal (vertical) epitaxial SiGe layer, and a laterally epitaxial strained Si layer formed by selective compound epitaxial growth (SCE) using a silicon substrate. 1 shows a part of a semiconductor integrated circuit including a short-channel N-channel MIS field effect transistor formed, 1 is a p-type Si substrate of about 10 ¹⁵ cm ⁻³ , and 2 is a SOI / element isolation region of about 400 nm. Oxide film (SiO ₂ ), 3 is a p-type lateral epitaxial SiGe layer having a thickness of about 80 nm and a concentration of about 10 ¹⁶ cm ⁻³ , 4 is a buried insulating film (SiO ₂ ) for forming an element isolation region, and 5 is Nitride film (Si ₃ N ₄ ) of about 30 nm, 6 is an oxide film (SiO ₂ ) of about 10 nm, 7 is about 250 nm in height, about 30 nm in width, and p-type longitudinal epitaxial SiGe with a concentration of about 10 ¹⁶ cm ⁻³ Layer 8, 8 is about 25nm wide, p-type lateral epi of concentration about 10 ¹⁶ cm ^-3 Taxially strained Si layer, 9 is an n ⁺ type source region of about 10 ²⁰ cm ⁻³ , 10 is an n type drain region of about 10 ¹⁷ cm ⁻³ , 11 is an n ⁺ type drain region of about 10 ²⁰ cm ⁻³ , 12 Is a gate oxide film (Ta ₂ O ₅ / SiO ₂ ) of about 10 nm, 13 is a gate electrode (Al) of about 80 nm thickness, 14 is a mask layer (SiO ₂ ) for forming a gate electrode wiring, and 15 is about 200 nm Phosphorsilicate glass (PSG) film, 16 is about 20 nm nitride film (Si ₃ N ₄ ), 17 is about 400 nm oxide film (SiO ₂ ), 18 is about 20 nm etching stopper film (Si ₃ N ₄ ), 19 Is about 10 nm barrier metal (TiN), 20 is a conductive plug (W), 2l is about 500 nm interlayer insulating film (SiOC), 22 is about 10 nm barrier metal (TaN), and 23 is about 500 nm Cu wiring (Cu 24 includes a barrier insulating film (Si ₃ N ₄ ) of about 20 nm.
In this figure, a p-type lateral (horizontal) epitaxial SiGe layer 3 (the manufacturing method will be described in detail later) is provided on a p-type silicon substrate 1 via an oxide film (SiO ₂ ) 2. The SiGe layer 3 is insulated and isolated in an island shape by a buried insulating film (SiO ₂ ) 4 and an oxide film (SiO ₂ ) 2 for forming an element isolation region. A p-type longitudinal (vertical) epitaxial SiGe layer 7 is selectively provided on the insulated SiGe layer 3, and a p-type lateral epitaxial strain having a slightly small lattice constant is formed on the side surface of the SiGe layer 7. A Si layer 8 is provided around to form a strained SOI substrate. An n ⁺ -type drain region 11 and an n-type drain region 10 are provided above the SiGe layer 7 and the strained Si layer 8, and an n ⁺ -type source region is formed below the entire SiGe layer 3 and the SiGe layer 7 and the strained Si layer 8. 9 is provided, and a gate electrode (Al) 13 is provided around the side surface of the strained Si layer 8 via a gate oxide film (Ta ₂ O ₅ / SiO ₂ ) 12 to form an n ⁺ type drain region 11 and an n ⁺ type A vertical type of strained SOI structure in which a Cu wiring 23 having a barrier metal (TaN) 22 is connected to the source region 9 and the gate electrode 13 through a conductive plug (W) 20 having a barrier metal (TiN) 19 respectively. An (channel operation) N-channel MIS field effect transistor is formed. (Here, a p-type silicon substrate is used as the semiconductor substrate. However, since the MIS field-effect transistor is not directly formed on the silicon substrate, it may be p-type or n-type. )
Therefore, without using a strained SOI structure semiconductor substrate formed by the SIMOX method, a normal semiconductor substrate is used, and the lateral and vertical epitaxial semiconductor layers selectively formed on the insulating film are used as strained SOI substrates. Since a drain region, a channel region, and a source region can be formed on this strained SOI substrate, it is possible to easily form a fully depleted strained SOI structure, reducing the junction capacitance of the source / drain region (substantially zero), and depletion The threshold voltage can be reduced by reducing the layer capacitance, improving the breakdown voltage of the source / drain region, and improving the subthreshold characteristics.
In addition, since the Si layer can be formed by an easy technology and in contact with the SiGe layer, the strained Si layer can be formed by the tensile stress caused by the SiGe layer having a large lattice constant, so the mobility can be increased. Speeding up is possible.
Further, the channel length for determining various characteristics of the MIS field effect transistor can be determined by the growth thickness of the epitaxial semiconductor layer having good controllability and the diffusion of impurities by heat treatment without depending on the control of the gate length by the photolithography technique. In addition, a MIS field effect transistor having stable characteristics can be obtained even in a large-diameter wafer.
In addition, since the channel region can be completely surrounded by the gate electrode, it is possible to improve the back channel effect that is inevitably generated in the SOI-structure MIS field-effect transistor, and to achieve high performance and high reliability with extremely excellent leakage characteristics. In addition, since the entire periphery can be a channel region, a highly integrated MIS field effect transistor with an increased channel width can be obtained.
Further, a low concentration region formed as a means for improving the deterioration of transfer conductance over the lifetime due to the hot carrier effect generated due to the strong electric field in the vicinity of the drain region peculiar to the N channel MIS field effect transistor is formed only in the drain region. Since it can be formed without being provided in the region, the resistance of the source region can be reduced, and the channel length can be made fine without degrading the breakdown voltage.
In addition, Ta ₂ O ₅ with a high dielectric constant can be used as the gate oxide film, so the gate oxide film can be made thicker, minimizing current leakage between the gate electrode and the strained Si layer, and reducing the gate capacitance. It is.
In addition, the source / drain regions that require high-temperature heat treatment to activate the impurity regions can be formed in a self-aligned manner before forming the gate electrode, so that low resistance, low melting point metal can be used without using polycrystalline silicon (semiconductor layer). Since the gate electrode made of (Al) can be formed, the resistance of the gate electrode wiring can be reduced and the depletion layer capacitance at the gate electrode can be removed, so that the power can be reduced by reducing the threshold voltage.
Each element (low concentration and high concentration drain region, high concentration source region, gate oxide film and gate electrode) can also be finely formed in self-alignment with the strained Si layer.
That is, without using an expensive semiconductor substrate having a strained SOI structure (a semiconductor substrate formed by bonding two semiconductor substrates or a semiconductor substrate formed by a SIMOX method), an easy process (details are given in the manufacturing method). By using the strained SOI substrate formed by the lateral and vertical epitaxial semiconductor layers formed in the description), it has a channel surrounding type low resistance metal gate electrode having high speed, low power, high reliability, high performance and high integration. A vertical (vertical operation) MIS field effect transistor having a strained SOI structure can be obtained.

Next, a manufacturing method of the first embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. However, here, only the manufacturing method related to the formation of the semiconductor device of the present invention is described, and the description of the manufacturing method related to the formation of various elements (other transistors, resistors, capacitors, etc.) mounted on a general semiconductor integrated circuit is omitted. To do.
FIG.
The p-type silicon substrate 1 is oxidized at about 1000 ° C. to grow an oxide film (SiO ₂ ) 2 of about 500 nm. Next, using an ordinary photolithography technique, the oxide film (SiO ₂ ) 2 is anisotropically dry etched using a resist (not shown) as a mask layer to form an opening. Next, the resist (not shown) is removed. Next, a p-type longitudinal (vertical) epitaxial SiGe layer (containing about 10% Ge) 25 is grown on the exposed p-type silicon substrate 1 by chemical vapor deposition. Then SiGe layer 25 that protrudes from the flat surface to chemical mechanical polishing (abbreviated as C hemical M echanical P olishing after CMP), to flatten. Next, annealing is performed in a N ₂ atmosphere at about 1300 ° C., and the SiGe layer 25 is relaxed.
FIG.
Next, the SiGe layer 25 is anisotropic dry etched by about 20 nm to form a stepped portion. Next, a nitride film (Si ₃ N ₄ ) 26 of about 20 nm is grown by chemical vapor deposition. Next, chemical mechanical polishing (CMP) is performed, and a nitride film (Si ₃ N ₄ ) 26 is flatly embedded in the stepped portion. Next, using an ordinary photolithography technique, the oxide film (SiO ₂ ) 2 is selectively dry etched by about 150 nm using a resist (not shown) as a mask layer. Next, the resist (not shown) is removed. Next, a p-type lateral (horizontal) epitaxial SiGe layer (containing about 10% Ge) 3 is grown on the side surface of the exposed longitudinal epitaxial SiGe layer 25.
FIG.
Next, the upper surface of the p-type lateral epitaxial SiGe layer 3 is oxidized at about 900 ° C. to grow an oxide film (SiO ₂ ) 27 of about 10 nm. Next, using the oxide film (SiO ₂ ) 2 and the oxide film (SiO ₂ ) 27 as a mask layer, the nitride film (Si ₃ N ₄ ) 26 and the longitudinal epitaxial SiGe layer 25 are sequentially subjected to anisotropic dry etching, and the opening portion is formed. Form. (At this time, the p-type silicon substrate 1 is slightly etched, but there is no problem.)
FIG.
Next, an oxide film (SiO ₂ ) 4 of about 500 nm is grown by chemical vapor deposition. Next, chemical mechanical polishing (CMP) is performed, and an oxide film (SiO ₂ ) 4 is flatly embedded only in the opening portion. Thus, the initially formed vertical epitaxial SiGe layer 25 is removed by etching and replaced with the element isolation region buried oxide film (SiO ₂ ) 4 in a self-aligning manner. The lateral epitaxial SiGe layer 3 and the oxide film oxide film grown on the top surface of the _{(SiO 2) 2 (SiO 2} ) 4 is also removed. Then, oxidation is performed at about 1100 ° C. to reduce the thickness of the SiGe layer 3 and increase the Ge concentration (about 30%). (Because Ge does not easily diffuse into the oxide film, the Ge concentration in the SiGe layer increases.) Next, chemical mechanical polishing (CMP) is performed to remove the oxide film on the SiGe layer 3 and planarize.
FIG.
Next, a nitride film (Si ₃ N ₄ ) 5 of about 30 nm is grown by chemical vapor deposition. Next, an oxide film (SiO ₂ ) 6 of about 10 nm is grown by chemical vapor deposition. Next, a nitride film (Si ₃ N ₄ ) 28 of about 220 nm is grown by chemical vapor deposition. Next, using ordinary photolithography technology, using a resist (not shown) as a mask layer, a nitride film (Si ₃ N ₄ ) 28, an oxide film (SiO ₂ ) 6 and a nitride film (Si ₃ N ₄ ) 5 are sequentially formed. Anisotropic dry etching is performed to form an opening. Next, the resist (not shown) is removed. Next, by chemical vapor deposition, a p-type vertical (vertical) epitaxial SiGe layer (Ge concentration of about 30%) 7 having a width of about 30 nm is grown on the exposed p-type lateral epitaxial SiGe layer 3 by about 260 nm. Next, the exposed surface of the SiGe layer 7 is oxidized to grow an oxide film (SiO ₂ ) 29.
FIG.
Next, the entire surface of the nitride film (Si ₃ N ₄ ) 28 is anisotropically dry etched. Next, a p-type lateral epitaxial Si layer 8 having a width of about 25 nm is grown on the exposed side surface of the longitudinal epitaxial SiGe layer 7 by chemical vapor deposition.
FIG.
Next, the oxide film (SiO ₂ ) 29 is subjected to anisotropic dry etching. (At this time, the oxide film (SiO ₂ ) 6 is also etched away.) Next, an oxide film (not shown) for ion implantation of about 10 nm is grown by chemical vapor deposition. Next, boron ion implantation for controlling the threshold voltage is performed. Next, heat treatment is performed at about 1000 ° C., the concentration of the strained Si layer 8 and the SiGe layer 7 is controlled, and then phosphorus ion implantation for forming the n-type drain region 10 is performed. (At this time, ion implantation is performed with an acceleration energy as low as about 25 kev so that phosphorus is ion-implanted only into the upper surfaces of the strained Si layer 8 and the SiGe layer 7.) Next, n ⁺ -type source / drain regions (9, 11) Arsenic ions are implanted for formation. (Thus, the arsenic for forming the n ⁺ -type source / drain regions (9, 11) is ion-implanted in a self-aligned manner on the upper surfaces of the strained Si layer 8, the SiGe layer 7, and the SiGe layer 3 without a mask layer.) by annealing by (R apid T hermal P rocessing) , strained Si layer 8 and the upper part is diffused in the vertical direction n ⁺ -type drain region 11 and the n-type drain region 10 of the SiGe layer 7, SiGe layer 3 Then, an n ⁺ type source region 9 is formed which diffuses in the vertical and lateral directions and fills the entire SiGe layer 3, the SiGe layer 7 and the lower part of the strained Si layer 8, and then an oxide film for ion implantation (not shown). ) Isotropic dry etching.
FIG.
Next, a gate oxide film (Ta ₂ O ₅ / SiO ₂ ) 12 of about 10 nm is grown, and then Al 13 to be a gate electrode of about 80 nm is grown by sputtering. (A barrier metal (TiN) may be provided under the Al gate electrode.) Next, an oxide film (SiO ₂ ) 14 of about 130 nm is grown by chemical vapor deposition. Next, chemical mechanical polishing (CMP) is performed to remove the oxide film (SiO ₂ ) 14, Al 13 and the gate oxide film (Ta ₂ O ₅ / SiO ₂ ) 12 on the strained Si layer 8 and the SiGe layer 7 and planarize them. .
FIG.
Next, using an ordinary photolithography technique, the oxide film (SiO ₂ ) 14 is anisotropically dry etched using a resist (not shown) as a mask layer. Next, the resist (not shown) is removed. Next, using the remaining oxide film (SiO ₂ ) 14 as a mask layer, Al 13 and the gate oxide film (Ta ₂ O ₅ / SiO ₂ ) 12 are sequentially subjected to anisotropic dry etching. (The reason why the etching is performed using the oxide film (SiO ₂ ) 14 as a mask layer is to form the gate electrode wiring portion other than the side surface of the strained Si layer 8.)
FIG.
Next, PSG15 of about 200 nm is grown by chemical vapor deposition. Then, chemical mechanical polishing (CMP) is performed to remove the PSG 15 on the strained Si layer 8 and the SiGe layer 7 and planarize. Next, PSG15 is anisotropically etched by about 20 nm to form a stepped portion. Next, a nitride film (Si ₃ N ₄ ) 16 of about 20 nm is grown by chemical vapor deposition. Next, chemical mechanical polishing (CMP) is performed, and a nitride film (Si ₃ N ₄ ) 16 is flatly embedded in the stepped portion.
FIG.
Next, an oxide film (SiO ₂ ) 17 of about 400 nm is grown by chemical vapor deposition. Next, a nitride film (Si ₃ N ₄ ) 18 of about 20 nm is grown by chemical vapor deposition. Next, using a normal photolithography technique, the nitride film (Si ₃ N ₄ ) 18 and the oxide film (SiO ₂ ) 17 are sequentially subjected to anisotropic dry etching using the first resist (not shown) as a mask layer. (At this stage, a via is opened in a part of the n ⁺ -type drain region 11.) Then, using a normal photolithography technique, the mask layer of the first resist (not shown) is left as it is, and n ⁺ A second resist mask layer (not shown) that covers only the via portion of the mold drain region 11 is formed. Next, using the first and second resists (not shown) as mask layers, the nitride film (Si ₃ N ₄ ) 16, PSG 15, oxide film (SiO ₂ ) 14 and nitride film (Si ₃ N ₄ ) 5 are sequentially different. Isotropic dry etching. (Thus, vias are also opened in a part of the n ⁺ -type source region 9 and the gate electrode wiring 13.) Next, all resist (not shown) is removed.
FIG.
Next, TiN19 to be a barrier metal is grown by sputtering. Next, tungsten (W) 20 is grown by chemical vapor deposition. Next, a conductive plug (W) 20 having a barrier metal (TiN) 19 is formed by chemical mechanical polishing (CMP).
FIG.
Next, an interlayer insulating film (SiOC) 21 of about 500 nm is grown by chemical vapor deposition. Next, using an ordinary photolithography technique, the interlayer insulating film (SiOC) 21 is anisotropically dry-etched using a resist (not shown) as a mask layer to form an opening. (At this time, the nitride film (Si ₃ N ₄ ) 18 becomes an etching stopper film.) Next, the resist (not shown) is removed. Next, a barrier metal (TaN) 22 of about 10 nm is grown by chemical vapor deposition. Next, a Cu seed layer is grown by sputtering. Next, Cu of about 500 nm is grown by electrolytic plating. Next, chemical mechanical polishing (CMP) is performed, Cu is flatly embedded in the opening, and a Cu wiring 23 having a barrier metal (TaN) 22 is formed. Next, a nitride film (Si ₃ N ₄ ) 24 serving as a Cu barrier insulating film is grown by chemical vapor deposition, and a channel-enclosed low-resistance metal gate having a strained SOI structure by the selective composite epitaxial growth method (SCE) of the present invention. A vertical (vertical operation) N-channel MIS field effect transistor having electrodes is completed.

FIG. 14 shows a second embodiment of the semiconductor device according to the present invention. A lateral (horizontal) direction epitaxial SiGe layer and a longitudinal (vertical) direction epitaxial SiGe layer formed by selective composite epitaxial growth (SCE) using a silicon substrate. 1 shows a part of a semiconductor integrated circuit including a short-channel N-channel MIS field effect transistor formed on a strained SOI substrate composed of a laterally epitaxial strained Si layer, wherein 1 to 24 are the same as those in FIG. The lower layer wiring (WSi) 31 indicates an insulating film (SiO ₂ ).
In the figure, a lower layer wiring (WSi) 30 is provided under a p-type lateral epitaxial SiGe layer 3 in which an n ⁺ type source region 9 is formed, and a conductive material having a barrier metal (TiN) 19 at another location. A vertical (vertical operation) N-channel MIS field effect transistor having the same strained SOI structure as in FIG. 1 except that it is connected to a Cu wiring 23 having a barrier metal (TaN) 22 via a plug (W) 20. Is formed.
In this embodiment, the same effect as that of the first embodiment can be obtained, and the lower layer wiring can be used. Therefore, the degree of freedom of the wiring can be increased, thereby enabling further higher integration.

FIG. 15 shows a third embodiment of the semiconductor device of the present invention, which is a lateral epitaxial Si layer, a lateral epitaxial SiGe layer, and a longitudinal epitaxial strained Si formed by selective composite epitaxial growth (SCE) using a silicon substrate. 1 shows a part of a semiconductor integrated circuit including a short-channel N-channel MIS field effect transistor formed on a strained SOI substrate composed of layers, wherein 1, 2, 4 to 6, and 9 to 24 are the same as those in FIG. 32 denotes a p-type lateral epitaxial Si layer, 33 denotes a p-type longitudinal epitaxial Si layer, and 34 denotes a p-type lateral epitaxial SiGe layer.
In the figure, a p-type lateral epitaxial Si layer 32 is provided, and a p-type longitudinal epitaxial strained Si layer 33 is provided on the p-type lateral epitaxial Si layer 32 in a cylindrical structure. The vertical type (vertical operation in the vertical direction) of FIG. 1 except that a p-type lateral epitaxial SiGe layer 34 is provided in contact with the inner surface of the cylindrical p-type epitaxial strained Si layer 33. ) N-channel MIS field effect transistor.
In the present embodiment, the same effect as that of the first embodiment can be obtained only with a slightly different manufacturing method.

FIG. 16 shows a fourth embodiment of the semiconductor device of the present invention. A lateral epitaxial SiGe layer, a longitudinal epitaxial SiGe layer, and a lateral epitaxial strained Si formed by a selective compound epitaxial growth method (SCE) using a silicon substrate. 1 shows a part of a semiconductor integrated circuit including a short-channel N-channel MIS field effect transistor formed on a strained SOI substrate composed of layers, wherein 1 to 12 and 14 to 24 are the same as in FIG. 1, and 13a is an outer surface. A gate electrode 13b indicates an inner side gate electrode.
In the figure, a p-type longitudinal epitaxial SiGe layer 7 is provided in a cylindrical structure, and a p-type lateral epitaxial strained Si layer 8 is in contact with the inner and outer surfaces of the cylindrical SiGe layer 7 respectively. A conductive plug having an outer surface gate electrode 13a and an inner surface gate electrode 13b provided on the inner and outer surfaces of the strained Si layer 8 via a gate oxide film 12 and also having a barrier metal (TiN) 19 on the inner surface gate electrode. A vertical (vertical operation) N-channel MIS field effect transistor is formed having the same strained SOI structure as in FIG. 1 except that a Cu wiring 23 having a barrier metal (TaN) 22 is connected via (W) 20. Has been.
In this embodiment, in addition to the same effects as those of the first embodiment, since channels can be formed on the inner and outer surfaces of the strained Si layer 8, the degree of integration is slightly reduced, but higher speed can be expected.

17 is a schematic sectional side view of a fifth embodiment of the semiconductor device of the present invention, and FIGS. 18 to 23 are process sectional views of the manufacturing method of the fifth embodiment of the semiconductor device of the present invention.
FIG. 17 shows a fifth embodiment of the semiconductor device of the present invention. A strained SOI substrate comprising a lateral epitaxial SiGe layer and a longitudinal epitaxial strained Si layer formed by selective compound epitaxial growth (SCE) using a silicon substrate. 1 shows a part of a semiconductor integrated circuit including a short-channel N-channel MIS field effect transistor formed in 1-5, 9-13, 15, 17-24 are the same as FIG. 1, and 35 is a p-type. , A vertical epitaxial strained Si layer, 37 is a sidewall (SiO ₂ ), and 38 is an n-type source region.
In the figure, a p-type lateral (horizontal) epitaxial SiGe layer 3 is provided on a p-type silicon substrate 1 via an oxide film (SiO ₂ ) 2, and this SiGe layer 3 is used for forming an element isolation region. Insulated and isolated in an island shape by the buried insulating film (SiO ₂ ) 4 and the oxide film (SiO ₂ ) 2. A p-type longitudinal (vertical) direction epitaxial strained Si layer 35 is provided on the insulated SiGe layer 3 in a self-aligned manner to form a strained SOI substrate. On the strained Si layer 35, a gate electrode (A1) 13 having sidewalls (SiO ₂ ) 37 on the side walls is provided via a gate oxide film (Ta ₂ O ₅ / SiO ₂ ) 12. The n-type source drain regions self-aligned (10,38) is provided on the gate electrode 13, self-aligned n ⁺ -type source and drain regions (9, 11) is provided on the side wall 37, n ⁺ Each of the source / drain regions (9, 11) and the gate electrode (Al) 13 (not shown) has a barrier metal (TaN) 22 via a conductive plug (W) 20 having a barrier metal (TiN) l9. A lateral type (horizontal operation) N-channel MIS field effect transistor having a strained SOI structure to which a Cu wiring 23 is connected is formed. (Here, a p-type silicon substrate is used as the semiconductor substrate. However, since the MIS field-effect transistor is not directly formed on the silicon substrate, it may be p-type or n-type. )
In this embodiment, a lateral and longitudinal epitaxial semiconductor selectively formed on an insulating film by an easy technique using a normal semiconductor substrate without using a strained SOI substrate formed by the SIMOX method. Since a strained SOI substrate is formed by the layers, and a drain region, a channel region, and a source region can be formed on the strained SOI substrate, a fully depleted strained SOI structure can be easily formed, and the junction capacitance of the source / drain region can be easily formed. Can be reduced (substantially zero), the depletion layer capacitance can be reduced, the breakdown voltage of the source / drain region can be improved, and the threshold voltage can be reduced by improving the subthreshold characteristics.
In addition, since a Si layer that has a laminated structure and is in contact with the SiGe layer can be formed by an easy technique, a strained Si layer can be formed by a tensile stress caused by a SiGe layer having a large lattice constant, so that mobility can be increased. Speeding up is possible.
In addition, Ta ₂ O ₅ with a high dielectric constant can be used as the gate oxide film, so the gate oxide film can be made thicker, minimizing current leakage between the gate electrode and the strained Si layer, and reducing the gate capacitance. It is.
In addition, the source / drain regions that require high-temperature heat treatment to activate the impurity regions can be formed in a self-aligned manner before forming the gate electrode, so that low resistance, low melting point metal can be used without using polycrystalline silicon (semiconductor layer). Since the gate electrode made of (Al) can be formed, the resistance of the gate electrode wiring can be reduced and the depletion layer capacitance at the gate electrode can be removed, so that the power can be reduced by reducing the threshold voltage.

Next, a manufacturing method of the fifth embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. However, the steps shown in FIGS. 2 to 5 described before FIG. 18 are performed.
FIG.
Next, a p-type longitudinal epitaxial strained Si layer 35 of about 25 nm is grown on the p-type compositional epitaxial SiGe layer 3 by chemical vapor deposition. Next, a nitride film (Si ₃ N ₄ ) 5 of about 25 nm is grown by chemical vapor deposition. Next, the nitride film (Si ₃ N ₄ ) 5 on the strained Si layer 35 is subjected to chemical mechanical polishing (CMP) and planarized.
FIG.
Next, a dummy gate oxide film (SiO ₂ ) 36 of about 10 nm is grown by chemical vapor deposition. Next, boron ion implantation for controlling the threshold voltage is performed. Next, a nitride film (Si ₃ N ₄ ) 39 of about 200 nm is grown by chemical vapor deposition. Next, using a normal photolithography technique, a nitride (Si ₃ N ₄ ) 39 is anisotropically dry etched using a resist (not shown) as a mask layer to form a dummy gate electrode (Si ₃ N ₄ ) 39 To do. Next, the resist (not shown) is removed. Next, using the dummy gate electrode (Si ₃ N ₄ ) 39 as a mask layer, phosphorus ions are implanted for forming the n-type source / drain region (10, 38), and then the dummy gate electrode (Si ₃ N ₄ ) 39 is used as the mask layer. Then, the dummy gate oxide film (SiO ₂ ) 36 is removed by etching. Next, an oxide film (SiO ₂ ) 37 of about 20 nm is grown by chemical vapor deposition. Next, anisotropic dry etching is performed to form side walls (SiO ₂ ) 37 on the side walls of the dummy gate electrode (Si ₃ N ₄ ) 39. Next, thermal oxidation is performed to grow an oxide film (not shown) for ion implantation of about 10 nm. Next, arsenic ions are implanted for forming the n ⁺ -type source / drain regions (9, 11) using the dummy gate electrode (Si ₃ N ₄ ) 39 and the sidewalls (SiO ₂ ) 37 as mask layers. Subsequently, n ⁺ type source region 9, n type source region 38, n ⁺ type drain region 11 and n type drain region 10 are formed by annealing by RTP method. Next, the oxide film for ion implantation (not shown) is removed by etching.
FIG.
Next, PSGl5 of about 200 nm is grown by chemical vapor deposition. Then, chemical mechanical polishing (CMP) is performed and planarization is performed. Next, the dummy gate electrode (Si ₃ N ₄ ) 39 and the dummy gate oxide film (SiO ₂ ) 36 are sequentially removed by etching to form an opening.
FIG.
Next, a gate oxide film (Ta ₂ O ₅ / SiO ₂ ) 12 of about 10 nm is grown. Next, Al13 to be a gate electrode of about 200 nm is grown by sputtering. (Barrier metal (TiN) may be provided under the Al gate electrode.) Then, chemical mechanical polishing (CMP) is performed to fill the opening portion flatly.
FIG.
Next, an oxide film (SiO ₂ ) 17 of about 400 nm is grown by chemical vapor deposition. Next, a nitride film (Si ₃ N ₄ ) 18 of about 20 nm is grown by chemical vapor deposition. Next, using normal photolithography technology, using a resist (not shown) as a mask layer, the nitride film (Si ₃ N ₄ ) 18, the oxide film (SiO ₂ ) 17 and PSGl5 are sequentially anisotropically dry etched to form vias Open the hole. Next, the resist (not shown) is removed.
FIG.
Next, TiN19 to be a barrier metal is grown by sputtering. Next, tungsten (W) 20 is grown by chemical vapor deposition. Next, a conductive plug (W) 20 having a barrier metal (TiN) l9 is formed by chemical mechanical polishing (CMP), which is flatly embedded in the via.
FIG.
Next, an interlayer insulating film (SiOC) 21 of about 500 nm is grown by chemical vapor deposition. Next, using an ordinary photolithography technique, the interlayer insulating film (SiOC) 21 is anisotropically dry-etched using a resist (not shown) as a mask layer to form an opening. (At this time, the nitride film (Si ₃ N ₄ ) 18 becomes an etching stopper film.) Next, the resist (not shown) is removed. Next, a barrier metal (TaN) 22 of about 10 nm is grown by chemical vapor deposition. Next, a Cu seed layer is grown by sputtering. Next, Cu of about 500 nm is grown by electrolytic plating. Next, chemical mechanical polishing (CMP) is performed, Cu is flatly embedded in the opening, and a Cu wiring 23 having a barrier metal (TaN) 22 is formed. Next, a nitride film (Si ₃ N ₄ ) 24 serving as a Cu barrier insulating film is grown by chemical vapor deposition, and has a low-resistance metal gate electrode having a strained SOI structure by the selective complex epitaxial growth method (SCE) of the present invention. A horizontal (horizontal operation) N-channel MIS field effect transistor is completed.

FIG. 24 shows a sixth embodiment of the semiconductor device of the present invention. A lateral epitaxial SiGe layer, a longitudinal epitaxial SiGe layer and a lateral epitaxial strained Si formed by a selective compound epitaxial growth method (SCE) using a silicon substrate. 1 shows a part of a CMOS type semiconductor integrated circuit composed of a short-channel N-channel and P-channel MIS field effect transistor formed on a strained SOI substrate composed of layers, wherein 1 to 24 are the same as in FIG. 1, and 40 is n A vertical epitaxial SiGe layer of the type, 41 is an n-type lateral epitaxial strained Si layer, 42 is a p ⁺ type source region, and 43 is a p ⁺ type drain region.
In the figure, a p-type lateral epitaxial SiGe layer 3 is provided on a p-type silicon substrate 1 via an oxide film (SiO ₂ ) 2, and this SiGe layer 3 is buried insulating for forming an element isolation region. It is insulated and isolated in an island shape by the film (SiO ₂ ) 4 and the oxide film (SiO ₂ ) 2. A p-type longitudinal epitaxial SiGe layer 7 is selectively provided on the right-side SiGe layer 3 that is insulated and isolated, and a p-type lateral epitaxial strained Si layer having a slightly small lattice constant is provided on the side surface of the SiGe layer 7. 8 is provided around to form a strained SOI substrate. An n ⁺ -type drain region 11 and an n-type drain region 10 are provided above the SiGe layer 7 and the strained Si layer 8, and an n ⁺ -type source region is formed below the entire SiGe layer 3 and the SiGe layer 7 and the strained Si layer 8. 9 is provided, and a gate electrode (Al) 13 is provided around the side surface of the strained Si layer 8 via a gate oxide film (Ta ₂ O ₅ / SiO ₂ ) 12 to form an n ⁺ type drain region 11 and an n ⁺ type A vertical type of strained SOI structure in which a Cu wiring 23 having a barrier metal (TaN) 22 is connected to the source region 9 and the gate electrode 13 via a conductive brag (W) 20 having a barrier metal (TiN) 19 respectively. An (channel operation) N-channel MIS field effect transistor is formed. Further, an n-type longitudinal epitaxial SiGe layer 40 is selectively provided on the left SiGe layer 3 which is isolated from the insulation, and an n-type lateral epitaxial strain having a slightly small lattice constant is formed on the side surface of the SiGe layer 40. A Si layer 41 is provided around to form a strained SOI substrate. A p ⁺ -type drain region 43 is provided above the SiGe layer 40 and the strained Si layer 41, and a p ⁺ -type source region 42 is provided below the entire SiGe layer 3 and the SiGe layer 40 and the strained Si layer 41. A gate electrode (Al) 13 is provided around the side surface of the Si layer 41 via a gate oxide film (Ta ₂ O ₅ / SiO ₂ ) 12, and includes a p ⁺ -type drain region 43, a p ⁺ -type source region 42, and a gate electrode. 13 is a vertical type (vertical operation) of a strained SOI structure in which a Cu wiring 23 having a barrier metal (TaN) 22 is connected via a conductive plug (W) 20 having a barrier metal (TiN) 19 respectively. A P-channel MIS field effect transistor is formed.
In this embodiment, a lateral and longitudinal epitaxial semiconductor selectively formed on an insulating film by an easy technique using a normal semiconductor substrate without using a strained SOI substrate formed by the SIMOX method. Since a strained SOI substrate is formed by the layers, and a drain region, a channel region, and a source region can be formed on the strained SOI substrate, a fully depleted strained SOI structure can be easily formed, and the junction capacitance of the source / drain region can be easily formed. Can be reduced (substantially zero), the depletion layer capacitance can be reduced, the breakdown voltage of the source / drain region can be improved, and the threshold voltage can be reduced by improving the subthreshold characteristics.
In addition, since the Si layer can be formed by an easy technology and in contact with the SiGe layer, the strained Si layer can be formed by the tensile stress caused by the SiGe layer having a large lattice constant, so the mobility can be increased. Speeding up is possible.
Further, the channel length for determining various characteristics of the MIS field effect transistor can be determined by the growth thickness of the epitaxial semiconductor layer having good controllability and the diffusion of impurities by heat treatment without depending on the control of the gate length by the photolithography technique. In addition, a MIS field effect transistor having stable characteristics can be obtained even in a large-diameter wafer.
Further, since the channel region can be completely surrounded by the gate electrode, the back channel effect that is inevitably generated in either the N-channel MIS field-effect transistor or the P-channel MIS field-effect transistor, which is peculiar to the SOI structure CMOS, is completely achieved. It is possible to obtain a highly integrated MIS field effect transistor with an increased channel width because it has a high performance and high reliability with extremely excellent leakage characteristics, and the entire periphery can be made into a channel region. Can do.
Further, both the mobility of holes and electrons can be increased, and a CMOS having a high switching speed can be formed.
Further, a low concentration region formed as a means for improving the deterioration of transfer conductance over the lifetime due to the hot carrier effect generated due to the strong electric field in the vicinity of the drain region peculiar to the N channel MIS field effect transistor is formed only in the drain region. Since it can be formed without being provided in the region, the resistance of the source region can be reduced, and the channel length can be made fine without degrading the breakdown voltage.
In addition, Ta ₂ O ₅ with a high dielectric constant can be used as the gate oxide film, so the gate oxide film can be made thicker, minimizing current leakage between the gate electrode and the strained Si layer, and reducing the gate capacitance. It is.
In addition, the source / drain regions that require high-temperature heat treatment to activate the impurity regions can be formed in a self-aligned manner before forming the gate electrode, so that low resistance, low melting point metal can be used without using polycrystalline silicon (semiconductor layer). Since the gate electrode made of (Al) can be formed, the resistance of the gate electrode wiring can be reduced and the depletion layer capacitance at the gate electrode can be removed, so that the power can be reduced by reducing the threshold voltage.
Each element (low concentration and high concentration drain region, high concentration source region, gate oxide film and gate electrode) can also be finely formed in self-alignment with the longitudinal epitaxial strained Si layer.
That is, without using a semiconductor substrate having an expensive strained SOI structure (a semiconductor substrate formed by bonding two semiconductor substrates or a semiconductor substrate formed by the SIMOX method), the lateral direction formed on the semiconductor substrate by an easy process and By using a strained SOI substrate formed of a longitudinal epitaxial semiconductor layer, a vertical (vertical) strained SOI structure with a channel-enclosed low-resistance metal gate electrode that combines high speed, low power, high reliability, high performance, and high integration. A CMOS type semiconductor integrated circuit composed of N-channel and P-channel MIS field effect transistors in the direction operation) can be obtained.

FIG. 25 shows a seventh embodiment of the semiconductor device of the present invention. In the semiconductor device of the present invention, a lateral epitaxial SiGe layer, a longitudinal epitaxial SiGe layer and a lateral epitaxial strained Si formed by a selective compound epitaxial growth method (SCE) using a silicon substrate. A short channel P-channel MIS field effect transistor formed on a strained SOI substrate composed of layers, and a short channel N channel MIS field effect transistor formed on an SOI substrate composed of a lateral epitaxial Si layer and a longitudinal epitaxial Si layer. A part of a CMOS type semiconductor integrated circuit is shown, wherein 1 to 6 and 9 to 24 are the same as FIG. 1, 32 is the same as FIG. 15, 40 to 43 are the same as FIG. A p-type longitudinal epitaxial Si layer is shown.
In FIG. 24, except that a vertical (vertical operation) N-channel MIS field effect transistor is formed using a lateral epitaxial Si layer 32 and a vertical epitaxial Si layer 44 as a p-type SOI substrate. A CMOS having the same structure is formed.
In the present embodiment, substantially the same effect as in the sixth embodiment can be obtained, and further, the mobility of holes is further improved and the mobility of electrons is brought closer to that of the P-channel MIS field effect transistor. Since the channel MIS field-effect transistors can be formed in different structures while maintaining high integration, a high switching speed with good on / off characteristics can be obtained.

FIG. 26 shows an eighth embodiment of the semiconductor device according to the present invention. This is a lateral epitaxial Si layer, a longitudinal epitaxial SiGe layer and a lateral epitaxial strained Si formed by selective composite epitaxial growth (SCE) using a silicon substrate. A CMOS type semiconductor integrated circuit including a short channel P-channel MIS field effect transistor formed on a strained SOI substrate composed of layers and a short channel N channel MIS field effect transistor formed on a lateral epitaxial Si layer SOI substrate. 1, 2, 4, 9-13, 15-24 are the same as in FIG. 1, 32 is the same as in FIG. 15, 36 is the same as in FIG. 19, and 37 is in FIG. The same thing, 40-43 has shown the same thing as FIG.
In the figure, a lateral (horizontal operation) N-channel MIS field effect transistor is formed using a lateral epitaxial Si layer 32 as an SOI substrate, and a longitudinal epitaxial SiGe layer and a lateral epitaxial layer formed on the lateral epitaxial Si layer 32 are formed. A CMOS having substantially the same structure as that of FIG. 24 is formed except that a vertical (vertical operation) P-channel MIS field effect transistor is formed on a strained SOI substrate formed of a directional epitaxial strained Si layer.
In this embodiment, although the manufacturing method is somewhat complicated, it is possible to obtain substantially the same effect as in the sixth embodiment, and further improve the mobility of holes and approach the mobility of electrons. Since the P-channel MIS field effect transistor and the N-channel MIS field effect transistor can be formed in different structures while maintaining high integration, a high switching speed with good on / off characteristics can be obtained.

FIG. 27 shows a ninth embodiment of the semiconductor device of the present invention, which is a strained SOI substrate comprising a lateral epitaxial SiGe layer and a longitudinal epitaxial strained Si layer formed by selective compound epitaxial growth (SCE) using a silicon substrate. 2 shows a part of a CMOS type semiconductor integrated circuit including a short channel P-channel MIS field effect transistor formed on the semiconductor substrate and a short channel N channel MIS field effect transistor formed on a lateral epitaxial Si layer SOI substrate. 1, 2, 4, 9 to 13, 15, 17 to 24 are the same as in FIG. 1, 32 is the same as in FIG. 15, 37 is the same as in FIG. 17, and 42 and 43 are the same as in FIG. 45 denotes an n-type lateral epitaxial SiGe layer, 46 denotes an n-type longitudinal epitaxial strained Si layer, and 47 denotes a back gate electrode (WSi).
In the figure, a lateral (horizontal operation) N-channel MIS field effect transistor is formed using a lateral epitaxial Si layer 32 as an SOI substrate, and a strain comprising a lateral epitaxial SiGe layer 45 and a longitudinal epitaxial strained Si layer 46 is formed. A CMOS having substantially the same structure as that of FIG. 24 is formed except that a lateral (horizontal operation) P-channel MIS field effect transistor having a back gate electrode 47 is formed on an SOI substrate.
In this embodiment, since lateral (horizontal operation) N-channel and P-channel MIS field effect transistors are formed, a back gate electrode (WSi) is formed on the P-channel MIS field effect transistor in order to prevent back channel leakage. (P-type Si substrate is used as the back gate electrode for the N-channel MIS field effect transistor), compared with a vertical (vertical operation) MIS field effect transistor having an enclosed gate electrode. However, there are disadvantages such as inferior leakage characteristics, inability to increase the channel width, and determination of the channel length depending on the photolithography technique, but the other effects are almost the same as in the sixth embodiment. Can be obtained, the manufacturing method is relatively simple, further improve the mobility of holes and approach the mobility of electrons As described above, the P-channel MIS field-effect transistor and the N-channel MIS field-effect transistor can be formed in different structures while maintaining high integration, so that a high switching speed with good on / off characteristics can be obtained. .

FIG. 28 is a schematic side sectional view of the tenth embodiment of the semiconductor device of the present invention, FIG. 29 is a schematic side sectional view of the gate electrode wiring connection portion of the tenth embodiment of the semiconductor device of the present invention, and FIGS. 37 is a process sectional view of the manufacturing method according to the tenth embodiment of the semiconductor device of the present invention.
FIG. 28 shows a tenth embodiment of the semiconductor device of the present invention. A lateral epitaxial SiGe layer, a longitudinal epitaxial SiGe layer, and a lateral epitaxial strain formed by a selective complex epitaxial growth method (SCE) using a silicon substrate. A short-channel P-channel MIS field effect transistor formed on a strained SOI substrate made of a Si layer, and a short-channel N-channel MIS field formed on a strained SOI substrate made of a lateral epitaxial SiGe layer and a longitudinal epitaxial strained Si layer. 1 shows a part of a CMOS type semiconductor integrated circuit including an effect transistor, wherein 1 to 5, 9 to 13 and 15 to 24 are the same as those in FIG. 1, and 35 and 38 are the same as those in FIGS. , 40 to 43 are the same as in FIG.
24 is substantially the same as FIG. 24 except that a lateral (horizontal operation) N-channel MIS field effect transistor is formed on a strained SOI substrate composed of a lateral epitaxial SiGe layer 3 and a longitudinal epitaxial strained Si layer 35. A CMOS structure is formed.
In this example, the manufacturing method is somewhat complicated, but almost the same effect as in the sixth example can be obtained, and further, the mobility of holes is further improved, and the mobility of electrons is approached. Since the P-channel MIS field effect transistor and the N-channel MIS field effect transistor can be formed in different structures while maintaining high integration, a high switching speed with good on / off characteristics can be obtained.

Next, a manufacturing method of a tenth embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. 30 to 37 and FIG. However, the steps shown in FIGS. 2 to 5 described before FIG. 30 are performed.
FIG.
Next, the surface of the p-type lateral epitaxial SiGe layer 3 is thermally oxidized to grow an oxide film (SiO ₂ ) of about 10 nm. Next, using an ordinary photolithography technique, the oxide film (SiO ₂ ) on the SiGe layer 3 on the right side is removed by etching using a resist (not shown) as a mask layer. Next, the resist (not shown) is removed. Next, a p-type longitudinal epitaxial strained Si layer 35 of about 25 nm is grown on the exposed right SiGe layer 3 by chemical vapor deposition. Next, the oxide film (SiO ₂ ) on the left SiGe layer 3 is removed by etching. Next, a nitride film (Si ₃ N ₄ ) 5 of about 25 nm is grown by chemical vapor deposition. Next, the nitride film (Si ₃ N ₄ ) 5 on the strained Si layer 35 is subjected to chemical mechanical polishing (CMP) and planarized.
FIG.
Next, a dummy gate oxide film (SiO ₂ ) 36 of about 10 nm is grown by chemical vapor deposition. Next, boron is used for threshold voltage control of an N-channel MIS field effect transistor using a normal photolithography technique using a resist (not shown) as a mask layer. Next, the resist (not shown) is removed. Next, a nitride film (Si ₃ N ₄ ) 39 of about 200 nm is grown by chemical vapor deposition. Next, using a normal photolithography technique, using a resist (not shown) as a mask layer, a nitride film (Si ₃ N ₄ ) 39, a dummy gate oxide film (SiO ₂ ) 36 and a nitride film (Si ₃ N ₄ ) 5 Are sequentially subjected to anisotropic dry etching to form an opening. Next, the resist (not shown) is removed. Next, by chemical vapor deposition, an n-type vertical epitaxial SiGe layer (Ge concentration of about 30%) 40 having a width of about 30 nm is grown on the exposed p-type lateral epitaxial SiGe layer 3 by about 250 nm. Next, the exposed surface of the SiGe layer 7 is oxidized to grow an oxide film (SiO ₂ ) 29.
FIG.
Next, using a normal photolithography technique, a nitride (Si ₃ N ₄ ) 39 is anisotropically dry etched using a resist (not shown) as a mask layer to form a dummy gate electrode (Si ₃ N ₄ ) 39 To do. Next, the resist (not shown) is removed. Next, an n-type lateral epitaxial strained Si layer 41 having a width of about 25 nm is grown on the exposed side surface of the longitudinal epitaxial SiGe layer 40.
FIG.
Next, the oxide film (SiO ₂ ) 29 is subjected to anisotropic dry etching. (At this time, the exposed oxide film (SiO ₂ ) 36 is also removed by etching.) Next, thermal oxidation is performed to grow an oxide film (not shown) for ion implantation of about 10 nm. Next, using normal photolithography technology, phosphorus ions are implanted to control the threshold voltage of the P-channel MIS field effect transistor using a resist (not shown) as a mask layer. Next, the resist (not shown) is removed. Next, heat treatment is performed at about 1000 ° C., and the strained Si layer 35 and SiGe layer 3 that become the semiconductor substrate of the N-channel MIS field effect transistor, and the strained Si layer 41, SiGe layer 40, and SiGe layer that become the semiconductor substrate of the P-channel MIS field effect transistor Control the concentration of 3. Next, using normal photolithography technology, phosphorus ion implantation for forming the n-type source / drain regions (10, 38) is performed using a resist (not shown) and a dummy gate electrode (Si ₃ N ₄ ) 39 as a mask layer. Do it. Next, the resist (not shown) is removed. Next, boron is ion-implanted for forming the p ⁺ -type source / drain regions (42, 43) using a normal photolithography technique using a resist (not shown) as a mask layer. Next, the resist (not shown) is removed. Next, the oxide film for ion implantation (not shown) is removed by etching. Next, an oxide film (SiO ₂ ) 37 of about 20 nm is grown by chemical vapor deposition. Next, anisotropic dry etching is performed to form side walls (SiO ₂ ) 37 on the side walls of the dummy gate electrode (Si ₃ N ₄ ) 39. (At this time, unnecessary sidewalls (SiO ₂ ) 37 are also formed on the sidewalls of the strained Si layer 41, but there is no problem.) Next, thermal oxidation is performed, and an oxide film for ion implantation of about 10 nm (not shown). ) Grow up. Next, using normal photolithography technology, n ⁺ type source / drain regions (9, 11) using a resist (not shown), dummy gate electrode (Si ₃ N ₄ ) 39 and sidewall (SiO ₂ ) 37 as mask layers. ) Arsenic ion implantation for forming. Next, the resist (not shown) is removed. Next, annealing is performed by the RTP method, so that the n ⁺ type source region 9, the n type source region 38, the n ⁺ type drain region 11, the n type drain region 10, the p ⁺ type source region 42 and the p ⁺ type drain region 43 are formed. Form. Next, the oxide film for ion implantation (not shown) is removed by etching.
FIG.
Next, PSG15 of about 200 nm is grown by chemical vapor deposition. Then, chemical mechanical polishing (CMP) is performed to remove the PSG 15 on the strained Si layer 41 and the SiGe layer 40 and planarize. Next, the dummy gate electrode (Si ₃ N ₄ ) 39 and the dummy gate oxide film (SiO ₂ ) 36 are sequentially removed by etching to form an opening. Next, by using a normal photolithography technique, PSG 15 in the vicinity of the strained Si layer 41 (side gate electrode forming portion) is anisotropically dry etched using a resist (not shown) as a mask layer. Next, the resist (not shown) is removed.
FIG.
Next, a gate oxide film (Ta ₂ O ₅ / SiO ₂ ) 12 of about 10 nm is grown. Next, Al13 to be a gate electrode of about 120 nm is grown by sputtering. Next, chemical mechanical polishing (CMP) is performed to remove Al 13 and the gate oxide film (Ta ₂ O ₅ / SiO ₂ ) 12 on the strained Si layer 41 and the SiGe layer 40 and planarize them. Next, Al13 and the gate oxide film (Ta ₂ O ₅ / SiO ₂ ) 12 are sequentially over-etched by about 50 nm to form a stepped portion. (At this time, PSG 15 is also etched by about 50 nm.) Next, a nitride film (Si ₃ N ₄ ) 16 of about 50 nm is grown by chemical vapor deposition. Next, chemical mechanical polishing (CMP) is performed, and a nitride film (Si ₃ N ₄ ) 16 is flatly embedded in the stepped portion.
FIG.
Next, an oxide film (SiO ₂ ) 17 of about 400 nm is grown by chemical vapor deposition. Next, a nitride film (Si ₃ N ₄ ) 18 of about 20 nm is grown by chemical vapor deposition. Next, using a normal photolithography technique, the nitride film (Si ₃ N ₄ ) 18 and the oxide film (SiO ₂ ) 17 are sequentially subjected to anisotropic dry etching using the first resist (not shown) as a mask layer. (At this stage, a via is opened in a part of the p ⁺ -type drain region 43.) Then, using a normal photolithography technique, the mask layer of the first resist (not shown) is left as it is, and the p ⁺ A second resist mask layer (not shown) that covers only the via portion of the mold drain region 11 is formed. Next, using the first and second resists (not shown) as a mask layer, the nitride film (Si ₃ N ₄ ) 16, PSG 15, and nitride film (Si ₃ N ₄ ) 5 are sequentially subjected to anisotropic dry etching. (Thus, vias are also opened in a part of the p ⁺ type source region 42, the n ⁺ type source region 9, the n ⁺ type drain region 11 and the gate electrode wiring 13.) Next, all resists (not shown) are formed. Remove.
FIG.
Next, TiN19 to be a barrier metal is grown by sputtering. Next, tungsten (W) 20 is grown by chemical vapor deposition. Next, a conductive plug (W) 20 having a barrier metal (TiN) 19 is formed by chemical mechanical polishing (CMP).
FIG.
Next, an interlayer insulating film (SiOC) 21 of about 500 nm is grown by chemical vapor deposition. Next, using an ordinary photolithography technique, the interlayer insulating film (SiOC) 21 is anisotropically dry-etched using a resist (not shown) as a mask layer to form an opening. (At this time, the nitride film (Si ₃ N ₄ ) 18 becomes an etching stopper film.) Next, the resist (not shown) is removed. Next, a barrier metal (TaN) 22 of about 10 nm is grown by chemical vapor deposition. Next, a Cu seed layer is grown by sputtering. Next, Cu of about 500 nm is grown by electrolytic plating. Next, chemical mechanical polishing (CMP) is performed, Cu is flatly embedded in the opening, and a Cu wiring 23 having a barrier metal (TaN) 22 is formed. Next, a nitride film (Si ₃ N ₄ ) 24 serving as a Cu barrier insulating film is grown by chemical vapor deposition, and a channel-enclosed low resistance metal having a strained SOI structure is formed by the selective composite epitaxial growth method (SCE) of the present invention. A CMOS type semiconductor comprising a vertical (vertical operation) P-channel MIS field effect transistor having a gate electrode and a lateral (horizontal operation) N-channel MIS field effect transistor having a low-resistance metal gate electrode having a strained SOI structure. Complete the device.

In the description of the above embodiment, the case where the strained Si layer is formed by the SiGe layer on the silicon substrate is described. However, a strained compound semiconductor layer having a lattice constant close to that of the silicon substrate may be formed. However, a strained compound semiconductor layer having a lattice constant close to that of the compound semiconductor substrate may be formed.
When epitaxially growing a semiconductor layer, not only by chemical vapor deposition but also by molecular beam growth (MBE), metal organic chemical vapor deposition (MOCVD), or atomic layer crystal growth (ALE). Any other crystal growth method may be used.
In addition, the vertical epitaxial semiconductor layer formed directly on the semiconductor substrate (the region that eventually becomes the buried insulating film in the element isolation region) is a convex structure portion of the semiconductor substrate formed by providing a trench in the semiconductor substrate. May be.
The planar shape of the epitaxial semiconductor layer is a straight line, a curved line, a circle, a rectangle, other geometric shapes, or a double shape. The invention of the present application can be established even in a triple shape (eg, a U-shape).
The gate electrode, the gate oxide film, the barrier metal, the conductive plug, the wiring, the insulating film, the conductive film, and the like are not limited to the above embodiments, and any material may be used as long as it has similar characteristics. .
The gate electrode has a single layer structure of Al, but may have a double layer structure in which a barrier metal (TiN or the like) is provided under the Al.
In the vertical MIS field effect transistor of the above embodiment, the drain region is formed in the upper portion of the strained SOI substrate and the source region is formed in the lower portion, but these may be formed in the opposite manner.
In addition, although all of the above embodiments describe the case where an enhancement type MIS field effect transistor is formed, a depletion type MIS field effect transistor may be formed. In this case, an epitaxial semiconductor layer having the opposite conductivity type is grown, or an epitaxial semiconductor layer having a similar structure is formed by growing an epitaxial semiconductor layer and then ion-implanting an impurity of the opposite conductivity type to convert the conductivity type. A MIS field effect transistor may be formed.

The present invention is particularly aimed at a very high speed and highly integrated MIS field effect transistor, but is not limited to a high speed and can be used for all semiconductor integrated circuits equipped with a MIS field effect transistor.
Moreover, it can be used not only as a semiconductor integrated circuit but also as a single individual semiconductor element.
In addition to the MIS field effect transistor, it may be used for other field effect transistors, current driving elements, photoelectric conversion elements, and the like.

Schematic side sectional view of the first embodiment of the semiconductor device of the present invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Schematic side sectional view of the second embodiment of the semiconductor device of the present invention Schematic side sectional view of the third embodiment of the semiconductor device of the present invention Schematic side sectional view of the fourth embodiment of the semiconductor device of the present invention Schematic side sectional view of the fifth embodiment of the semiconductor device of the present invention. Process sectional drawing of the manufacturing method of the 5th Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of the 5th Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of the 5th Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of the 5th Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of the 5th Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of the 5th Example in the semiconductor device of this invention Schematic side sectional view of the sixth embodiment of the semiconductor device of the present invention. Schematic side sectional view of the seventh embodiment of the semiconductor device of the present invention Schematic side sectional view of the eighth embodiment of the semiconductor device of the present invention. Schematic side sectional view of the ninth embodiment of the semiconductor device of the present invention. Schematic side sectional view of the tenth embodiment of the semiconductor device of the present invention. Schematic side sectional view of the gate electrode wiring portion of the tenth embodiment in the semiconductor device of the present invention. Process sectional drawing of the manufacturing method of the 10th Example in the semiconductor device of this invention. Process sectional drawing of the manufacturing method of the 10th Example in the semiconductor device of this invention. Process sectional drawing of the manufacturing method of the 10th Example in the semiconductor device of this invention. Process sectional drawing of the manufacturing method of the 10th Example in the semiconductor device of this invention. Process sectional drawing of the manufacturing method of the 10th Example in the semiconductor device of this invention. Process sectional drawing of the manufacturing method of the 10th Example in the semiconductor device of this invention. Process sectional drawing of the manufacturing method of the 10th Example in the semiconductor device of this invention. Process sectional drawing of the manufacturing method of the 10th Example in the semiconductor device of this invention. Schematic side sectional view of a conventional semiconductor device

Explanation of symbols

1 p-type silicon (Si) substrate
2 Oxide film for SOI / element isolation region (SiO ₂ )
3 p-type lateral (horizontal) epitaxial SiGe layer
4 Embedded insulating film (SiO ₂ ) for element isolation region
5 Nitride film (Si ₃ N ₄ )
6 Oxide film (SiO ₂ )
7 p-type longitudinal (vertical) epitaxial SiGe layer
8 p-type lateral (horizontal) epitaxial strained Si layer
9 n ⁺ type source region
10 n-type drain region
11 n ⁺ type drain region
12 Gate oxide film (Ta ₂ O ₅ / SiO ₂ )
13 Gate electrode (Al)
13a External gate electrode (Al)
13b Inner side gate electrode (Al)
14 Mask layer (SiO ₂ ) for gate electrode wiring formation
15 Phosphorsilicate glass (PSG) film
16 Nitride film (Si ₃ N ₄ )
17 Oxide film (SiO ₂ )
18 Etching stopper film (Si ₃ N ₄ )
19 Barrier metal (TiN)
20 Conductive plug (W)
21 Interlayer insulation film (SiOC)
22 Barrier metal (TaN)
23 Cu wiring (including Cu seed layer)
24 Barrier insulation film (Si ₃ N ₄ )
25 p-type longitudinal (vertical) epitaxial SiGe layer
26 Nitride film (Si ₃ N ₄ )
27 Oxide film (SiO ₂ )
28 Nitride film (Si ₃ N ₄ )
29 Oxide film (SiO ₂ )
30 Lower layer wiring (WSi)
31 Insulating film (SiO ₂ )
32 p-type lateral (horizontal) epitaxial Si layer
33 p-type longitudinal (vertical) epitaxial strained Si layer
34 p-type lateral (horizontal) epitaxial SiGe layer
35 p-type longitudinal (vertical) epitaxial strained Si layer
36 Dummy gate oxide film (SiO ₂ )
37 Side wall (SiO ₂ )
38 n-type source region
39 Dummy gate electrode (Si ₃ N ₄ )
40 n-type longitudinal (vertical) epitaxial SiGe layer
41 n-type lateral (horizontal) epitaxial strained Si layer
42 p ⁺ type source region
43 p ⁺ type drain region
44 p-type longitudinal (vertical) epitaxial Si layer
45 n-type lateral (horizontal) epitaxial SiGe layer
46 n-type vertical (vertical) epitaxial strained Si layer
47 Back gate electrode (WSi)

Claims (3)

A semiconductor substrate, an insulating film provided on the semiconductor substrate, and a first lateral epitaxial semiconductor layer selectively provided on the insulating film in a direction parallel to a main surface of the semiconductor substrate; A vertical epitaxial semiconductor layer selectively provided on the first lateral epitaxial semiconductor layer in a direction perpendicular to the main surface of the semiconductor substrate, and around a side surface of the vertical epitaxial semiconductor layer. A second lateral strained epitaxial semiconductor layer having a lattice constant different from that of at least the longitudinal epitaxial semiconductor layer; and an upper portion of the longitudinal epitaxial semiconductor layer and the second lateral strained epitaxial semiconductor layer. The drain region (or source region) provided in the source region and the drain region (or source region) spaced apart from the drain region (or source region) Source region (or drain region) provided below the vertical epitaxial semiconductor layer and the second lateral strained epitaxial semiconductor layer, the vertical epitaxial semiconductor layer, and the second epitaxial semiconductor layer. A source region (or drain region) provided in the first lateral epitaxial semiconductor layer in contact with a source region (or drain region) provided under the two lateral strained epitaxial semiconductor layers; And a vertical (operation in the vertical direction) MIS field effect transistor having a gate electrode provided on a side surface of the laterally strained epitaxial semiconductor layer of 2 via a gate insulating film. Semiconductor device. 2. The semiconductor device according to claim 1, wherein a wiring body is provided on a lower surface of the first lateral epitaxial semiconductor layer. Forming a first insulating film on the semiconductor substrate; selectively forming a first opening in the first insulating film to expose a part of the upper surface of the semiconductor substrate; Forming a first vertical epitaxial semiconductor layer in one opening, forming a first mask layer on an upper surface of the first vertical epitaxial semiconductor layer, and forming a first insulating film on the first insulating film; A step of selectively removing a portion to expose a part of the side surface of the first vertical epitaxial semiconductor layer; and a first lateral epitaxial semiconductor layer on the exposed side surface of the first vertical epitaxial semiconductor layer. Forming a second mask layer on the upper surface of the first lateral epitaxial semiconductor layer, and a first mask using the first insulating film and the second mask layer as an etching mask Layer and said first longitudinal Forming a second opening to remove the epitaxial semiconductor layer, a step of the second insulating film is buried and removing the second mask layer planarizing the second opening, a plurality of layers third forming an insulating film, a step of exposing a part of an upper surface of the third insulating film is selectively formed a third opening in the first lateral epitaxial semiconductor layer made of A step of forming a second vertical epitaxial semiconductor layer in the third opening, a step of forming a third mask layer on the top surface of the second vertical epitaxial semiconductor layer, and the third a step of exposing a part of the side surface of the longitudinal epitaxial semiconductor layer, the exposed part to the lattice constant of the side surface of the second longitudinal epitaxial semiconductor layer is different from the part removed of the second insulating film Form a second lateral epitaxial semiconductor layer The method of manufacturing a semiconductor device which comprises a that step.

Images