KR20030002722A - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR20030002722A KR20030002722A KR1020010038422A KR20010038422A KR20030002722A KR 20030002722 A KR20030002722 A KR 20030002722A KR 1020010038422 A KR1020010038422 A KR 1020010038422A KR 20010038422 A KR20010038422 A KR 20010038422A KR 20030002722 A KR20030002722 A KR 20030002722A
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- ion implantation
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 49
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 30
- 238000005468 ion implantation Methods 0.000 claims abstract description 28
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 2
- 229920005591 polysilicon Polymers 0.000 abstract 2
- 238000005530 etching Methods 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 8
- 238000002955 isolation Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히, 플래시 메모리의 유전체막으로 사용되는 ONO 구조에서 발생하는 스마일링(smiling)을 억제하여 특성 안정화에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to stabilizing characteristics by suppressing smearing generated in an ONO structure used as a dielectric film of a flash memory.
반도체 메모리 장치는 DRAM(dynamic random access memory) 및 SRAM(static random access memory)과 같이 시간이 지남에 따라 데이터를 잃어버리는 휘발성(volatile)이면서 데이터의 입/출력이 빠른 RAM 제품과, 한번 데이터를 입력하면 그 상태를 유지할 수 있지만 데이터의 입·출력이 느린 ROM(read only memory) 제품으로 크게 구분할 수 있다. 이러한 ROM 제품은 ROM, PROM(programmable ROM), EPROM(erasable PROM) 및 EEPROM(electrically EPROM)으로 분류할 수 있는데, 이 중에서 전기적 방법으로 데이터를 프로그램 및 소거(erase)할 수 있는 EEPROM에 대한 수요가 증가하고 있는 추세이다. 상기한 EEPROM이나 일괄 소거 기능을 갖는 플래쉬 EEPROM은 플로팅 게이트전극과 콘트롤 게이트전극이 적층된 스택형 게이트 구조를 갖는다.Semiconductor memory devices, such as dynamic random access memory (DRAM) and static random access memory (SRAM), are volatile and fast data input / output that loses data over time, and data is input once. If you do this, you can maintain the status, but it can be divided into ROM (read only memory) products with slow data input and output. These ROM products can be categorized into ROM, programmable ROM (PROM), erasable PROM (EPROM), and electrically EPROM (EEPROM), among which there is a need for an EEPROM that can program and erase data in an electrical manner. The trend is increasing. The EEPROM or the flash EEPROM having a batch erase function has a stacked gate structure in which a floating gate electrode and a control gate electrode are stacked.
상기 스택형 게이트 구조의 메모리 셀은 F-N 터널링(Fowler-Nordheim tunneling)에 의해 데이터를 프로그램 및 소거하며, 반도체 기판의 상부에 터널 산화막, 플로팅 게이트전극, 유전체막 및 콘트롤 게이트전극이 적층된 구조로 형성된다. 상기 플로팅 게이트전극은 일반적으로 내열성이 강한 불순물이 도핑된 다결정질 실리콘막(polysilicon)으로 형성되고, 상기 컨트롤 게이트전극은 다결정질 실리콘막 및 텅스텐 실리사이드(tungsten silicide; Wsix)의 적층 구조로 이루어진다.The memory cell of the stacked gate structure is programmed and erased by FN tunneling (Fowler-Nordheim tunneling), and has a structure in which a tunnel oxide layer, a floating gate electrode, a dielectric layer, and a control gate electrode are stacked on the semiconductor substrate. do. The floating gate electrode is generally formed of a polycrystalline silicon film doped with impurities having strong heat resistance, and the control gate electrode is formed of a stacked structure of a polycrystalline silicon film and tungsten silicide (Wsix).
이러한, 스택형 게이트구조는 일반적으로 게이트마스크를 이용한 식각공정을 통해 형성되고, 상기 식각공정에 의해 손상되는 부위를 보상하기 위한 후속공정으로 열처리공정이 수반된다. 그러나, 상기 열처리공정에 의해 상기 플로팅 게이트전극과 콘트롤 게이트전극이 산화되어 ONO 구조의 유전체막의 에지 부위의 크기가 증가하는 스마일링(smiling) 현상이 발생하게 된다. 이러한 ONO 구조의 유전체막의 스마일링 현상은 플래시 셀 트랜지스터의 프로그램 및 소거 특성의 저하를 가져온다.Such a stacked gate structure is generally formed through an etching process using a gate mask, and a heat treatment process is accompanied by a subsequent process for compensating for a portion damaged by the etching process. However, by the heat treatment process, the floating gate electrode and the control gate electrode are oxidized, and a smileing phenomenon occurs in which the size of the edge portion of the dielectric film of the ONO structure increases. Such a phenomenon of smiling the dielectric film of the ONO structure results in deterioration of program and erase characteristics of the flash cell transistor.
스택 구조의 게이트전극을 형성한 후, 산화막 강화(oxide enhance)를 위해 진행되는 열처리 공정은 식각 손상을 보상하는 작용과, ONO 구조의 유전체막의 에지 부위가 증가하는 스마일링 현상을 발생하는 작용을 동시에 함으로써, Re 산화막 및 SAS(self align source) 열공정 후, 셀 트랜지스터의 접합영역 에지 부분의 손상에 대한 충분한 보상에 대해 셀 트랜지스터의 물리적 특성 변화에 대한 어려운 점이 있으며, ONO 층 증가에 의한 셀 커플링 비율 감소에 의해 셀 트랜지스터의 특성이 약화되어 프로그램 동작시 프로그램 상태로 셋팅하기 위한 프로그램 펄스 수의 증가및 소거 상태로 셋팅하기 위한 소거 펄스 수의 증가등의 속도 저하로 인해 셀 트랜지스터의 전기적 특성 저하가 발생한다.After forming the gate electrode of the stacked structure, an annealing process performed for oxide enhancement simultaneously compensates for etch damage and generates a smile phenomenon in which the edge portion of the ONO structure dielectric film increases. Thereby, there is a difficulty in changing the physical characteristics of the cell transistor for sufficient compensation for damage of the junction region edge portion of the cell transistor after the Re oxide film and the self align source (SAS) thermal process, and cell coupling due to the increase of the ONO layer. As the ratio decreases, the characteristics of the cell transistors are weakened, and the electrical characteristics of the cell transistors are deteriorated due to the decrease in speed such as the increase in the number of program pulses for setting to the program state and the increase in the number of erase pulses for setting to the erase state during program operation. Occurs.
따라서, 본 발명은 상기의 문제를 해결하기 위해 안출된 것으로, 플래시 메모리 셀의 ONO 구조의 유전체막에서 발생하는 스마일링 현상을 저온 산화막과 LATID(Large tilted) N2이온 주입공정으로 형성된 질소 이온주입 산화층(nitrogen implanted oxide layer)을 이용하여 후속 열처리 공정에 의해 발생하는 ONO 구조의 유전체막의 스마일링을 억제하여 셀 트랜지스터의 프로그램 펄스 수의 증가 및 소거 펄스 수의 증가로 나타나는 특성 저하를 방지하여 안정된 플래시 셀 트랜지스터 형성을 목적으로 한다.Accordingly, the present invention has been made to solve the above problem, and the nitrogen phenomena formed by the low temperature oxide film and the large tilted N 2 ion implantation process are applied to the smile phenomenon occurring in the dielectric film of the ONO structure of the flash memory cell. Stable flash by using a nitrogen implanted oxide layer to suppress the smiling of the ONO structure dielectric film generated by the subsequent heat treatment process, thereby preventing the deterioration of characteristics caused by an increase in the number of program pulses and an increase in the number of erase pulses. The purpose is to form a cell transistor.
도 1은 본 발명의 일 실시예에 따른 반도체 소자의 레이아웃도.1 is a layout of a semiconductor device according to an embodiment of the present invention.
도 2a 내지 도 2d는 도 1에 도시된 선 'A-A'를 따라 도시한 반도체 소자의 단면도.2A through 2D are cross-sectional views of a semiconductor device taken along the line 'A-A' shown in FIG. 1.
도 3은 도 2d에 도시된 'B' 부위를 확대하여 도시한 확대도.3 is an enlarged view illustrating an enlarged 'B' portion shown in FIG.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11 : 반도체 기판 12 : 활성영역11 semiconductor substrate 12 active region
13 : 소자 분리막 14 : 터널산화막13 device isolation layer 14 tunnel oxide film
15 : 제 1 다결정 실리콘층 16 : 유전체막15 first polycrystalline silicon layer 16 dielectric film
17 : 제 2 다결정 실리콘층 18 : WSix층17 second polycrystalline silicon layer 18 WSix layer
19 : 반사방지막 20 : 콘트롤 게이트전극19: antireflection film 20: control gate electrode
21 : 플로팅 게이트전극 22 : 저온 산화막21: floating gate electrode 22: low temperature oxide film
22a : 나이트라젠 인플란트 산화층22a: Nitragen implant oxide layer
23 : 소오스 라인 24 : 소오스 접합부23 source line 24 source junction
25 : 드레인 접합부25: drain junction
상술한 목적을 달성하기 위해 본 발명은 반도체 기판 상에 게이트전극 구조를 형성하는 단계; 전체 구조 상부에 절연막을 형성한 후, N2LATID 이온 주입공정을 진행하여 상기 절연막 내에 나이트라젠 인플란트 산화층을 형성하는 단계; 상기 소오스/드레인 이온 주입공정을 진행하여 상기 반도체 기판에 소오스 및 드레인 접합부를 형성하는 단계를 포함하여 이루어진다.In order to achieve the above object, the present invention comprises the steps of forming a gate electrode structure on a semiconductor substrate; Forming an insulating layer on the entire structure, and then performing a N 2 LATID ion implantation process to form a nitragen implant oxide layer in the insulating layer; And performing a source / drain ion implantation process to form source and drain junctions on the semiconductor substrate.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
이를 도 1은 본 발명의 일 실시예에 따른 반도체 소자의 레이아웃도이고, 도 2a 내지 도 2c는 도 1에 선 'A-A'를 따라 도시한 반도체 소자의 단면도이다.1 is a layout view of a semiconductor device in accordance with an embodiment of the present invention, and FIGS. 2A to 2C are cross-sectional views of the semiconductor device taken along the line 'A-A' in FIG. 1.
도 1 및 도 2a를 참조하면, 반도체 기판(11)이 제공되고, 아이솔레이션 공정을 진행하여 상기 반도체 기판(11)의 소정 영역에 활성영역(12)을 정의하기 위한 소자분리막(13)이 형성된다. 이어서, 전체 구조 상부에는 터널 산화막(14) 및 제 1 다결정 실리콘층(15), 유전체막(16), 제 2 다결정 실리콘층(17), WSix층(18) 및 반사방지막(19)이 순차적으로 형성된다. 상기 유전체막(16)은 산화막-질화막-산화막이 순차적으로 적층된 ONO 구조로 형성된다.1 and 2A, a semiconductor substrate 11 is provided, and an isolation layer 13 is formed to define an active region 12 in a predetermined region of the semiconductor substrate 11 by performing an isolation process. . Subsequently, the tunnel oxide film 14 and the first polycrystalline silicon layer 15, the dielectric film 16, the second polycrystalline silicon layer 17, the WSix layer 18, and the antireflection film 19 are sequentially formed on the entire structure. Is formed. The dielectric film 16 is formed in an ONO structure in which an oxide film-nitride film-oxide film is sequentially stacked.
도 2b를 참조하면, 게이트마스크를 이용한 소정의 식각공정을 진행하여 상기 반사방지막(19), WSix층(18), 제 2 다결정 실리콘층(17) 및 유전체막(16)을 일차적으로 식각함으로써 WSix층(18) 및 제 2 다결정 실리콘층(17)의 적층구조의 콘트롤 게이트전극(20)이 형성된다. 이어서, 소정의 스트립공정을 진행하여 상기 게이트마스크를 제거한 후, 자기정렬 식각(self align etch; SAE) 마스크를 이용한 자기정렬 식각공정을 진행하여 제 1 다결정 실리콘층(15) 및 터널 산화막(14)을 식각함으로써 플로팅 게이트전극(21)이 형성된다.Referring to FIG. 2B, a predetermined etching process using a gate mask is performed to firstly etch the antireflection film 19, the WSix layer 18, the second polycrystalline silicon layer 17, and the dielectric film 16. A control gate electrode 20 having a stacked structure of the layer 18 and the second polycrystalline silicon layer 17 is formed. Subsequently, the gate mask is removed by performing a predetermined strip process, and then the first polycrystalline silicon layer 15 and the tunnel oxide layer 14 are subjected to a self-aligned etching process using a self-aligned etch (SAE) mask. By etching the floating gate electrode 21 is formed.
도 2c를 참조하면, 전체 구조 상부에 저온으로 형성될 수 있는 저온 산화막막(22)을 형성한다. 상기 저온 산화막(22)은 저온에서 LPCVD 방법을 통해 50 내지 200Å의 두께로 형성되는데 일반적으로, TEOS막이 사용된다.Referring to FIG. 2C, a low temperature oxide film 22 may be formed on the entire structure at a low temperature. The low temperature oxide film 22 is formed to a thickness of 50 to 200 kPa by the LPCVD method at a low temperature, in general, TEOS film is used.
도 2d를 참조하면, 전체 구조 상부에 블랭켓(blanket) N2LATID 이온 주입공정을 진행하여 상기 저온 산화막(22)의 소정 부위에 질소 이온주입 산화층(22a)이 형성된다. 상기 N2LATID 이온 주입공정은 N2가스를 소오스 가스로 하며, 틸트(tilt)를 30 내지 60°로 하고, 도즈(dose)량을 1E14 내지 1E15 ion/㎤로 하며, 이온 주입에너지를 10 내지 15KeV로 하여 진행된다.Referring to FIG. 2D, a blanket N 2 LATID ion implantation process is performed on the entire structure to form a nitrogen ion implantation oxide layer 22a at a predetermined portion of the low temperature oxide layer 22. In the N 2 LATID ion implantation process, the N 2 gas is a source gas, the tilt is 30 to 60 °, the dose is 1E14 to 1E15 ion / cm 3, and the ion implantation energy is 10 to Proceed to 15 KeV.
도 1을 참조하면, 자기정렬 소오스(self align source; SAS) 식각 마스크를 이용한 자기정렬 소오스 식각공정을 진행하여 소오스 라인(23)이 형성된다. 이어서, 상기 자기정렬 소오스 식각공정시 손상되는 반도체 기판(11)의 식각손상을 보상하기 위한 자기정렬 소오스 열처리 공정이 실시된다. 그런 다음, 자기정렬 게이트 셀 소오스/드레인 이온 주입(self align gate cell junction implant)공정을 진행하여 상기 활성영역(12)에 소오스 및 드레인 접합부(24,25)가 형성된다.Referring to FIG. 1, a source line 23 is formed by performing a self-aligned source etching process using a self-aligned source (SAS) etching mask. Subsequently, a self alignment source heat treatment process is performed to compensate for the etch damage of the semiconductor substrate 11 which is damaged during the self alignment source etching process. Then, source and drain junctions 24 and 25 are formed in the active region 12 by performing a self align gate cell source / drain ion implantation process.
즉, 본 발명은 스택 구조의 게이트전극을 형성한 후, 도 3에 도시된 바와 같이 전체 구조 상부에 저온 산화막(22)을 증착하고, 그 상부에 N2LATID 이온 주입공정을 진행하여 상기 저온 산화막(22)의 소정 부위에 질소 이온주입 산화층(22a)을 형성한다. 따라서, ONO 구조의 유전체막(16)과 저온 산화막(22) 사이에 질소 이온주입 산화층(22a)을 형성함으로써, 상기 질소 이온주입 산화층(22a)으로 하여금 후속 공정인 SAS 열처리공정을 포함한 소정의 열처리공정에 의한 스트레스가 유전체막(16)으로 가해지는 것을 차단하게 하여 유전체막(16)의 스마일링의 현상을 억제할 수 있다.That is, in the present invention, after forming a gate electrode having a stacked structure, a low temperature oxide film 22 is deposited on the entire structure as shown in FIG. 3, and a N 2 LATID ion implantation process is performed on the low temperature oxide film. The nitrogen ion implantation oxide layer 22a is formed in the predetermined part of (22). Therefore, by forming the nitrogen ion implantation oxide layer 22a between the ONO structure dielectric film 16 and the low temperature oxide film 22, the nitrogen ion implantation oxide layer 22a is subjected to a predetermined heat treatment including a subsequent SAS heat treatment process. It is possible to prevent the stress caused by the process from being applied to the dielectric film 16, thereby suppressing the phenomenon of the smiling of the dielectric film 16.
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 스택 구조의 게이트전극을 형성한 후, 전체 구조 상부에 저온 산화막으로 TEOS막을 증착하고, 그 상부에 N2LATID 이온 주입공정을 진행하여 상기 TEOS막의 소정 부위에 질소 이온주입 산화층을 형성함으로써, 상기 질소 이온주입 산화층으로 하여금 후속 공정인 SAS 열처리공정을 포함한 소정의 열처리공정에 의한 스트레스가 유전체막으로 가해지는 것을 차단하게 하여 유전체막의 스마일링의 현상을 억제할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and after forming a gate electrode having a stacked structure, depositing a TEOS film with a low temperature oxide film over the entire structure, and performing a N 2 LATID ion implantation process thereon, thereby predetermining the TEOS film. By forming the nitrogen ion implantation oxide layer at the site, the nitrogen ion implantation oxide layer is prevented from applying stress to the dielectric film by a predetermined heat treatment process including a subsequent SAS heat treatment process to suppress the phenomenon of the smiling of the dielectric film. can do.
또한, N2LATID 이온 주입공정을 진행하여 상기 TEOS막의 소정 부위에 질소 이온주입 산화층을 형성함으로써, 종래의 CVD를 이용한 캡핑 질화막과 같은 후속 증착공정을 필요로 하지 않아 그 만큼 공정이 단순해질 수 있다.In addition, by performing a N 2 LATID ion implantation process to form a nitrogen ion implantation oxide layer on a predetermined portion of the TEOS film, a subsequent deposition process such as a capping nitride film using a conventional CVD is not required, and thus the process can be simplified. .
또한, N2LATID 이온 주입공정을 블랭켓으로 진행함으로써, 마스크 공정이 필요하지 않아 그 만큼 공정이 단순해질 수 있다.In addition, by performing the N 2 LATID ion implantation process as a blanket, a mask process is not necessary and the process can be simplified.
또한, 유전체막의 측벽에 질소 이온주입 산화층을 형성함으로써, 상기 유전체막의 스마일링을 억제하여 균일한 채널 길이를 확보할 수 있어 안정된 셀 트랜지스터의 문턱전압을 얻을 수 있다.In addition, by forming a nitrogen ion implantation oxide layer on the sidewall of the dielectric film, it is possible to suppress the smiling of the dielectric film and to ensure a uniform channel length, thereby obtaining a stable threshold voltage of the cell transistor.
더 나아가, 셀 어레이내의 셀 트랜지스터 간의 전류를 균일하게 형성할 수 있으며, 셀 트랜지스터의 동작시 더 적은 펄스 수에 의한 셀 동작이 가능해지고, 이로 인해 셀 트랜지스터의 동작시 프로그램 및 소거 상태에 대해 슬로우(slow) 및 패스트(fast) 구동을 보이는 셀 트랜지스터를 감소시킬 수 있다.Furthermore, the current between the cell transistors in the cell array can be uniformly formed, and the cell operation can be performed by a smaller number of pulses during the operation of the cell transistor, thereby slowing down the program and erase states during the operation of the cell transistor. It is possible to reduce cell transistors showing slow and fast driving.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100616671B1 (en) * | 2005-02-07 | 2006-08-28 | 삼성전기주식회사 | Method for manufacturing a semiconductive chip device having an insulated layer, and the semiconductive chip device manufactured therefrom |
| KR100824918B1 (en) * | 2005-01-17 | 2008-04-23 | 주식회사 하이닉스반도체 | Flash memory cell and method of manufacturing thereof |
| KR100932135B1 (en) * | 2007-12-27 | 2009-12-16 | 주식회사 동부하이텍 | Flash memory device manufacturing method |
| KR100947945B1 (en) * | 2007-11-30 | 2010-03-15 | 주식회사 동부하이텍 | Method for fabricating semiconductor device |
| KR100956595B1 (en) * | 2003-06-30 | 2010-05-11 | 주식회사 하이닉스반도체 | Fabricating method of protecting tungsten contamination in semiconductor device |
| KR101037688B1 (en) * | 2003-11-21 | 2011-05-30 | 매그나칩 반도체 유한회사 | Method for fabricating semiconductor device |
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2001
- 2001-06-29 KR KR1020010038422A patent/KR20030002722A/en not_active Application Discontinuation
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100956595B1 (en) * | 2003-06-30 | 2010-05-11 | 주식회사 하이닉스반도체 | Fabricating method of protecting tungsten contamination in semiconductor device |
| KR101037688B1 (en) * | 2003-11-21 | 2011-05-30 | 매그나칩 반도체 유한회사 | Method for fabricating semiconductor device |
| KR100824918B1 (en) * | 2005-01-17 | 2008-04-23 | 주식회사 하이닉스반도체 | Flash memory cell and method of manufacturing thereof |
| KR100616671B1 (en) * | 2005-02-07 | 2006-08-28 | 삼성전기주식회사 | Method for manufacturing a semiconductive chip device having an insulated layer, and the semiconductive chip device manufactured therefrom |
| KR100947945B1 (en) * | 2007-11-30 | 2010-03-15 | 주식회사 동부하이텍 | Method for fabricating semiconductor device |
| KR100932135B1 (en) * | 2007-12-27 | 2009-12-16 | 주식회사 동부하이텍 | Flash memory device manufacturing method |
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