KR100593154B1 - Cell of nonvolatile memory device and method for manufacturing the same - Google Patents

Abstract

According to the present invention, in a cell of a nonvolatile memory device having a structure in which a control gate is formed to overlap both sidewalls of the floating gate, the nonvolatile memory device can increase the coupling ratio by increasing the overlap area between the floating gate and the control gate. The present invention relates to a cell, and a method of manufacturing the same, which includes a substrate, a tunnel oxide film formed on the substrate, a floating gate formed on the tunnel oxide film, a first dielectric film formed on the floating gate, A first control gate formed on the first dielectric film, a second dielectric film formed on both sidewalls of the first control gate, the first dielectric film, and the floating gate, and both sidewalls of the second dielectric film so as to overlap the floating gate. A second control gate formed on the second control gate and exposed to both sides of the second control gate; A nonvolatile comprising a source / drain region formed in the first and second control gates and a metal silicide layer respectively formed on the source / drain region to electrically connect the first and second control gates. Provides a cell of a memory device.

Nonvolatile Memory Devices, EEPROMs, Coupling Ratios, Programs

Description

CELL OF NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME             

1 is a plan view illustrating a cell array formed through a cell manufacturing method of a nonvolatile memory device according to the prior art.

FIG. 2 is a cross-sectional view of a cell of a nonvolatile memory device taken along a cut line 'A-A' shown in FIG.

3 is a cross-sectional view illustrating a cell of a nonvolatile memory device according to a preferred embodiment of the present invention.

4A to 4K are cross-sectional views illustrating a cell manufacturing method of the nonvolatile memory device shown in FIG. 3.

<Explanation of symbols for the main parts of the drawings>

110 semiconductor substrate 111 tunnel oxide film

112: floating gate 113: first dielectric film

114: first control gate 115: buffer oxide film

116: hard mask 118: sidewall oxide film

119 sidewall nitride film 121 gate oxide film

122: control gate 125a, 125b: DDD region

126: spacer 128a, 128b: source / drain region

129 mask 130 metal silicide layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell of a nonvolatile memory device (NVM) and a method of manufacturing the same. In particular, a nonvolatile memory having a structure in which a control gate is formed to overlap both sidewalls of a floating gate. A cell of a device and a method of manufacturing the same.

The semiconductor memory device may be classified into a volatile memory device and a nonvolatile memory device. Volatile memory devices lose their data when their power supplies are interrupted, such as DRAM (Dynamic Random Access Memory) devices and static RAM (SRAM) devices. Nonvolatile memory devices include memory devices that retain data of the memory device even when a power supply is cut off, such as EEPROM devices and flash devices.

Program operation in a nonvolatile memory device is performed by F-N tunneling and hot electron injection. The F-N tunneling method is a method in which a program operation is performed by applying a high electric field to a gate insulating film to inject electrons into a floating gate from a semiconductor substrate. The hot electron injection method is a method in which a hot electron generated in a channel region near a drain is injected into a floating gate to perform a program operation. Meanwhile, an erase operation of the nonvolatile memory device is performed by releasing electrons injected into the floating gate into the semiconductor substrate or the source through a program operation.

Specifically, when a high voltage is applied to the control gate, the program operation may be floated by a capacitance ratio between the control gate and the floating gate and a capacitance ratio between the floating gate and the substrate (hereinafter referred to as a coupling ratio). A predetermined voltage is induced at the gate. Electrons are injected from the substrate into the floating gate by the induced voltage. That is, electrons are injected into the floating gate through the F-N tunneling method. As a result, the threshold voltage of the channel is increased by the electrons injected into the floating gate. The erase operation is reversed to the program operation. A high voltage is applied to the substrate to emit electrons injected into the floating gate. Of course, in this case also uses the F-N tunneling scheme. As a result, all of the electrons injected into the floating gate are emitted to lower the threshold voltage of the channel. The data is stored in the cell through the threshold voltage which is changed by the program and erase operations.

Hereinafter, a cell and a problem thereof of a nonvolatile memory device formed according to the prior art will be described with reference to FIGS. 1 and 2. 1 is a plan view of a cell array of a nonvolatile memory device, and FIG. 2 is a cross-sectional view taken along a cut line 'A-A' of FIG. 1.

As shown in FIG. 1 and FIG. 2, the control gate 18 is formed on both sidewalls of the floating gate 12 in the conventional nonvolatile memory device. In addition, a TiSi ₂ layer 22 is formed as a metal silicide layer on the control gate 18 and on the source / drain regions 21a and 21b, respectively. The tunnel oxide film 11 is interposed between the floating gate 12 and the semiconductor substrate 10, and the spacers 15, 16, and 17 having an ONO structure are interposed between the floating gate 12 and the control gate 18. . In addition, the upper portion of the floating gate 12 is covered with a buffer oxide layer 13 and a nitride mask-based hard mask 14. Meanwhile, '19a' and '19b', which are not shown and described in FIGS. 1 and 2, are doubled diffused drain (DDD) regions, '20' DDD spacers, '30' is an active region, and '40' Contact area.

However, as described above, in the cell structure of the nonvolatile memory device according to the related art, the control gate 18 is formed so as to overlap only on both side walls of the floating gate 12, thereby increasing the coupling ratio. As described above, since the coupling ratio is closely related to the program operating characteristics, when the coupling ratio is increased, even though the same voltage is applied, the coupling ratio increases, and thus the threshold voltage may be higher. In another aspect, the bias voltage applied to the control gate can be lowered to obtain the same threshold voltage. Lowering the applied voltage has many benefits in terms of cell reliability.

Accordingly, the present invention has been proposed to solve the above-described problems of the prior art, and in a cell of a nonvolatile memory device having a structure in which a control gate is formed so as to overlap both side walls of the floating gate, an overlap between the floating gate and the control gate is provided. It is an object of the present invention to provide a cell of a nonvolatile memory device and a method of manufacturing the same that can increase the coupling ratio by increasing the area.

According to an aspect of the present invention, there is provided a substrate, a tunnel oxide film formed on the substrate, a floating gate formed on the tunnel oxide film, a first dielectric film formed on the floating gate, and the first material. A first control gate formed on the first dielectric film, a second dielectric film formed on both sidewalls of the first control gate, the first dielectric film, and the floating gate, and both sidewalls of the second dielectric film so as to overlap the floating gate. A second control gate formed at the gate, a source / drain region formed at the substrate exposed to both sides of the second control gate, and the first and second control gates to electrically connect the first and second control gates. A cell of a nonvolatile memory device comprising a top and a metal silicide layer formed on the source / drain regions, respectively. do.

In addition, according to another aspect of the present invention, there is provided a substrate in which a tunnel oxide film, a floating gate, a first dielectric film, a first control gate, a buffer oxide film, and a hard mask are sequentially stacked; Sequentially depositing a sidewall oxide film and a sidewall nitride film along a step on the substrate, etching the sidewall nitride film to leave the sidewall nitride film on both sidewalls of the sidewall oxide film, and the remaining sidewall nitride film Depositing an oxide film along a step on top of the structure, forming a second control gate on both sidewalls of the oxide film so as to overlap the floating gate, and source / exposed to the substrate exposed to both sides of the second control gate. Forming a drain region, and an etching mask having an open portion overlapping an upper portion of the hard mask; Exposing an upper portion of the first control gate by using an etching process, and forming a metal silicide layer on the upper portions of the first and second control gates and on the source / drain regions. A method of manufacturing a cell of a nonvolatile memory device is provided.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

Example

3 is a cross-sectional view illustrating a cell of a nonvolatile memory device according to a preferred embodiment of the present invention.

Referring to FIG. 3, a cell of a nonvolatile memory device according to an exemplary embodiment of the present invention may include a floating gate 112 separated from a semiconductor substrate 110 through a tunnel oxide film 111, and a dielectric film 113. The first control gate 114 overlapping the upper portion of the floating gate 112 and the insulating layers 118, 119, and 121 forming an oxide / nitride / oxide (ONO) structure overlapping both sidewalls of the floating gate 112. The second control gate 122 and source / drain regions 128a and 128b formed on the substrate 110 exposed to both sides of the second control gate 122 are included. In addition, metal silicide layers 130 are formed on the first and second control gates 114 and 122 and on the source / drain regions 128a and 128b, respectively. The first and second control gates 114 and 122 are electrically connected to each other by the metal silicide layer 130.

The cell of the nonvolatile memory device according to the preferred embodiment of the present invention having the above-described structure forms the first control gate 114 to overlap not only both side walls of the floating gate 112 but also the upper portion, and the first control. By interposing a dielectric film 113 between the gate 114 and the floating gate 112, the overlapping area between the floating gates can be increased by the area of the first control gate 114 than the cell structure according to the related art shown in FIG. 2. Can be.

With this structure, when the bias voltage is applied to the first and second control gates 114 and 122 at the same time during the program operation, the voltage induced in the floating gate 112 increases with the increase in the coupling ratio so that the program Operation characteristics can be improved.

Hereinafter, a method of manufacturing a cell of a nonvolatile memory device according to an exemplary embodiment of the present invention shown in FIG. 3 will be described with reference to FIGS. 4A to 4K. Here, the same reference numerals among the reference numerals shown in FIGS. 4A to 4K are the same elements performing the same function.

As shown in FIG. 4A, a semiconductor substrate 110 in which an active region and a field region are defined by an isolation layer (or a field oxide layer) (not shown) formed through a shallow trench isolation (STI) process is provided.

Subsequently, a well region and a threshold voltage ion implantation process are performed to form a well region (not shown) in a predetermined region of the semiconductor substrate 110. In this case, the well region forming process may be formed before forming the device isolation layer according to the device manufacturing process. This may be adjusted accordingly.

Subsequently, an oxidation process is performed on the substrate 110 to form the tunnel oxide film 111. At this time, the oxidation process is carried out in a dry or wet oxidation process. Thereafter, the annealing process may be performed.

Subsequently, a floating silicon polysilicon film 112 is deposited on the tunnel oxide film 111. In this case, the polysilicon film 112 is formed of an undoped or doped silicon film. For example, the deposition using LPCVD (Low Pressure Chemical Vapor Deposition) method using Si ₂ H ₆ or Si ₂ H ₆ and PH ₃ gas.

Subsequently, an ONO structure dielectric film 113 is formed on the polysilicon film 113. At this time, the oxide film 113a, which is the lower layer of the dielectric film 113, is formed by a thermal oxidation process or is formed by a CVD method. The intermediate layer nitride film 113b is deposited by CVD, plasma enhanced CVD (PECVD) or atmospheric pressure CVD (APCVD). An oxide layer 113c, which is an upper layer, is deposited by CVD.

Next, the polysilicon film 114 for the first control gate is deposited on the dielectric film 113. At this time, the polysilicon film 114 is deposited by LPCVD using Si ₂ H ₆ or Si ₂ H ₆ and PH ₃ gas.

Next, a buffer oxide film 115 is deposited on the polysilicon film 114. In this case, the buffer oxide film 115 serves to protect the polysilicon film 114 for the first control gate from the stress applied during the deposition process of the hard mask 116 formed through a subsequent process.

Next, a hard mask 116 is formed on the polysilicon film 114 in an insulating film series.

Subsequently, as shown in FIG. 4B, the hard mask 116 is etched by performing a photolithography process.

Subsequently, an etching process 117 using the etched hard mask 116 is performed to sequentially etch the buffer oxide film 115, the polysilicon film 114, the dielectric film 113, and the polysilicon film 112. As a result, a profile of the first control gate 114 and the floating gate 112 is defined.

Subsequently, as shown in FIG. 4C, the sidewall oxide layer 118 and the sidewall nitride layer 119 are sequentially deposited on the entire structure where the floating gate 112 is defined. In this case, the sidewall oxide film 118 is deposited by CVD, and the sidewall nitride film 119 is deposited by LPCVD.

Next, as illustrated in FIG. 4D, an etch back process 120 is performed to etch the sidewall nitride layer 119. As a result, the sidewall nitride film 119 remains only on the sidewall of the pad oxide film 118.

Subsequently, as illustrated in FIG. 4E, the oxide film 121 is formed along the step of the upper portion of the entire structure after the etch back process. At this time, the oxide film 121 is a gate insulating film for a high voltage gate, and is formed of a high temperature low pressure dielectric (HLD) oxide film. Here, the gate insulating film for a high voltage gate is a gate insulating film of a high voltage transistor for driving an EEPROM cell when the EEPROM cell is implemented in a chip together with a logic element.

The sidewall oxide film 118, the sidewall nitride film 119, and the oxide film 121 are interposed between the floating gate 112 and the second control gate 22 to function as a dielectric film in an ONO structure.

Next, the polysilicon film 122 for the second control gate is deposited to cover the oxide film 121. At this time, the polysilicon film 122 is deposited by LPCVD using Si ₂ H ₆ or Si ₂ H ₆ and PH ₃ gas.

Next, as illustrated in FIG. 4F, an etch back process 123 is performed to etch the polysilicon film 122. As a result, a profile of the second control gate 122 is defined such that a portion overlaps the active region so that a portion of the active region is exposed, and a portion overlaps both sidewalls of the floating gate 112.

Next, as illustrated in FIG. 4G, the DDD ion implantation process 124 is performed to form the DDD regions 125a and 125b on the substrate 110 exposed to both sides of the second control gate 122. Here, the reason for performing the DDD ion implantation process 124 is to prevent the drain region from being damaged by the high voltage applied to the drain region during the program operation.

Subsequently, as shown in FIG. 4H, spacers 126 are formed on a part of both side walls of the second control gate 122. In this case, the spacer 126 is formed of a nitride film-based material.

Subsequently, the source / drain ion implantation process 127 is performed to form source / drain regions 128a and 128b in the DDD regions 125a and 125b exposed through the spacer 126, respectively.

Subsequently, as shown in FIG. 4I, only the region overlapping the upper portion of the hard mask 116 is formed to form an open mask 129. At this time, the mask 129 is a photoresist or an anti-reflection film. Here, the antireflection film may be either an organic or inorganic antireflection film.

Subsequently, as illustrated in FIG. 4J, the etching process using the mask 129 is performed to remove the oxide film 121, the hard mask 116, and the buffer oxide film 115 exposed through the mask 129. As a result, an upper portion of the first control gate 114 is exposed.

Subsequently, as shown in FIG. 4K, Ti, Co, Ti / TiN, or Co / TiN is deposited along the step of the upper portion of the entire structure where the first control gate 114 is exposed, and then subjected to a heat treatment process. TiSi ₂ or CoSi ₂ layer 130, which is a metal silicide layer, is formed on the second control gates 114 and 122 and on the source / drain regions 128a and 128b, respectively. As a result, the first and second control gates 114 and 122 are electrically connected to each other by the metal silicide layer.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, in a cell of a nonvolatile memory device having a structure in which a control gate is formed so as to overlap both side walls of the floating gate, the control gate is formed so as to overlap not only both side walls of the floating gate but also the top. By forming, the overlapping area between the floating gate and the control gate can be increased to increase the coupling ratio. Through this, the program operating characteristics of the nonvolatile memory device can be improved.

Claims (8)

Board; A tunnel oxide film formed on the substrate; A floating gate formed on the tunnel oxide film; A first dielectric layer formed on the floating gate A first control gate formed on the first dielectric layer; A second dielectric layer formed on both sidewalls of the first control gate, the first dielectric layer, and the floating gate; Second control gates formed on both sidewalls of the second dielectric layer to overlap the floating gate; Source / drain regions formed in the substrate exposed to both sides of the second control gate; And Metal silicide layers formed on top of the first and second control gates and on the source / drain regions, respectively, to electrically connect the first and second control gates; A cell of a nonvolatile memory device comprising a. The method of claim 1, And the source / drain region is formed in a DDD region formed in the substrate. The method of claim 1, And the first and second dielectric layers are formed in an ONO structure. Providing a substrate in which a tunnel oxide film, a floating gate, a first dielectric film, a first control gate, a buffer oxide film, and a hard mask are sequentially stacked; Sequentially depositing sidewall oxide films and sidewall nitride films along the steps on the substrate; Etching the sidewall nitride film to leave the sidewall nitride film on both sidewalls of the sidewall oxide film; Depositing an oxide film along a step above an entire structure including the remaining sidewall nitride film; Forming second control gates on both sidewalls of the oxide layer to overlap the floating gate; Forming a source / drain region in the substrate exposed at both sides of the second control gate; Exposing an upper portion of the first control gate by performing an etching process using an etching mask in which an area overlapping an upper portion of the hard mask is opened; And Forming a metal silicide layer on top of the first and second control gates and on top of the source / drain regions; Cell manufacturing method of a nonvolatile memory device comprising a. The method of claim 4, wherein And the first and second control gates are electrically connected to each other by the metal silicide layer. The method of claim 4, wherein And the etching mask is formed of a photoresist or an anti-reflection film. The method of claim 4, wherein Forming a DDD region in the substrate exposed to both sides of the second control gate before forming the source / drain region; And Forming spacers on both sides of the second control gate; Cell manufacturing method of a nonvolatile memory device further comprising. The method of claim 7, wherein And forming the DDD region deeper than the source / drain region.

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