KR100536799B1 - semiconductor device and fabricating method thereof - Google Patents

Abstract

An ONO triple layer, a polycrystalline silicon film, and a nitride film are stacked and selectively etched on the semiconductor substrate to form an upper insulating film, a SONOS gate electrode, and an ONO triple layer. A sidewall insulating film is formed on the side of the SONOS gate electrode, a gate oxide film is formed on the semiconductor substrate, and then a pass and recall gate electrode is formed on the side of the sidewall insulating film on the gate oxide film. The source region and the drain region are formed by doping impurity ions into the semiconductor substrate using the gate electrodes and the sidewall insulating film as masks. An interlayer insulating film is formed over the pass and recall gate electrodes, and a via hole exposing the gate electrodes and the source and drain regions is formed. A plug filling the via hole is formed, and a wiring is formed on the interlayer insulating film.

Description

Semiconductor device and fabrication method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device using a silicon-oxide-nitride-oxide-silicon (SONOS) structure.

Among the semiconductor memory devices, the nonvolatile memory device is characterized in that prior data is not destroyed even when power is not supplied.

Semiconductor nonvolatile memory that can read and write digital data electrically includes EEPROM, which can be erased and written in units of cells, and flash memory that can erase and write data in blocks of tens or hundreds of bytes or more. There are two kinds.

The nonvolatile memory may be implemented using a SONOS cell structure or a floating gate.

Among them, nonvolatile memory using the SONOS cell structure includes two SONOS transistors for storing respective "H" and "L" states stored in the volatile memory latch when the power is turned off, reading of the SONOS transistor, Six transistors, two pass gates and two recall gates, for controlling write, erase, and the like, form one memory element. Therefore, the nonvolatile memory using the SONOS structure has a large area occupied by one device, making it difficult to integrate.

The structure of a conventional SONOS cell will now be described with reference to the drawings.

1 and 2 are cross-sectional views of SONOS cells of a nonvolatile memory according to the prior art.

First, referring to FIG. 1, a source region 11 and a drain region 12 doped with N-type impurities are formed on a semiconductor substrate 10, and a gate oxide film 21 is formed on the semiconductor substrate 10. have.

A recall gate electrode 41 and a pass gate electrode 42 made of polycrystalline silicon are formed on the gate oxide film 21. At this time, the gate oxide film 21 is removed in the center region between the two gate electrodes 41 and 42.

A sidewall insulating film 23 is formed on the gate electrodes 41 and 42, and an ONO triple layer of the first oxide film 31, the nitride film 32, and the second oxide film 32 is formed on the sidewall insulating film 23. . At this time, the first oxide film 31 of the ONO triple layer is in contact with the surface of the semiconductor substrate 10 in the region where the gate oxide film 21 between the two gate electrodes 41 and 42 is removed.

The SONOS gate electrode 43 made of polycrystalline silicon is formed on the second oxide film 32 of the ONO triple layer, and the interlayer insulating film 50 is formed on the SONOS gate electrode 43.

At this time, the recall gate electrode 21 and the pass gate electrode 22 pass through the vias 61 and 62 passing through the interlayer insulating film 50, the ONO triple layers 31, 32, and 33, and the sidewall insulating film 23. The SONOS gate electrode 43 is connected to a wiring (not shown) through a via 63 penetrating through the interlayer insulating film 50. The source region 11 and the drain region 12 are vias 64 and 65 passing through the interlayer insulating film 50, the ONO triple layers 31, 32 and 33, the sidewall insulating film 23 and the gate oxide film 21. Is connected to a wiring (not shown).

Next, referring to FIG. 2, the source region 11, the source / drain regions 13 and 15, and the drain region 17 doped with N-type impurities are formed on the semiconductor substrate 10, and the N-type impurities are formed. The heavily doped LDD regions 12, 14, 16 are formed on one side of the source region 11, on both sides of the source / drain regions 13, 15, and on one side of the drain region 17, respectively.

An ONO triple layer made of a gate insulating film 21, a first oxide film 31, a nitride film 32, and a second oxide film 33 is formed on the semiconductor substrate 10.

A recall gate electrode 41 and a pass gate electrode 42 made of polycrystalline silicon are formed on the gate insulating film 21, and the second oxide film 33 of the ONO triple layer located between the two gate electrodes 41 and 42 is formed. ), A SONOS gate electrode 43 made of polycrystalline silicon is formed.

The gate electrodes 41, 42, 43 are covered with the protective oxide film 71, and the sidewall insulating film 72 is formed outside thereof, and the interlayer insulating film 50 is formed on the sidewall insulating film 72.

In this case, the three gate electrodes 21, 22, and 23 are connected to a wiring (not shown) through the vias 61, 62, and 63 passing through the interlayer insulating film 50 and the protective oxide film 71. The source region 11 and the drain region 17 are connected to a wiring (not shown) through the vias 64 and 65 passing through the interlayer insulating film 50 and the gate oxide film 21.

1 and 2, in the structure of a SONOS cell according to the related art, multiple insulating layers are formed between the SONOS gate 43, the recall gate 41, and the pass gate 42 so that the area occupied by them is reduced. Difficult to reduce

The technical problem to be achieved by the present invention is to reduce the area occupied by semiconductor devices using the SONOS structure.

In order to solve this problem, the present invention provides a semiconductor substrate having a source region and a drain region, a gate oxide film formed on the source region and the drain region of the semiconductor substrate, between the source region and the drain region on the semiconductor substrate. An oxide film / nitride film / oxide film triple layer formed, a SONOS gate electrode formed on the oxide film / nitride film / oxide film triple layer, a sidewall insulating film formed on the side of the SONOS gate electrode, and formed on the gate oxide film, and the sidewall insulating film A semiconductor device including second and third gate electrodes formed on side surfaces of a semiconductor device is provided.

In this case, an upper insulating film formed on the first gate electrode, an upper insulating film, an interlayer insulating film formed on the first and second gate electrodes, a wiring formed on the interlayer insulating film, the source region, and the drain region. And a plurality of vias connecting the first to third gate electrodes and the wiring, wherein the sidewall insulating layer is in contact with the surface of the semiconductor substrate between the gate oxide layer and the oxide layer / nitride layer / oxide layer triple layer. desirable. In addition, the upper insulating film may be a nitride film.

In the semiconductor device, the first to third insulating films, the polycrystalline silicon film, and the fourth insulating film are stacked on the semiconductor substrate and selectively etched to form a triple layer of an upper insulating film, a first gate electrode, and an oxide film / nitride film / oxide film. Forming a sidewall insulating film on a side of the first gate electrode, forming a gate oxide film on the semiconductor substrate, forming second and third gate electrodes on a side of the sidewall insulating film on the gate oxide film, the second And forming a source region and a drain region by doping impurity ions to the semiconductor substrate using the first to third gate electrodes and the sidewall insulating layer as a mask.

In this case, forming an interlayer insulating film on the second and third gate electrodes, forming a via hole exposing the source and drain regions of the first to third gate electrodes, and forming a plug filling the via hole. The method may further include forming a wiring on the interlayer insulating film, wherein the first and third insulating films are oxide films, and the second and fourth insulating films are nitride films.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A semiconductor device according to an embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view of a SONOS cell of a nonvolatile memory in accordance with an embodiment of the present invention.

The source region 11 and the drain region 12 doped with N-type impurities are formed on the semiconductor substrate 10.

The triple layer of ONO (Oxide-Nitride_Oxide) formed of the gate oxide film 21, the first oxide film 31, the nitride film 32, and the second oxide film 33 is formed on the surface of the semiconductor substrate 10. A sidewall insulating film 71 is formed on the surface of the semiconductor substrate 10 between the gate oxide film 21 and the ONO triple layer.

Here, the gate oxide film 21 is disposed on the source region 11 and the drain region 12, and the ONO triple layer is formed between the source region 11 and the drain region 12.

A SONOS gate electrode 43 made of polycrystalline silicon or a metal is formed on the ONO triple layer. The side surface of the SONOS gate electrode 43 is surrounded by the sidewall insulating film 71, and the upper insulating film 72 is formed on the SONOS gate electrode 43.

On the gate oxide film 21, a recall gate electrode 41 and a pass gate electrode 42 are formed in close contact with the side surface of the sidewall insulating film 71. The electrodes may be made of polycrystalline silicon or metal. In the semiconductor device having a plurality of transistors, the triple gate structure may reduce the area of the device by forming a plurality of gates on the side of the semiconductor device regardless of the type of the device, the type of the gate, and the arrangement of the gates.

An interlayer insulating film 50 is formed on the recall gate electrode 41, the pass gate electrode 42, and the upper insulating film 72.

Here, the recall gate electrode 41 and the pass gate electrode 42 are connected to a wiring (not shown) formed on the interlayer insulating layer 50 through vias 61 and 62 formed in the interlayer insulating layer 50. The SONOS gate electrode 41 is connected to a wiring (not shown) on the interlayer insulating film 50 through a via 63 passing through the interlayer insulating film 50 and the upper insulating film 72. The source region 11 and the drain region 12 are wirings (not shown) formed on the interlayer insulating film 50 through vias 64 and 65 passing through the interlayer insulating film 50 and the gate oxide film 21. )

When the SONOS cell is formed in such a structure, since only one sidewall insulating film 71 exists between the recall and pass gates 41 and 42 and the SONOS gate 43, the area occupied by the SONOS cell is reduced compared with the prior art. In addition, since the recall and pass gates 41 and 42 are formed in close contact with the sidewall insulating film 71 in the form of sidewalls, the area occupied by the SONOS cell is reduced compared with the prior art.

In such a structure, when a predetermined high voltage H is applied to the pass gate electrode 43 and a predetermined low voltage L is applied to the drain region 12, the semiconductor substrate 10 under the SONOS gate electrode 42 is formed. The low voltage causes most of the program voltage applied to the SONOS gate electrode 42 to be applied to the ONO triple layer. As a result, a program operation occurs in which electrons collected on the surface of the semiconductor substrate 10 tunnel through the lower tunnel oxide film 31 of the ONO triple layer to be trapped by the nitride film 32 of the ONO triple layer. Increase the threshold voltage of the SONOS transistor.

On the other hand, when the high voltage H is applied to both the pass gate electrode 43 and the drain region 12, the channel under the pass gate is turned off. In this state, the semiconductor substrate 10 under the SONOS gate electrode is placed in a deep depletion state by a program voltage applied to the SONOS gate electrode 42. In this deep depletion state, most of the program voltage applied to the SONOS gate is applied to the deep depletion region, and almost no electric field is applied to the ONO triple layer. Therefore, a program operation in which electrons tunnel through the tunnel oxide film and traps the nitride film does not occur. Do not. This phenomenon is called DWI (Dynamic Write Inhibition).

The semiconductor device according to the present invention stores information by using a threshold voltage increase due to electron trapping of a nitride film and a phenomenon maintaining phenomenon due to DWI.

4A through 4E are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

First, an isolation region (not shown) defining an active region is formed on the semiconductor substrate 10 by using a local oxidation silicon (LOCOS) or shallow trench isolation (STI) scheme. The LOCOS method forms a device isolation region by oxidizing a predetermined region of the substrate 10. The STI method forms a device isolation region by forming a trench in the substrate and then filling an insulating material.

Next, the first oxide film 31, the first nitride film 32, the second oxide film 33, the polycrystalline silicon film, and the second nitride film are sequentially stacked on the active region of the semiconductor substrate 10.

The first oxide film 31 is formed by oxidizing the semiconductor substrate 10 to a thickness of 15 to 30 μm, and the second oxide film 33 is deposited by a method such as CVD (chemical vapor deposition). Form. The first nitride film 32 and the second nitride film are deposited by CVD to form a thickness of 60 to 200 mW and 500 to 1,500 mW, respectively. In addition, the metal gate or the polycrystalline silicon film is formed by depositing the doped polycrystalline silicon by a method such as CVD to a thickness of 1,000 ~ 3,000Å.

Next, after the photoresist pattern is formed on the second nitride film, the second nitride film and the polysilicon film are etched using a dry etching method using plasma using the photoresist pattern as an etch mask. 72 and a SONOS gate electrode 43.

4B, the ONO triple layers 31, 32, and 33 are etched using the photoresist pattern used for forming the upper insulating film 72 and the SONOS gate electrode 43 as an etching mask.

As shown in FIG. 4C, an oxide film is deposited and patterned by a selective etching method to form a sidewall insulating film 71.

The sidewall insulating layer 71 is formed to have a thickness of 5 to 300 kV so as not to be destroyed even when a high voltage is applied to the SONOS gate electrode 43.

Next, as shown in FIG. 4D, the surface of the semiconductor substrate 10 is oxidized to form a gate oxide film 21. It is formed in a range of 20 to 200 kHz so as not to be destroyed by voltages applied to the source, the drain region, the gate electrode and the like.

Subsequently, as shown in FIG. 4E, the polysilicon film is formed on the gate oxide film 21 to a thickness of 1,000 to 3,000 kPa, and then the dry etching is performed using a selective etching process to closely adhere to the side surface of the sidewall insulating film 71. The gate electrode 41 and the pass gate electrode 42 are formed.

As shown in FIG. 4F, the source region 11 and the drain region 12 are doped by doping N-type impurity ions into the active region using the gate electrodes 41, 42, 43, and the sidewall insulating layer 71 as a self-aligning mask. To form.

A process of forming a lightly doped region (not shown) may be added before forming the source region 11 and the drain region 12. To form a low concentration doped region, first, dopant ions are lightly doped in an active region of the semiconductor substrate 10, and spacers having a predetermined thickness are formed on sidewalls of the recall gate electrode 41 and the pass gate electrode 42. . Thereafter, an impurity doping process for forming source and drain regions is performed in the active region. This forms a lightly doped region only under the spacer.

Next, as shown in FIG. 3, after the interlayer insulating film 50 is formed of an insulating material such as PE-TEOS, FSG, USG, the via hole and the gate electrode 41 exposing the source region 11 and the drain region 12. To form via holes exposing 42, 43 respectively. The via hole is filled with metal such as tungsten to form a plug to complete the via.

Thereafter, a metal film is formed on the interlayer insulating film 50, and then the metal film is patterned by a selective etching process to form a metal wiring layer connected to the vias 61, 62, 63, 64, and 65. Thereafter, several more interlayer insulating films and metal wiring layers may be formed.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

According to an embodiment of the present invention, since only one sidewall insulating film exists between the recall and pass gate and the SONOS gate, and the recall and pass gate are formed in close contact with the sidewall insulating film, the area occupied by the SONOS cell is reduced. .

1 and 2 are cross-sectional views of SONOS cells of a nonvolatile memory according to the prior art.

3 is a cross-sectional view of a SONOS cell of a nonvolatile memory in accordance with an embodiment of the present invention.

4A through 4F are cross-sectional views illustrating a manufacturing process of a nonvolatile memory in accordance with an embodiment of the present invention.

Claims (10)

delete delete A semiconductor substrate having a source region and a drain region, A gate insulating film formed on the source region and the drain region of the semiconductor substrate, An oxide film / nitride film / oxide film triple layer formed between the source region and the drain region on the semiconductor substrate, A SONOS gate electrode formed on the oxide layer / nitride layer / oxide layer triple layer; A sidewall insulating film formed on a side of the SONOS gate electrode, Second and third gate electrodes formed on the gate oxide layer and formed on side surfaces of the sidewall insulating layer. Semiconductor device comprising a. In claim 3, An upper insulating film formed on the first gate electrode, An interlayer insulating layer formed on the upper insulating layer, the first and second gate electrodes, Wiring formed on the interlayer insulating film, A plurality of vias connecting the source region, the drain region, and the first to third gate electrodes to the wiring; A semiconductor device further comprising. In claim 4, And the sidewall insulating film is in contact with a semiconductor substrate surface between the gate oxide film and the oxide film / nitride film / oxide film triple layer. In claim 4, The upper insulating film is a semiconductor device. Stacking and selectively etching the first to third insulating films, the polycrystalline silicon film, and the fourth insulating film on the semiconductor substrate to form a triple layer of the upper insulating film, the first gate electrode, and the oxide film / nitride film / oxide film, Forming a sidewall insulating film on a side of the first gate electrode; Forming a gate insulating film on the semiconductor substrate, Forming second and third gate electrodes on side surfaces of the sidewall insulating film over the gate oxide film, Forming a source region and a drain region by doping impurity ions to the semiconductor substrate using the first to third gate electrodes and the sidewall insulating layer as a mask; Method for manufacturing a semiconductor device comprising a. In claim 7, Forming an interlayer insulating film on the second and third gate electrodes, Forming a via hole exposing the source and drain regions of the first to third gate electrodes; Forming a plug filling the via hole; Forming a wire on the interlayer insulating film Method of manufacturing a semiconductor device further comprising. In claim 8, And the first and third insulating layers and the second and fourth insulating layers are alternately formed of an oxide film or a nitride film. In claim 7, The sidewall insulating film is a semiconductor device manufacturing method of 5 ~ 300Å.