JP2000031436A - Semiconductor storage device and manufacture of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device with less current consumption, while larger capacity of a memory is made possible. SOLUTION: Each memory cell comprises diffused layers 2 and 3, which is formed on the surface of a p-type silicon substrate 1, to be a source/drain region, and a channel region 4 formed between the diffused layers 2 and 3. An insulating film 8 of lamination structure comprising a silicon oxide film 5, a silicon nitride film 6, and a silicon oxide film 7 is formed above the channel region 4. A gate electrode 9 is formed on the upper surface of the insulating film 8 of the laminated structure. The gate electrode 9 is utilized as a word line. An interlayer insulating film 10 is formed between the diffused layers 2 and 3 and the gate electrode 9. By implanting hot electrons into the silicon nitride film 8 in the insulating film 8 of lamination structure from a substrate, data is written. The silicon nitride film 6 and the diffused layer 3 partially overlap vertically, while an offset part 11 provided between the silicon nitride film 6 and the diffusion layer 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an electrically rewritable semiconductor memory device, and more particularly to a technique for forming a memory cell having a fine structure.

[0002]

2. Description of the Related Art FIG. 10 is a view showing a cell sectional structure of a conventional M (O) NOS type EEPROM. The memory cell of FIG. 10 has a memory transistor 53 formed on the upper surface of a p-type well region 52 on an n-type silicon substrate 51, and first and second select transistors 54 and 55. The gate insulating film 56 of the memory transistor 53 has a silicon oxide film 57 /
The silicon nitride film 58 / tunnel oxide film 59 has a laminated structure, and the silicon nitride film 58 is used as a charge storage layer for electrons directly and tunnel-injected from the substrate 52.

When writing data into an EEPROM having a structure as shown in FIG. 10, data is first erased from all memory cells in a predetermined cell block. More specifically, a high positive voltage is applied to the p-type well region 52, and electrons are emitted from the silicon nitride film 58 to the p-type well region 52 by direct tunneling. As a result, all the memory cells are normally on.

Next, data is written to a desired memory cell. Specifically, the first selection transistor 54,
An arbitrary memory cell is selected by designating a control gate of the memory transistor 53 and a bit line (not shown). Writing to the memory transistor 53 is performed by applying a high voltage to the first selection transistor 54 and the control gate 53 with the bit line at the ground level while the second selection transistor 55 is turned off. Thereby, electrons are directly tunnel-injected from the substrate 52 into the silicon nitride film 58.

The control gate 53 in FIG. 10 is shared by a plurality of memory cells, and the bit lines of the non-selected memory cells are set to an intermediate potential in order to avoid writing data to the non-selected memory cells. Also, the second selection transistor 5 is connected to prevent a through current from flowing from the bit line to the source side.
5 is set to the off state.

[0006]

The EEPROM shown in FIG.
It has the following problems.

The number of selection transistors is two for each memory cell.
Since the number is required, the cell size must be increased, and it is difficult to increase the memory capacity.

[0008] Since the charge written in the silicon nitride film is easily leaked to the substrate side by direct tunneling, that is, the structure is liable to cause charge loss, the charge retention characteristics are poor.

As a method for solving the above problems, a virtual ground type (Virtual Ground Array) EEPROM has been proposed.

FIG. 11 is a schematic sectional view of a virtual ground type EEPROM, and FIG. 2 is a circuit diagram showing an internal configuration of the EEPROM of FIG.

In a virtual ground type EEPROM, as shown in FIG. 2, a plurality of memory cells are arranged in a matrix, and control gates in memory cells in the same row are commonly connected to form a word line. . The sources and drains of memory cells adjacent in the column direction are connected to each other, and the sources and drains of the same column are commonly connected to form a column line.

As shown in FIG. 11, each memory cell includes a floating gate 61 and a control gate 62, and an n ⁺ diffusion layer used as a source region or a drain region is provided in a semiconductor substrate 63 thereunder. 64 and an n ^- diffusion layer 65 are formed. Specifically, n ⁻ diffusion layer 6 of n ⁺ diffusion layer 64
The side closer to 5 is the source region, and the opposite side is the drain region. In addition, the floating gate 61 has an n ⁺ diffusion layer 64.
And n ⁻ diffusion layer 65.

When writing data to the EEPROM of FIG.
The source diffusion layer is set to the ground level, and a high voltage is applied to the word line and the drain diffusion layer. Thus, hot electrons are injected into the floating gate 61 from the drain side.

An unselected cell adjacent to the source side of the selected cell has its drain diffusion layer at the ground level to avoid writing data. In addition, the non-selected cell adjacent to the drain side of the selected cell has its drain diffusion layer and source diffusion layer at the same potential to avoid writing data,
Reduce the program current.

The EEPROM shown in FIG. 11 has the following problems.

At the time of writing, a large program current of the mA level flows through the memory cell alone.

A pattern for forming a diffusion layer wiring, a selection transistor, and the like has a relatively large voltage drop, and thus has poor writing characteristics and a large variation in threshold voltage. For this reason, simultaneous multi-bit writing is difficult.

Because of the two-layer gate structure, the structure is complicated and the manufacturing process is complicated.

As described above, because of the problem described above,
Even if the circuit configuration of the EEPROM is a virtual ground type, good electrical characteristics cannot be obtained, and as a result, there is a problem that it is difficult to increase the capacity of the memory.

The present invention has been made in view of such a point, and an object of the present invention is to provide a semiconductor memory device which consumes less current and can realize a large memory capacity.

[0021]

In order to solve the above-mentioned problems, the invention according to claim 1 includes a first conductivity type semiconductor substrate,
A plurality of second conductivity type diffusion layer regions formed in parallel on the semiconductor substrate, and a first layer provided between the pair of adjacent diffusion layer regions and having one end in contact with one of the diffusion layer regions. A channel region, one end of which is the first channel region;
A second channel region having the other end in contact with the other diffusion layer region; a charge storage layer having a stacked structure formed on the first channel region; and a charge storage layer on the second channel region and the charge storage layer. A gate electrode formed substantially in parallel with the direction in which the diffusion layer regions are arranged on the layer with an insulating film interposed therebetween, wherein the threshold value of the second channel region below the gate electrode is set by the gate This is higher than the threshold value of the first channel region below the electrode.

The invention according to claim 8 is a step of forming an element isolation region on a semiconductor substrate, and forming an impurity ion for controlling a threshold on a semiconductor substrate in a cell region formed around the element isolation region. Implanting, forming a stacked insulating film composed of a silicon oxide film, a silicon nitride film for charge storage, and a silicon oxide film on a semiconductor substrate in a cell region, and including an upper surface of the stacked insulating film. Forming a polysilicon layer on the upper surface of the semiconductor substrate, and selectively removing the polysilicon layer and the laminated insulating film in a cell region;
Forming an opening for the drain region and an opening for the source region, and forming a drain region by implanting impurity ions into the opening for the drain region using a resist formed on the upper surface of the substrate as a mask. Forming a sidewall insulating film on a sidewall portion of each of the openings for the drain region and the source region; and using the resist formed on the upper surface of the substrate and the sidewall insulating film as a mask, Implanting impurity ions into the opening to form a source region; embedding an insulating material in each of the drain region and source region openings; and forming a polysilicon layer serving as a gate electrode on the upper surface of the substrate And a step of performing.

According to a ninth aspect of the present invention, there is provided a process for forming an element isolation region on a semiconductor substrate, and the step of forming an impurity ion for controlling a threshold value on the semiconductor substrate in a cell region formed around the element isolation region. Implanting, forming a stacked insulating film composed of a silicon oxide film, a silicon nitride film for charge storage, and a silicon oxide film on a semiconductor substrate in a cell region, and including an upper surface of the stacked insulating film. Forming a polysilicon layer on the upper surface of the semiconductor substrate, and selectively removing the polysilicon layer and the laminated insulating film in a cell region;
Forming an opening for a drain region and an opening for a source region, and using the polysilicon layer as a mask, a substrate surface in each of the openings for the drain region and the source region; Forming a drain region and a source region by implanting impurity ions from an oblique direction;
A step of embedding an insulating material in each of the openings for the drain region and the source region; and a step of forming a polysilicon layer serving as a gate electrode on the upper surface of the substrate.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor memory device according to the present invention will be specifically described with reference to the drawings. In the following, as an example of a semiconductor memory device, a virtual ground type EE
The PROM will be described.

[First Embodiment] FIG. 1 is a diagram showing a cell cross-sectional structure of an EEPROM of a first embodiment, and FIG. 2 is a circuit diagram showing an internal configuration of the EEPROM of the first embodiment. As shown in FIG. 2, the EEPROM of this embodiment has a virtual grounding type configuration, and a plurality of memory cells are arranged in a matrix.
The control gates in the memory cells in the same row are commonly connected to form word lines WL _{i + 1 to} WL _{i + m} , and the sources and drains of adjacent memory cells in the same column are commonly connected to each other to form a column line. Is composed.

As shown in FIG. 1, each memory cell constituting the EEPROM includes diffusion layers 2 and 3 serving as source / drain regions formed on the surface of the p-type silicon substrate 1 and a region between the diffusion layers 2 and 3. And a channel region 4 formed on the substrate. Above the channel region 4, an insulating film 8 having a laminated structure including a silicon oxide film 5, a silicon nitride film 6, and a silicon oxide film 7 is formed. A gate electrode 9 is formed on the upper surface of the insulating film 8 having the laminated structure. This gate electrode 9 is used as a word line. Further, an interlayer insulating film 10 is formed between the diffusion layers 2 and 3 and the gate electrode 9.

Silicon nitride film 6 in insulating film 8 having a laminated structure
The data is written by injecting hot electrons from the substrate into the substrate. While the silicon nitride film 6 and the diffusion layer 3 partially overlap in the vertical direction, an offset portion 11 is provided between the silicon nitride film 6 and the diffusion layer 2.

The source and the drain of each memory cell constituting the EEPROM of the first embodiment are reversed between when writing data and when reading data. That is, at the time of data writing, the diffusion layer 2 in FIG. 1 is a source and the diffusion layer 3 is a drain, whereas at the time of data reading, the diffusion layer 3 is a source and the diffusion layer 2 is a drain.

The threshold in the channel region formed below silicon nitride film 6 is set higher than the threshold in the channel region formed below offset portion 11.

Next, the principle of writing data in the memory cell of FIG. 1 will be described. At the time of data writing, as shown in FIG. 3, the diffusion layer 2 is set at 5V, the diffusion layer is set at 0V, and the gate electrode (word line) is set at 6V. Offset unit 11 in FIG.
Only acts on the lines of electric force from the side of the gate and weakly controls the gate, so that only a weak inversion layer is formed. On the other hand, a depletion layer is formed in the channel region 4 immediately below the silicon nitride film 6. The reason why the depletion layer is formed is that the channel region 4 is subjected to strong gate control, so that an inversion layer is to be formed. However, since the offset portion 11 is a weak inversion layer, supply of channel electrons from the source side is suppressed. This is because it can be suppressed.

Therefore, a high electric field region is formed near the edge of the depletion layer on the diffusion layer 2 side, and the offset portion 1 is formed from the source side.
The electrons that have entered the high electric field region through one weak inversion layer become hot electrons, and the hot electrons are drawn into the gate electrode 9 side and trapped in the silicon nitride film 6.

On the other hand, when reading data, as shown in FIG. 3, the diffusion layer 2 is set to 1.5V, the diffusion layer 3 is set to 0V, and the gate voltage is set to 3.3V. Thereby, the offset unit 1
Whether or not electrons are injected into the silicon nitride film 6 is determined based on whether a depletion layer extends from the diffusion layer 2 in contact with 1 to the offset portion 11 and a current flows from the diffusion layer 2 to the diffusion layer 3.

FIGS. 4 and 5 are manufacturing process diagrams of the first embodiment of the virtual ground type EEPROM. First, as shown in FIG. 4A, a field oxide film 21 having a thickness of about 600 nm is formed in a device isolation region on a p-type silicon substrate 1 by a known LOCOS method. The region surrounded by the field oxide film 21 becomes the cell region. Next, after exposing the surface of the p-type silicon substrate 1 on the cell region, the surface is coated with a thermal oxidation method.
A 15 nm thick silicon oxide film 22 is formed. Then, CVD
A polysilicon layer 23 having a thickness of about 50 nm is formed on the upper surface of the substrate by the method.

Next, as shown in FIG. 4B, a resist 24 is formed on the polysilicon layer 23 except for the cell region. Next, using the resist 24 as a mask, the polysilicon layer 23 in the cell region is removed by RIE. Next, channel ion implantation for threshold value control is performed in the cell region.

Next, after removing the resist 24, the silicon oxide film 22 is diluted using the polysilicon layer 23 as a mask.
Etching is removed by HF to expose the surface of the silicon substrate 1 on the cell region. Next, as shown in FIG.
After a silicon oxide film 5 having a thickness of about 5 nm is formed by a thermal oxidation method, a silicon nitride film 6 having a thickness of about 5 nm is formed. next,
A silicon oxide film 7 having a thickness of about 4 nm is formed on the surface of the silicon nitride film 6.
To form Next, a resist 25 is formed on the silicon oxide film 7 except for the peripheral circuit formation region.

Next, using the resist 25 as a mask, the silicon oxide film 5, the silicon nitride film 6, the silicon oxide film 7, and the polysilicon layer 23 are removed by RIE. Next, channel ion implantation for controlling the threshold value of the peripheral transistor is performed. Next, the silicon oxide film 22 is
To remove by etching.

Next, as shown in FIG. 5A, a silicon oxide film 26 having a thickness of about 15 nm is formed by a thermal oxidation method.
A polysilicon layer 9 having a thickness of about 100 nm is formed by a CVD method. On this polysilicon layer 9, the source /
A resist 27 having a drain region opened is formed.

Next, as shown in FIG. 5B, using the resist 27 as a mask, the polysilicon layer 9 and the silicon oxide film 7 are formed.
Then, the silicon nitride film 6 is etched away by RIE. Next, after removing the resist 27, arsenic is ion-implanted from an oblique direction (for example, a direction of 45 degrees) using the polysilicon layer 9 as a mask. Thereby, the polysilicon layer 9 is formed.
Diffusion layers 2 and 3 having a self-aligned structure and offset portion 1
1 is formed.

Next, as shown in FIG. 5C, a silicon oxide film 10 is formed by a CVD method. More specifically,
For example, the polysilicon layer 9 is etched back by RIE.
The silicon oxide film 10 is buried in the space of FIG. next,
After a polysilicon layer 28 having a thickness of about 50 nm is formed by the CVD method, a WSi film 29 having a thickness of about 150 nm is formed on the upper surface thereof by the CVD method.
To form

Next, as shown in FIG. 5D, after a transistor resist pattern 30 is formed in the cell region,
Using the resist 30 as a mask, the WSi film 29, the polysilicon layer 28 and the polysilicon layer 9 are etched away by RIE. Similarly, after forming a resist pattern in the peripheral region of the transistor and the wiring region, RIE is performed using the resist 30 as a mask, and the WSi film 29 and the polysilicon layer 28 are removed by etching.

Next, in the same manner as in a normal LSI manufacturing method, after ion implantation for forming source / drain diffusion layers of peripheral transistors, a BPSG of about 400 nm is formed as an interlayer film.
After depositing the film, heat treatment is performed, for example, at 850 ° C. next,
After forming the contact hole, a barrier metal layer is formed on the inner wall of the contact hole, and a metal material (eg,
Al-Si-Cu) is embedded and patterned. Next, after depositing a passivation film, pads are formed, and finally an EEPROM is obtained.

As described above, in the present embodiment, since the insulating film 8 having the laminated structure is formed and the hot electrons are injected into the silicon nitride film 6 as a part thereof, the floating gate is unnecessary as in the conventional case. . Therefore, the voltage applied to the gate electrode is applied to the silicon nitride film almost as it is, and the coupling ratio can be made 1, so that the program voltage can be reduced.

Further, since the injection from the source side is performed instead of the injection of hot electrons from the drain side as in the conventional case, the program current is small, and the current consumption is reduced in the case of a virtual ground type structure. Can be suppressed, so that the capacity of the memory can be increased.

Further, since hot electrons are injected from the source side, electrons can be trapped on the entire surface of the silicon nitride film, and the threshold voltage does not change.
The charge retention characteristics are improved.

[Second Embodiment] In a second embodiment, the manufacturing process shown in FIG.
It forms the EEPROM.

6 to 8 are manufacturing process diagrams of a second embodiment of the virtual ground type EEPROM. First, as shown in FIG. 6A, a field oxide film 21 having a thickness of about 600 nm is formed in a device isolation region on a p-type silicon substrate by a known LOCOS method. A cell region is formed around field oxide film 21. Next, after exposing the surface of the Si substrate 1 on the cell region, a silicon oxide film 22 having a thickness of about 15 nm is formed on the surface by a thermal oxidation method.

Next, as shown in FIG. 6B, after a resist 24 is formed on the silicon oxide film 22 except for the cell region, channel ions for controlling the threshold value are implanted into the cell region. Next, using the resist 24 as a mask, the silicon oxide film is removed by etching with dilute HF to expose the surface of the silicon substrate on the cell region.

Next, as shown in FIG. 6C, after removing the resist 24, a silicon oxide film 5 having a thickness of about 5 nm is formed by a thermal oxidation method. At this time, in the peripheral circuit area,
The silicon oxide film 5 is re-oxidized. Next, after forming a silicon nitride film 6 having a thickness of about 5 nm on the silicon oxide film 5,
Further, about 4 μm is formed on the upper surface of the silicon nitride film 6 by thermal oxidation.
A silicon oxide film 7 having a thickness of nm is formed.

Next, the silicon oxide film 5, the silicon nitride film 6, and the silicon oxide film 7 are removed by etching using a resist having an opening in the peripheral circuit region as a mask. Next, after removing and removing the resist, a silicon oxide film 40 having a thickness of about 12 nm is formed by a thermal oxidation method. Next, channel ion implantation is performed to control threshold values of peripheral transistors for the high-voltage circuit and the low-voltage circuit.

Next, as shown in FIG. 7A, the silicon oxide film 40 is removed by etching using a resist having an opening in the peripheral low voltage circuit region as a mask. Next, after removing and removing the resist, a silicon oxide film 41 for a low voltage circuit having a thickness of about 60 Å is formed by a thermal oxidation method. At this time, the silicon oxide film 40 for the high voltage circuit is reoxidized to a thickness of about 150 Å, but the silicon oxide film 7 on the silicon nitride film 6 in the cell region hardly regrows.

Next, as shown in FIG. 7B, a polysilicon layer 9 having a thickness of about 100 nm is formed by the CVD method. Next, a resist 27 having an opening in the source / drain region in the cell region is formed on the upper surface thereof, and the polysilicon layer 9, the silicon oxide film 7, and the silicon nitride film 6 are formed by RIE using the resist 27 as a mask. Remove by etching.

Next, as shown in FIG. 7C, after removing the resist 27, a resist 42 having an opening in the drain region in the cell region is formed on the upper surface of the polysilicon layer 9. Next, using the polysilicon layer 9 as a mask, 1E15 arsenic is ion-implanted at a voltage of 50 keV. As a result, the drain diffusion layer 3 having a self-aligned structure with respect to the polysilicon layer 9 is formed.

Next, as shown in FIG. 7D, a silicon oxide film having a thickness of about 70 nm is formed by the CVD method.
Etchback is performed by RIE to form a sidewall oxide film 43 on the sidewall of the polysilicon layer. Next, after forming a resist 44 having an opening in the source region in the cell region, the polysilicon layer 9 and the side wall oxide film 43 are used as a mask at a voltage of 50 keV to form a resist 1.
Arsenic of E15 is ion-implanted. Thereby, the side wall oxide film 43 has a self-aligned structure with respect to the polysilicon layer 9.
The source diffusion layer 2 having the offset region 11 corresponding to the space width is formed.

Next, as shown in FIG. 8A, a silicon oxide film 10 having a thickness of about 400 nm is formed by the CVD method. That is, by etching back the silicon oxide film 10, the silicon oxide film 10 is buried in the polysilicon openings on the source diffusion layer 2 and the drain diffusion layer 3, and the upper surface of the polysilicon layer 9 is exposed. Next, CVD
A polysilicon layer 28 and a WSi layer 29 are each formed to a thickness of about 100 nm by the method.

Next, as shown in FIG. 8B, after forming a resist pattern 30 for the word line in the cell region, the WSi layer 29 is formed by RIE using the resist 30 as a mask.
The polysilicon layer 28, the polysilicon layer 9, the silicon oxide film 7, and the silicon nitride film 6 are respectively etched.

Next, as shown in FIG. 8B, after forming a resist pattern in a transistor in the peripheral region and a wiring region, the WSi layer 29 is formed using this resist pattern as a mask.
The polysilicon layer 28 and the polysilicon layer 9 are etched.

Next, similarly to the first embodiment, the formation of the source / drain diffusion layers of the peripheral transistor, the formation of the BPSG film as the interlayer film, the formation of the wiring region, the formation of the passivation film, and the formation of the pad are performed. And finally an EEPROM is obtained.

FIG. 9 is a diagram showing a cross-sectional structure of a cell region formed by the steps of FIGS. As illustrated, the second embodiment has a structure in which source terminals and drain terminals of adjacent transistors face each other. Note that also in the second embodiment, the source and the drain are reversed between when writing data and when reading data.

[0059]

As described in detail above, according to the present invention, since the silicon nitride film is used as the charge storage layer,
A voltage substantially equal to the voltage applied to the control gate can be applied to the silicon nitride film, and the program voltage applied to the control gate at the time of writing data can be set low.

Further, at the time of data writing, electrons are injected into the silicon nitride film from the source side, so that the program current can be reduced, and the current consumption can be suppressed even in the case of the virtual ground type configuration.

Further, since electrons are injected into the silicon nitride film from the source side, electrons can be trapped evenly over the entire surface of the silicon nitride film. The characteristics are improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a cell cross-sectional structure of an EEPROM according to a first embodiment.

FIG. 2 is a circuit diagram showing an internal configuration of an EEPROM according to the first embodiment.

FIG. 3 is a diagram showing voltages applied during data erasing / data writing / data reading.

FIG. 4 is a manufacturing process diagram of the first embodiment of the virtual ground type EEPROM;

FIG. 5 is a manufacturing process diagram following FIG. 4;

FIG. 6 is a manufacturing process diagram of the first embodiment of the virtual ground type EEPROM;

FIG. 7 is a manufacturing process diagram following FIG. 6;

FIG. 8 is a manufacturing process diagram following FIG. 7;

FIG. 9 is a view showing a cross-sectional structure of a cell region formed by the steps of FIGS. 6 to 8;

FIG. 10 is a diagram showing a cell cross-sectional structure of a conventional M (O) NOS type EEPROM.

FIG. 11 is a schematic sectional view of a virtual grounding type EEPROM.

[Explanation of symbols]

 Reference Signs List 1 p-type silicon substrate 2, 3 diffusion layer 4 channel region 5 silicon oxide film 6 silicon nitride film 7 silicon oxide film 8 laminated insulating film 9 gate electrode 10 interlayer insulating film 11 offset portion 21 field oxide film 22 silicon oxide film 23 polysilicon Layers 24, 25, 27 Resist 28 Polysilicon layer 29 WSi film

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F001 AA14 AC01 AD12 AD62 AG10 AG12 AG21 AG29 5F083 EP17 EP18 GA05 NA02 PR03 PR05 PR12 PR21 PR36

Claims (9)

[Claims] A first conductive type semiconductor substrate; a plurality of second conductive type diffusion layer regions formed in parallel on the semiconductor substrate; and a pair of adjacent diffusion layer regions, one end of which is one end. A first channel region provided in contact with the diffusion layer region, a second channel region provided with one end in contact with the first channel region and the other end in contact with the other diffusion layer region, A charge storage layer having a stacked structure formed on a channel region; and a gate formed on the second channel region and the charge storage layer via an insulating film, substantially in parallel with a direction in which the diffusion layer regions are arranged. And a threshold value of the second channel region below the gate electrode is higher than a threshold value of the first channel region below the gate electrode. . 2. A write operation, wherein a first write voltage and a second write voltage are applied to the diffusion layer region in contact with the first channel region.
A reference voltage is applied to the diffusion layer region that is in contact with the channel region, and a second write voltage is applied to the gate electrode.
2. The semiconductor memory device according to claim 1, wherein electrons are injected into the charge storage layer from a side of the channel region closer to the second channel region. 3. In reading, a reference voltage is applied to the diffusion layer region in contact with the first channel region, a first read voltage is applied to the diffusion layer region in contact with the second channel region, and a second voltage is applied to the gate electrode. And the second read voltage is applied.
And determining whether or not electrons are injected into the charge storage layer based on whether or not a current flows from the diffusion layer region in contact with the channel region to the first diffusion layer region. 3. The semiconductor memory device according to 2. 4. The semiconductor device according to claim 1, wherein the insulating film on the second channel region is formed to be thicker than the charge storage layer and the insulating film formed on the charge storage layer. The semiconductor memory device according to claim 1. 5. The semiconductor memory device according to claim 1, wherein said charge storage layer is a film made of a silicon nitride film. 6. The semiconductor memory device according to claim 1, wherein said diffusion layer region has one end in contact with said first channel region and the other end in contact with a second channel region. 7. The semiconductor device according to claim 1, wherein said diffusion layer region has both ends contacting said first channel region and both ends contacting said second channel region are alternately arranged. A semiconductor memory device according to claim 1. 8. A step of forming an element isolation region on a semiconductor substrate; and a step of implanting impurity ions for controlling a threshold into a semiconductor substrate in a cell region formed around the element isolation region. Forming a stacked insulating film composed of a silicon oxide film, a silicon nitride film for charge storage, and a silicon oxide film on a semiconductor substrate in a cell region; Forming a silicon layer; selectively removing the polysilicon layer and the laminated insulating film in a cell region to form an opening for a drain region and an opening for a source region; Implanting impurity ions into the opening for the drain region using the resist formed on the upper surface as a mask to form a drain region; and forming the opening for the drain region and the opening for the source region. Forming a sidewall insulating film on the side wall portion of the substrate, and implanting impurity ions into the opening for the source region using the resist formed on the upper surface of the substrate and the sidewall insulating film as a mask to form a source region Embedding an insulating material in each of the openings for the drain region and the source region; and forming a polysilicon layer serving as a gate electrode on the upper surface of the substrate. Production method. 9. A step of forming an element isolation region on a semiconductor substrate; and a step of implanting impurity ions for controlling a threshold value on a semiconductor substrate in a cell region formed around the element isolation region. Forming a stacked insulating film composed of a silicon oxide film, a silicon nitride film for charge storage, and a silicon oxide film on a semiconductor substrate in a cell region; Forming a silicon layer; selectively removing the polysilicon layer and the laminated insulating film in a cell region to form an opening for a drain region and an opening for a source region; Using the polysilicon layer as a mask, impurity ions are implanted into the substrate surface in each of the openings for the drain region and the source region from an oblique direction with respect to the substrate surface to thereby form a drain region and a source region. Forming an insulating material in each of the openings for the drain region and the source region; and forming a polysilicon layer serving as a gate electrode on the upper surface of the substrate. A method for manufacturing a semiconductor storage device.