JP3649751B2 - Semiconductor memory device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a semiconductor memory device, and more particularly to power saving thereof.
[0002]
[Prior art]
Today, a flash memory having a virtual ground array structure that does not require contacts in the cell array and can reduce the size of the cells is known. The virtual ground array structure means that when memory cells are arranged in a matrix, a source region of a certain memory cell and a drain region of a memory cell arranged in a column adjacent to the memory cell are shared.
[0003]
FIG. 13B shows an equivalent circuit 61 of a flash memory having a virtual ground array structure. As shown in the figure, the source region of the memory cell C22 and the drain region of the memory cell C21 arranged in the adjacent column are shared, and these shared regions constitute the bit line B2.
[0004]
FIG. 13A shows the structure of the nonvolatile memory 50 constituting each memory cell. The non-volatile memory 50 has n in the p-type silicon well 2 provided in the substrate. ⁺ Type drain 3 and n ⁺ A mold source 4 is provided. Between the drain 3 and the source 4 is a channel region 16. A tunnel oxide film 8 is provided on the channel region 16. Further, a floating gate 12 made of polysilicon, an interlayer insulating film 13, and a control gate electrode 14 are provided in this order on the tunnel oxide film 8.
[0005]
[Principle of writing, erasing and reading]
Information writing and erasing to the nonvolatile memory 50 will be described. When writing information “1”, a high voltage is applied to the control gate electrode 14 and the drain 3, and a ground potential is applied to the source 4 and the well 2. As a result, hot electrons generated near the drain 3 jump over the potential barrier of the tunnel oxide film 8 and flow into the floating gate 12.
[0006]
The threshold voltage of the control gate voltage for forming a channel in the channel region 16 is increased by the electrons flowing in this way. This state is a state in which information “1” is written in the flash nonvolatile memory 50 (hereinafter referred to as a write state).
[0007]
On the other hand, when information “0” is stored (erased) in the non-volatile memory 50, electrons that have flowed into the floating gate 12 are returned to the source 4. Applies a high voltage in the opposite direction. As a result, an electric field in a direction opposite to that at the time of writing is generated, and electrons are pulled back to the source 4 by FN (Fowler-Nordheim) tunneling.
[0008]
As the electrons are pulled back in this manner, the threshold value of the control gate voltage for forming a channel in the channel region 16 is lowered. This state is a state in which information “0” is stored in the nonvolatile memory 50 (hereinafter referred to as a non-write state).
[0009]
Next, an information reading operation in the nonvolatile memory 50 will be described. First, the sense voltage Vs is applied to the control gate electrode 14. The sense voltage Vs is a voltage intermediate between the threshold voltage in the writing state and the threshold voltage in the non-writing state.
[0010]
If the nonvolatile memory 50 is in a write state, the sense voltage Vs is lower than the threshold voltage of the nonvolatile memory 50, so that no channel is formed in the channel region 16. Therefore, even if the potential of the drain 3 is made higher than the potential of the source 4, no current flows between the drain 3 and the source 4.
[0011]
On the other hand, if the nonvolatile memory 50 is in a non-write state, the sense voltage Vs is higher than the threshold voltage of the nonvolatile memory 50, so that a channel is formed in the channel region 16. Therefore, a current flows between the drain 3 and the source 4 by making the drain 3 potential higher than the source 4 potential.
[0012]
As described above, in the non-volatile memory 50, at the time of reading, the control gate electrode 14 is applied with the sense voltage Vs, which is a voltage between the threshold voltages of the writing state and the non-writing state, so that the channel region 16 detects whether a channel is formed, and determines whether it is in a writing state or a non-writing state.
[0013]
[Operation when combined in matrix]
By the way, when the non-volatile memory 50 is arranged in a virtual ground array structure, there is a risk of writing or reading to a memory cell other than a memory cell desired to be written or read (hereinafter referred to as a selected cell). . Therefore, in the equivalent circuit 61 shown in FIG. 13B, the selected cell can be reliably selected as described below. (Note that cells other than the selected cell are hereinafter referred to as non-selected cells).
[0014]
First, writing will be described. A high voltage is applied to the word line W2 and the bit line B3, the bit lines B1 and B4 are opened, and the bit line B2, the word lines W1 and W3, and the well 2 are set to the ground potential. Looking at the selected cell C22, a high voltage is applied to the control gate electrode 14 and the drain 3, and a ground potential is applied to the source 4 and the well 2. As a result, hot electrons are generated in the vicinity of the drain 3 and a write state is established.
[0015]
As for the non-selected cells C21 and C23, since the source or drain is open, hot electrons are not generated and a write state is not obtained. For the other non-selected cells C11 to C13 and C31 to C33, the control gate electrode 14 is at the ground potential, so that it does not enter the write state. In this way, only the selected cell can be written.
[0016]
Reading is performed as follows. When the cell C22 is selected, the sense voltage Vs and the bit lines B1 and B4 are opened on the word line W2, the word lines W1 and W3 and the well 2 are set to the ground potential, and a potential difference is generated between the bit line B3 and the bit line B2. And a sense amplifier is connected to the bit line B2.
[0017]
If the cell C22 is in the write state, no channel is formed in the channel region 16 as described above, and no current flows between the drain 3 and the source 4. On the other hand, in the non-write state, a channel is formed in the channel region 16 and a current flows between the drain 3 and the source 4. This may be read by a sense amplifier connected to the bit line B2.
[0018]
As for the non-selected cells C21 and C23, since the source or drain is open, no current flows between the drain 3 and the source 4 even in the non-written state. For the other non-selected cells C11 to C13 and C31 to C33, the channel is not formed in the channel region 16 because the control gate electrode 14 is at the ground potential. Therefore, no current flows between the drain 3 and the source 4. In this way, only information on the selected cell can be read.
[0019]
In erasing, the word lines W1 to W4 are set to the ground potential, and a high voltage in the direction opposite to that at the time of writing is applied to the bit lines B1 to B4. As a result, electrons are pulled back to the source 4 and the memory cells are erased collectively.
[0020]
Thus, by configuring the nonvolatile memory 50 with the virtual ground array structure, no contact is required, and the cell area can be reduced.
[0021]
[Problems to be solved by the invention]
However, the above flash memory has the following problems. At the time of writing, since the hot electron injection method is used, the tunnel oxide film 8 is deteriorated. For this reason, there exists a possibility that the reliability as an element may fall. Further, in the hot electron injection method, only a very small amount (about 1%) of electrons flowing between the source and the drain flows into the floating gate 12, so that the injection efficiency is poor. For this reason, power consumption increases.
[0022]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device that solves the above-described problems and has low power consumption and improved reliability.
[0023]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a semiconductor memory device comprising: A) single memory cells having a1) to a6) arranged in a matrix; a1) a second conductive provided in a first conductive type region of a semiconductor substrate. A first region of the mold, which is a first region a2 formed by using phosphorus as an impurity a2) a second conductivity type second region provided so as to form an electric circuit formable region between the first region and the first region A second region formed by using arsenic as an impurity, a3) a first insulating film provided above the electric circuit forming region, a4) an electric circuit can be formed through the first insulating film A floating electrode provided above the region, a5) a second insulating film provided above the floating electrode, a6) a control electrode provided above the floating electrode via the second insulating film B) Control electrodes of single memory cells arranged in the same row are controlled by being electrically connected. C) the first regions of the single memory cells arranged in the same column are connected to each other in the semiconductor substrate to form a first impurity region line; D) The second regions of the single memory cells arranged in the same column are connected to each other in the semiconductor substrate to form a second impurity region line, and E) arranged in adjacent columns. A semiconductor memory device sharing the first impurity region line and the second impurity region line of a single memory cell as an impurity region line, wherein the first region has FN tunneling in a selected memory cell. When the electrons injected into the floating gate are pulled back to the source And FN tunneling in the memory cell adjacent to the selected memory cell. The electronic withdrawal is not performed, The first region has a low concentration region whose impurity concentration is lower than that of the second region, and one end of the first region extends to the first conductivity type region below the floating electrode. Is formed so as to overlap to a predetermined position at the lower end of the second region, and is formed to be larger than the second region in a direction perpendicular to the plane of the semiconductor substrate.
[0024]
[Action]
2. A semiconductor memory device according to claim 1. Is A first region formed using phosphorus as an impurity and a second region formed using arsenic as an impurity, and the first region includes FN tunneling in a selected memory cell. When the electrons injected into the floating gate are pulled back to the source And FN tunneling in the memory cell adjacent to the selected memory cell. The electronic withdrawal is not performed, The first region has a low concentration region whose impurity concentration is lower than that of the second region, and one end of the first region extends to the first conductivity type region below the floating electrode. Is formed so as to overlap to a predetermined position at the lower end of the second region, and is formed to be larger than the second region in a direction perpendicular to the plane of the semiconductor substrate. Therefore, a depletion layer having a large maximum depletion layer width is formed between the floating electrode on the first region side that does not have the high concentration region and the first region. This When pulling back the electrons In addition, the electric field between the floating electrode and the first region is weakened, and electrons are not extracted from the first region side. On the other hand, since a depletion layer having a thin maximum depletion layer width is formed between the floating electrode on the second region side having the high concentration region and the second region, electrons are extracted from the high concentration region of the second region. Can do.
[0025]
【Example】
[Structure of flash memory 1]
An embodiment of the present invention will be described with reference to the drawings. First, FIGS. 1 and 2 show a flash memory 1 according to an embodiment of the present invention. 2A is a plan view of the flash memory 1, FIG. 1 shows a cross section taken along the line AA in FIG. 2A, and FIG. 2B shows a cross section taken along the line BB in FIG. 2A.
[0026]
As shown in FIG. 1, in the flash memory 1, a non-volatile memory 70 constituting a single memory cell is arranged in a virtual ground array structure. The nonvolatile memory 70 includes an n + -type drain 3 that is a second region and an n-type that is a first region in a p-type silicon well 2 provided in the substrate. ^- A mold source 4 is provided. Between the drain 3 and the source 4, a channel region 16 that is a first electric path forming region is provided.
[0027]
A tunnel oxide film 8 that is a first insulating film is provided above the channel region 16, and a floating gate 12 that is a floating electrode is further provided above the tunnel oxide film 8. A control gate electrode 14 as a control electrode is provided above the floating gate 12 via an interlayer insulating film 13 as a second insulating film.
[0028]
As shown in FIG. 2A, the sources 4 of the single memory cells arranged in the same column are electrically connected to form a source line that is a first region line. Similarly, the drain 3 of each single memory cell arranged in the same column is electrically connected to form a drain line as a second region line.
[0029]
Furthermore, a drain line of a single memory cell and a source line of a single memory cell arranged in a column adjacent to the single memory cell are formed in common as a bit line which is a region line. For example, in FIG. 1, the bit line B <b> 3 forms the source 4 of the nonvolatile memory 51 and the drain 3 of the nonvolatile memory 70.
[0030]
Further, the control gate electrode 14 of each single memory cell arranged in the same row is electrically connected to another single memory cell arranged in the same row, so that a word line which is a control electrode line is formed. Forming. For example, as shown in FIGS. 1 and 2A, the control gate electrode 14 of the single memory cell 69 is electrically connected to the other single memory cells 70 and 71 arranged in the same column, so that the word Line W2 is formed. The word lines W1, W2, and W3 are provided for each row as shown in FIG. 2A.
[0031]
As shown in FIG. 2B, single memory cells arranged in the same column are separated by n-type regions 88a, 88b, 88c.
[0032]
In the present embodiment, all the drains 3 are formed in the high concentration region.
[0033]
[Operation of flash memory 1]
Next, a method of using the flash memory 1 will be described with reference to FIGS. 3A and 3B. FIG. 3A shows an equivalent circuit 81 of the flash memory 1. FIG. 3B shows an example of voltages applied at the time of erasing, writing and reading when the cell C22 is a selected cell.
[0034]
In the conventional example, a state in which electrons are injected into the floating gate 12 is a write state, and a state in which the injected electrons are pulled back to the source 4 is a non-write state. On the other hand, in this embodiment, the state where electrons are injected into the floating gate 12 is the erased state (non-written state), and the state where the injected electrons are pulled back to the source 4 is the written state.
[0035]
When writing to the cell C23, first, all the single memory cells connected to the word line to which the single memory cell to be written is connected are brought into an erased state. Specifically, as shown in FIG. 3B, 18V is applied to the word line W2, and 0V is applied to the others.
[0036]
The cell C23 in this state is shown in FIG. 4A. Since 18V is applied to the word line W2, a voltage corresponding to the coupling ratio between the well 2, the floating gate 12 and the control gate electrode 14 (about 12V in this case) is applied to the floating gate 12 of the cell C23. The Thereby, each channel region 16 of the cell C23 is turned on. Here, since 0V is applied to the bit lines B3 and B4, 0V is transferred to the channel region 16 of the selected cell C23. As a result, electrons are injected into the floating gate 12 by FN tunneling, and the selected cell C23 enters an erased state. The same applies to the other single memory cells C21, C22, C24.
[0037]
Next, a case where data is written in the cell C23 will be described. As shown in FIG. 3B, -7V is applied to the word line W2, 5V is applied to the bit line B4, and 0V is applied to the others.
[0038]
A cell C23 in this state is shown in FIGS. 4B and 4C. 4C shows a partial detail view of FIG. 4B. Referring to FIG. 4C, since −7V is applied to the word line W2, the voltage corresponding to the coupling ratio among the well 2, the floating gate 12 and the control gate electrode 14 is applied to the floating gate 12 of the cell C23. In this case, about -5V) is applied. Further, 5 V is applied to the bit line B4. As a result, the depletion layer at the interface between the drain 3 and the floating gate 12 is expanded to the maximum depletion layer width. However, even if the depletion layer expands to the maximum depletion layer width, the potential difference between the floating gate 12 and the drain 3 is 10 V. Therefore, electrons injected into the floating gate 12 are drained from the drain 3 of the cell C23 by FN tunneling. Then, the selected cell C23 enters a write state.
[0039]
On the other hand, the cell C24 which is a non-selected cell is in the following state. Since -7V is applied to the word line W2, approximately -5V is also applied to the floating gate 12 of the cell C24. Further, 5 V is applied to the bit line B4. Thereby, the depletion layer 23 at the interface between the source 4 and the floating gate 12 is expanded to the maximum depletion layer width. Here, the source 4 of the cell C24 is doped only with a lower concentration of impurities than the drain 3 of the cell C23. Therefore, the maximum depletion layer width of the depletion layer 23 formed in the source 4 of the cell C24 is larger than the maximum depletion layer width of the depletion layer formed in the drain 3 of the cell C23. Therefore, the thickness of the tunnel oxide film 8 becomes substantially equal to that of the tunnel oxide film 8, the electric field is weakened, and FN tunneling does not occur. That is, the cell C24, which is a non-selected cell, will not be erroneously written.
[0040]
On the other hand, the other unselected cells C21 and C22 are in the following state. Returning to FIG. 3A, since −7 V is applied to the word line W <b> 2, approximately −5 V is applied to the floating gate 12. However, since 0 V is applied to the bit lines B1 and B2, a voltage that causes FN tunneling between the floating gate 12 and the source 4 and between the floating gate 12 and the drain 3 is not applied. Therefore, the non-selected cells C21 and C22 are not in the write state.
[0041]
Further, the other non-selected cells C11 to C14 and C31 to C34 are not in the write state because 0 V is applied to the word lines W1 and W3. Thus, even when combined in a matrix form, by making the impurity concentration of the drain 3 of each memory cell higher than the impurity concentration of the source 4, a source line to which a certain memory cell belongs and a column adjacent to the memory cell are arranged. Even in a flash memory in which one bit line is formed by electrically connecting to a drain line to which a memory cell arranged in the memory cell 1 can be written, only the selected cell can be written using the FN current.
[0042]
Next, reading will be described with reference to FIG. 3A. When the cell C23 is a selected cell, 5 V is applied as a sense voltage to the word line W2, 1 V is applied to the bit line B4, and a sense amplifier is connected. Also, the bit lines B1, B2, and B5 are opened, and 0 V is applied to the others.
[0043]
Since the sense voltage (5 V) is applied to the word line W2, the channel region 16 of the selected cell C23 is turned on if the cell C23 is in a write state (a state where electrons are extracted from the floating gate 12). Here, since 1 V is applied to the drain 3 (bit line B4) of the cell C23 and 0 V is applied to the source 4 (bit line B3), the drain 3 (bit line B4) and the source 4 (bit line B3) are connected. Current can be read by the sense amplifier connected to the bit line B4.
[0044]
On the other hand, if the cell C23 is in a non-write state (a state where electrons are injected into the floating gate 12), the channel region 16 of the selected cell C23 is turned off. Therefore, no current flows between the drain 3 (bit line B4) and the source 4 (bit line B3).
[0045]
For the unselected cells C21, C22, and C24, since the bit lines B1, B2, and B5 are in an open state, no current flows by mistake. For other non-selected cells C11 to C13 and C31 to C33, the sense voltage is not applied to the word lines W1 and W3, so that the channel region 16 is in an off state. Therefore, no current flows by mistake. In this way, only information on the selected cell can be read.
[0046]
As described above, in the flash memory 1, the drain 3 of each memory cell has a high concentration region whose impurity concentration is higher than that of the source 4, and the high concentration region extends to the semiconductor substrate region below the floating gate 12. It is formed as follows. Therefore, a depletion layer having a large maximum depletion layer width is formed between the floating gate 12 on the source 4 side and the source 4. On the other hand, a depletion layer having a thin maximum depletion layer width is formed between the floating gate 12 on the drain 3 side and the drain 3. The thick depletion layer weakens the electric field between the floating gate 12 and the source 4 at the time of writing, and can extract electrons only from the drain 3.
[0047]
Thereby, it is possible to provide a flash memory having a virtual ground array structure in which information can be written by FN tunneling. That is, it is possible to provide a semiconductor memory device that does not require a contact and reduces the cell area while reducing power consumption and improving reliability.
[0048]
[Method of Manufacturing Flash Memory 1]
Next, a manufacturing method of the flash memory 1 will be described with reference to FIGS. A thermal oxide film 80 (pad oxide) is formed on the surface of the p-type silicon well 2 of the semiconductor substrate, a silicon nitride film is formed thereon using a chemical vapor deposition (CVD) method, and then a photoresist is used. The silicon nitride films 82a to 82d are formed by selective etching. This state is shown in FIG. 5A.
[0049]
Next, as shown in FIG. 5B, portions of the semiconductor substrate surface not covered with the silicon nitride films 82a to 82d are covered with resists 84a to 84d. In this state, arsenic (As) is ion-implanted into the entire surface of the semiconductor substrate. As a result, arsenic ions are implanted into the semiconductor substrate region 101 not covered with the silicon nitride films 82a to 82d and the resists 84a to 84d.
[0050]
Next, after removing the resists 84a to 84d, as shown in FIG. 5C, portions other than the region 101 into which arsenic ions have been implanted are covered with the resists 86a to 86d. In this state, phosphorus (P) ions are implanted into the entire surface of the semiconductor substrate. Thereby, phosphorus ions are implanted into the semiconductor substrate region 102 not covered with the silicon nitride films 82a to 82d and the resists 84a to 84d.
[0051]
Next, after heat-treating the semiconductor substrate, the silicon nitride films 82a to 82d and the thermal oxide film 80 (pad oxide) are removed. As a result of this heat treatment, oxidation proceeds only to the portions not covered with the silicon nitride films 82a to 82d, and the element isolation region 5 is formed as shown in FIG. 6A. At the same time, this heat treatment causes n-type silicon well 2 below element isolation region 5 to n ⁺ Type drain 3 and n ^- A mold source 4 is formed.
[0052]
6B is a plan view, and FIG. 6A is a CC cross section of FIG. 6B. In the figure, the width α indicates the width of the element isolation region 5, the width β indicates the width of the drain 3, and the width γ indicates the width of the source 4.
[0053]
In this embodiment, the high concentration region (n ⁺ Arsenic (As) is used as an impurity for forming the layer), and the impurity concentration is not so high (n ^- Phosphorus (P) is employed as an impurity for forming the layer. By adopting such a configuration, since arsenic has a lower diffusion coefficient than phosphorus, a high concentration region (n ⁺ It is possible to prevent the impurity concentration from being lowered due to diffusion of a portion to be formed as a layer.
[0054]
Note that the region where the impurity concentration is not so high (n ^- As an impurity forming the layer, arsenic may be employed instead of phosphorus. In this case, the high concentration region (n ⁺ In order to prevent a portion desired to be formed as a layer) from being diffused to lower the impurity concentration, the dose amount or the like may be adjusted.
[0055]
Next, a thin tunnel oxide film 8 is formed on the substrate surface by dilution oxidation. A polysilicon layer is formed thereon using a CVD method, and etching using a photoresist is performed to form a floating gate 12 as shown in FIG. 7A.
[0056]
Next, an interlayer insulating film 13 composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film is formed in order on the entire surface of the substrate. In this embodiment, the lowermost silicon oxide film is formed by dilution oxidation, the silicon nitride film is formed by low pressure CVD, and the uppermost silicon oxide film is formed by wet oxidation.
[0057]
Next, a polysilicon layer is formed on the interlayer insulating film 13 using the CVD method, and etching using a photoresist is performed to form the interlayer insulating film 13 and the control gate electrode 14 as shown in FIG. 7B. . At that time, the floating gate 12 on the element isolation region is removed. As a result, the width of the floating gate 12 is formed to the same width as the control gate electrode 14.
[0058]
From this state, by ion-implanting n-type impurities, the cells arranged in the same column are separated for each cell as shown in FIGS. 2A and 2B.
[0059]
Thus, in this embodiment, a bit line is formed under the element isolation region 5.
[0060]
[Other Embodiments (Flash Memory 80)]
FIG. 8 shows a flash memory 80 which is another embodiment. In the flash memory 80, a nonvolatile memory 81 is arranged in a virtual ground array structure.
[0061]
The structure of the non-volatile memory 81 is n ^- Region is n ⁺ The drain 3 is partly formed so as to cover the region. ^- The structure is the same as that of the nonvolatile memory 70 except for the area.
[0062]
That is, also in the nonvolatile memory 81, the drain 3 has a high concentration region having an impurity concentration higher than that of the source 4, and the high concentration region is formed to extend to the semiconductor substrate region below the floating gate 12. .
[0063]
In the flash memory 80, n is part of the drain 3. ^- Has an area. Therefore, the drain 3 side can have a high breakdown voltage structure. As a result, leakage current due to band-to-band tunneling can be reduced.
[0064]
The method of using the flash memory 80 is the same as that of the flash memory 1.
[0065]
For the manufacturing method of the flash memory 80, n ^- Region is n ⁺ The other points are the same except that they are formed so as to cover the region. n ^- Region is n ⁺ In order to cover the region, a mask pattern for forming the resists 84a to 84d and the resists 86a to 86d is formed in a desired n. ^- Region and n ⁺ What is necessary is just to change so that it may become an area | region.
[0066]
[Other Embodiments (Flash Memory 91)]
9A and 9B show a flash memory 91 which is another embodiment. In the flash memory 91, the nonvolatile memory 170 is arranged in a virtual ground array structure.
[0067]
The structure of the non-volatile memory 81 is n below the element isolation region 5. ^- Region and n ⁺ It differs from the nonvolatile memory 70 in that no region is formed. The other parts are almost the same as those of the nonvolatile memory 70, and thus description thereof is omitted.
[0068]
The method of using the flash memory 91 is the same as that of the flash memory 1.
[0069]
Next, a method for manufacturing the flash memory 91 will be described with reference to FIGS. First, as shown in FIG. 10A (plan view), a field oxide layer 123 is formed by a LOCOS method, and element isolation is performed. 10B is a cross-sectional view of the element isolation region taken along the line YY of FIG. 10A. The element isolation region is formed so that the field oxide layer 123 protrudes from the substrate surface. On the other hand, FIG. 10C is an XX cross section of FIG. 10A and a cross sectional view of an element formation region.
[0070]
Next, a thin tunnel oxide film 8 is formed on the entire surface by dilution oxidation, a polysilicon layer is formed thereon using a CVD method, and etching using a photoresist is performed, as shown in FIGS. 11A and 11B. Thus, the floating gate 12 is formed. FIG. 11B is a cross-sectional view taken along the line XX of FIG.
Next, as shown in FIG. 12A, an interlayer insulating film 13 composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film is formed in order on the entire surface of the substrate. In this embodiment, the lowermost silicon oxide film is formed by dilution oxidation, the silicon nitride film is formed by low pressure CVD, and the uppermost silicon oxide film is formed by wet oxidation.
[0071]
From this state, in the same manner as in FIGS. 5B and 5C, impurities are selectively ion-implanted using a resist, and then heat treatment is performed. ⁺ Type drain 3 and n ^- A mold source 4 is formed.
[0072]
Next, after a polysilicon layer is formed on the interlayer insulating film 13 using the CVD method, etching using a photoresist is performed, and each word line (control electrode 14) is formed as shown in FIGS. 9A and 9B. Form. At the same time, the floating gate 12 on the element isolation region is removed, and a floating gate is formed for each memory cell.
[0073]
In the flash memory 91, since the source 4 and the drain 3 are formed after the element isolation once, the lateral diffusion of the source 4 and the drain 3 that occurs due to the high-temperature treatment at the time of the element isolation is ensured. Can be prevented.
[0074]
Note that in the flash memory 91, as in the flash memory 80, n ^- Region is n ⁺ You may form so that an area | region may be covered.
[0075]
[Other application examples]
In each of the above embodiments, the interlayer insulating film 13 is formed of a three-layer film (ONO film) of a silicon oxide film, a silicon nitride film, and a silicon oxide film. For example, it may be formed of a silicon oxide film or the like.
[0076]
In each of the above embodiments, n ⁺ After ion implantation of impurities forming the layer, n ^- Impurities forming the layer are ion-implanted. However, n ^- After ion implantation of impurities forming the layer, n ⁺ Impurities for forming the layer may be ion-implanted.
[0077]
【The invention's effect】
With the semiconductor memory device according to the present invention, single memory cells can be arranged in a matrix in a virtual ground array structure, and information can be written by FN tunneling. Therefore, a semiconductor memory device with low power consumption and improved reliability can be provided.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a main part of a structure of a flash memory 1;
2A and 2B are a plan view and a partial cross-sectional view showing a structure of a flash memory 1, respectively.
FIG. 3 is a diagram showing an example of an equivalent circuit 81 of the flash memory 1 and a voltage applied during operation.
4 is a diagram showing a manufacturing process of the flash memory 1. FIG.
5 is a plan view showing the structure of the flash memory 1. FIG.
6 is a plan view showing the structure of the flash memory 1. FIG.
7 is a diagram showing a manufacturing process of the flash memory 1. FIG.
FIG. 8 is a cross-sectional view of a main part showing the structure of a flash memory 80 according to another embodiment.
FIG. 9 is a diagram showing a structure of a flash memory 91 according to another embodiment.
10 is a diagram showing a manufacturing process of the flash memory 91. FIG.
11 is a diagram showing manufacturing steps of the flash memory 91. FIG.
12 is a diagram showing a manufacturing process of the flash memory 91. FIG.
FIG. 13 is a diagram showing a flash memory having a conventional virtual ground array structure. A is a cross-sectional view of the main part, and B is a diagram showing an equivalent circuit 61.
[Explanation of symbols]
3 ... Drain
4 ... Source
8 ... Tunnel oxide film
12 ... Floating gate
13 ... Interlayer insulating film
14 ... Control gate electrode
16: Channel region
B1 to B4 ... bit lines
W1-W3 ... Word line

Claims (1)

A) Single memory cells having a1) to a6) are arranged in a matrix,
a1) a first region of a second conductivity type provided in a first conductivity type region of a semiconductor substrate, the first region being formed using phosphorus as an impurity;
a2) a second region of the second conductivity type provided so as to form an electric circuit forming region with the first region, the second region being formed using arsenic as an impurity;
a3) a first insulating film provided above the electric circuit formable region;
a4) a floating electrode provided above the electric circuit forming region via the first insulating film;
a5) a second insulating film provided above the floating electrode;
a6) a control electrode provided above the floating electrode via the second insulating film;
B) The control electrodes of the single memory cells arranged in the same row are electrically connected to form a control electrode line,
C) The first regions of the single memory cells arranged in the same column are connected to each other in the semiconductor substrate to form a first impurity region line;
D) The second regions of the single memory cells arranged in the same column are connected to each other in the semiconductor substrate to form a second impurity region line,
E) A semiconductor memory device in which a first impurity region line and a second impurity region line of a single memory cell arranged in adjacent columns are shared as impurity region lines,
In the first region, when electrons injected into the floating gate by FN tunneling in the selected memory cell are pulled back to the source, the electrons are pulled back by FN tunneling in the memory cell adjacent to the selected memory cell. A low concentration region having a lower impurity concentration than the second region,
One end of the first region is formed to extend to a region of the first conductivity type below the floating electrode,
The first region is formed so as to overlap to a predetermined position of a lower end portion of the second region, and is formed to be larger than the second region in a direction perpendicular to a semiconductor substrate plane;
A semiconductor memory device.

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