JPH11145312A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device in which the occurrence of read-disturb failure is suppressed by relaxing the electric field which is applied to a tunnel oxide film of unselected cells during the read period. SOLUTION: This device is an electrically rewritable nonvolatile semiconductor memory device constructed with memory cells having a charge storage layer. Therein, the memory cell comprises a stacked-gate type MOS structure field-effect transistor (first MOS-FET) 14 formed on a first major face of a silicon semiconductor layer 10 and having a charge storage layer 12, and a transistor of a MIS-FET structure (second MOS-FET) 16, formed on a second major face of the silicon semiconductor layer 10. The first MOS-FET and the second MOS-FET use n<+> -diffused layers 16 in common.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device for storing a nonvolatile semiconductor memory, and more particularly to a nonvolatile semiconductor memory device capable of reducing the occurrence of read disturb failure of a NAND flash memory.

[0002]

2. Description of the Related Art Conventionally, in a stacked gate type nonvolatile semiconductor memory device, a high voltage is applied to a tunnel oxide film to accumulate electrons in a floating gate or to extract data from the floating gate to retain data. doing. A high voltage is applied to the tunnel oxide film each time the program / erase is performed, and the tunnel oxide film gradually deteriorates. It is known that this deterioration increases the leakage current of the tunnel oxide film even in a low electric field region. Due to the increase in the leak current, a defect (read disturb defect) in which the charge in the floating gate disappears during the read operation has occurred.

Hereinafter, this read disturb defect will be described in detail. FIG. 21 is a sectional view of a cell in a conventional NAND flash memory. A floating gate electrode 104 is formed on a silicon substrate 100 via a first gate insulating film 102 which is a tunnel oxide film, and a control gate electrode 108 is provided on the floating gate electrode 104 via a second insulating film 106. Are formed. And the inside of the broken line A in FIG. 21 indicates one memory cell.

Here, as an example, the threshold voltage of a cell programmed to "0" is about 2 V, and the threshold voltage of a cell (erase cell) programmed to "1" is about -2 V. In this case, in order to read the state of the selected cell, data must be read regardless of whether the unselected cell is programmed to be "1" or "0". Therefore, it is necessary to apply a voltage equal to or higher than the threshold voltage of the programmed cell, for example, 5 V to the word line (control gate electrode) of the unselected cell to make the unselected cell conductive and operate.

Usually, the electric field applied to the tunnel oxide film at this time is 4 to 5 MV / cm. When the characteristics of the tunnel oxide film are not deteriorated, the leak current of the tunnel oxide film is extremely small in this electric field, and the charge loss can be ignored.

[0006]

However, when the program / erase is repeatedly performed as described above, the tunnel oxide film is deteriorated and the leak current increases. Due to the increase in the leak current, a defect that the charge in the floating gate disappears (read disturb defect) occurs.

FIG. 22 shows typical stress leakage current characteristics due to the deterioration of the tunnel oxide film. As can be seen from FIG. 22, the stress leakage current density (Current Dens
) depends on the electric field applied to the tunnel oxide film and the tunnel electric field (Electric Field), and the stress leak current density increases as the electric field applied to the tunnel oxide film increases.

From this, it can be seen that by suppressing the voltage applied to the unselected word line at the time of reading, it is possible to greatly reduce the occurrence of the read disturb failure. Thus, reducing the electric field applied to the tunnel oxide film of the non-selected cell at the time of reading, that is, suppressing the voltage applied to the tunnel oxide film to a low voltage is a major problem for suppressing the occurrence of read disturb failure. It is.

In view of the above, the present invention has been made in view of the above-mentioned problem, and the occurrence of read disturb failure can be suppressed by relaxing the electric field applied to the tunnel oxide film of a non-selected cell at the time of reading. It is an object to provide a nonvolatile semiconductor memory device.

[0010]

According to another aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising an electrically rewritable nonvolatile semiconductor comprising a memory cell having a charge storage layer. A storage device, wherein the memory cell is formed on a first main surface of a stack gate type having the charge storage layer formed on a first main surface of a semiconductor layer, and formed on a second main surface of the semiconductor layer. MIS-F
And a second transistor having an ET structure, wherein the first transistor and the second transistor share a diffusion layer with each other.

Further, in the nonvolatile semiconductor memory device according to the second aspect of the present invention, in the configuration according to the first aspect, the first semiconductor memory device has the first configuration.
The gate length of the first transistor is L1, the gate length of the second transistor is L2 (L1 <L2), the difference between them is ΔL, and the difference between the gate electrode of the first transistor and the gate electrode of the second transistor is When the displacement is represented by δ, the following condition is satisfied: ΔL = L2−L1> 2δ.

Further, the non-volatile semiconductor memory device according to the third aspect has the configuration according to the first or second aspect,
The memory cell is formed in an element region having an SOI (Silicon on Insulator) structure.

Further, a nonvolatile semiconductor memory device according to a fourth aspect of the present invention is characterized in that, in the configuration according to any one of the first to third aspects, the nonvolatile semiconductor memory device has a structure in which two or more memory cells are connected in series. And

Further, the non-volatile semiconductor memory device according to the fifth aspect has the structure according to any one of the first to fourth aspects, and has a structure in which two or more of the memory cells are connected in series. The first transistor in which select gate transistors on the bit line side and the source line side of the memory cell are formed on a first main surface of the semiconductor layer, and the first transistor formed on a second main surface of the semiconductor layer. And a second transistor, wherein the first transistor and the second transistor share a diffusion layer with each other.

Further, the nonvolatile semiconductor memory device according to claim 6 has the configuration according to claim 4 or 5,
At the time of reading data from a selected memory cell, data is read from a selected memory cell connected in series with the non-selected memory cell by applying a voltage to the gate electrode of the second transistor to make the non-selected memory cell conductive. It is characterized by the following.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. First, the structure of a memory cell in a nonvolatile semiconductor memory device according to an embodiment of the present invention will be described.

FIG. 1 is a diagram showing a layout pattern of a memory cell in a nonvolatile semiconductor memory device according to an embodiment of the present invention. As shown in FIG. 1, an SDG section (element area) 2 and a word line 4 are laid out so as to be orthogonal to each other, and an element isolation area 6 is laid out between the SDG sections 2.

FIG. 2A is a sectional view taken along line AA 'in FIG. 1, and FIG. 2B is a sectional view taken along line BB' in FIG. As shown in FIG. 2, a stack gate type MOS structure field effect transistor (hereinafter, referred to as a first layer) having a floating gate electrode 12 as a charge storage layer on the surface side of a first silicon semiconductor layer (hereinafter, a silicon layer) 10. MOS
-FET) 14, and a transistor (hereinafter referred to as a second MOS-FET) 16 having a normal MIS-FET structure is formed on the back side of the first silicon layer 10. The first MOS-FET 14 and the second MOS-FET 16 share the n @ + diffusion layer 18, and the first MOS-FET 14 and the second MOS-FET 16 constitute a memory cell. ing.

More specifically, the first silicon layer 10
A floating gate electrode 12 is formed on a surface side of the first gate insulating film 20 via a first gate insulating film 20 which is a tunnel oxide film, and a second insulating film (ONO insulating film) 2 is formed on the floating gate electrode 12.
2, a control gate electrode 24 is formed. Further, the first MO layer is provided in the first silicon layer 10.
An n @ + diffusion layer 18 serving as a source or a drain of the S-FET 14 is formed. As a result, a first MOS-FET 14 is formed on the front side of the first silicon layer 10.

A gate electrode 28 is formed on the back surface of the first silicon layer 10 with a third gate insulating film 26 interposed therebetween. Then, n in the first silicon layer 10
+ Diffusion layer 18 is shared with the first MOS-FET 14 and a second MOS-F
ET16 is formed. The second MOS-FET 16
An insulating film 30 is formed under the insulating film 30, and a second silicon substrate 32 is provided below the insulating film 30.

Next, the operation of the memory cell of the nonvolatile semiconductor memory device thus configured will be described. FIG.
FIG. 2 is a schematic circuit diagram of a memory cell in the nonvolatile semiconductor memory device. This memory cell has an SOI (Si
(Electronic Insulator) structure, the erasing method is significantly different from that of a normal NAND flash memory. This is because an electrode for controlling the potential of the SOI substrate is not prepared in order to have an SOI structure and to suppress an increase in the area of the memory cell, and the first silicon layer corresponding to the substrate (well) potential is not provided. Is floating in the p-type region. Therefore, in a normal NAND flash memory cell, erasing is performed by applying a positive voltage to the well, but such an operation becomes impossible in this memory cell.

Therefore, erasure is performed by the following operation. FIG. 4 is a diagram showing a control signal for causing an erasing operation to be performed. At the time of erasing, for example, the following voltages are applied to the respective terminals. VSL = 0V, VBL = 0V, Vsgs (Vsgs1, Vsgs2) = 5V, Vs
gd (Vsgd1, Vsgd2) = 5V, and then the control gate electrode 24 of the non-selected cell and the second MOS-
Vbgi = 5V or Vcgi = 5V is applied to at least one of the gate electrodes (non-selection gates) 28 of the FET 16. In this state, the potentials of the n + diffusion layers 18 as the source and drain of the selected cell are VSL and V
BL, and VSL and VBL are at 0V, so that both n + diffusion layers 18 of the selected cell are at 0V.

When one of the control gate electrode 24 of the non-selected cell and the gate electrode 28 of the second MOS-FET 16 is set to 5V, the other may be set to 0V, for example. Further, from the viewpoint of suppressing the occurrence of leakage current in the first gate insulating film 20 which is a tunnel oxide film, Vbgi = 5V is applied to the gate electrode 28 of the second MOS-FET 16 of the non-selected cell, and the control gate electrode 24 Is preferably Vcgi = 0V.

Here, an erasing voltage, for example, Vcgi = -20 V is applied to the control gate electrode 24 of the selected cell.
Gate electrode 28 of second MOS-FET 16 of selected cell
Is floating, for example. By this voltage application, electrons are applied to the floating gate electrode 12 using the tunnel effect in an overlap region where the floating gate electrode 12 of the selected cell and the n + diffusion layer 18 overlap with the tunnel oxide film interposed therebetween.
To the n @ + diffusion layer 18. As a result, a tunnel current (FN current) flows, and the selected cell is erased.
After elapse of a desired erase time (Tpe), the control gate electrode 2
4 is applied with Vcgi = 0V, and other signals are sequentially turned off (0
V) to perform erasure.

This operation can be performed collectively for the word line to which the selected cell is connected. Furthermore, by sequentially erasing cells connected in series,
All memory cells can be erased.

Here, both the source side and the drain side of the select gate transistor are the first side on the silicon layer surface side.
A channel and a second channel on the back side of the silicon layer,
Although an example of using both of them at the same potential has been described, the present invention is not limited to this, and on both the source side and the drain side, a gate electrode is provided only on one side of the front surface and the back surface, and only one channel is formed. Alternatively, for example, 0 V may be applied to any one of the gate electrodes, and only one of the channels may be turned on to operate.

Next, the write operation will be described. FIG. 5 is a diagram showing control signals for executing a write operation. Apply 0V to the bit line for “0” write,
For example, 9 V is applied to the bit line for writing “1”. As shown in FIG. 5, Vcgi = 20 V is applied to the write word line (select gate) on the word line side,
Vcgi = 0V is applied to an unselected word line (unselected gate). Further, Vbg is applied to a non-selected cell (non-selected gate).
i = 10 V is applied so that the potential of the bit line can be transferred to the cell. As for the select gate transistor, Vsgd = 10 V and Vsgs = 0 V on the drain side.
Is applied.

In the case of this operation, the second MOS of the selected cell
Regarding the gate electrode (selection gate) 28 of the FET 16, the operation is possible regardless of whether Vbgi = 0 V or 10 V is applied, and the operation may be floating. After a desired writing time (Tpw), writing can be performed by sequentially lowering the voltage of the control signal to 0V.

At this time, the control gate electrode 2 of the non-selected cell
4 (non-selection gate) is set to Vcgi = 0V or floating. For this reason, although the erroneous write margin and the like are insufficient in the conventional technique, the margin is greatly increased.

Here, both the source side and the drain side of the select gate transistor are located on the first side of the silicon layer surface side.
A channel and a second channel on the back side of the silicon layer,
Although an example of using both of them at the same potential has been described, the present invention is not limited to this, and on both the source side and the drain side, a gate electrode is provided only on one side of the front surface and the back surface, and only one channel is formed. Alternatively, for example, 0 V may be applied to any one of the gate electrodes, and only one of the channels may be turned on to operate.

Next, the read operation will be described. FIG. 6 is a diagram showing a control signal for executing a read operation. At the time of reading, Vcgi = 0 V is applied to the word line (select gate) of the selected cell, and Vcgi = 0 V is applied to the word line (non-selected gate) of the unselected cell, or the word line is floating, and the second MOS-FET 16 of the selected cell is set.
The gate electrode (selection gate) 28 is also set to Vbgi = 0V. On the other hand, Vbgi = 5V is applied to the gate electrode (non-selection gate) 28 of the second MOS-FET 16 of the non-selected cell to turn on the second MOS-FET 16, and all the non-selected cells of the cells connected in series are turned on. Turn on. As a result, a cell current corresponding to the amount of charge in the floating gate electrode 12 flows, and reading out becomes possible by detecting the cell current.

At this time, in a normal NAND flash memory cell, a high voltage is applied to the control gate electrode 24 of the non-selected cell in order to turn on the non-selected cell without depending on the charge amount in the floating gate 12. The application of this voltage deteriorates the tunnel oxide film and increases the leak current. Therefore, the application of the voltage to the control gate electrode 24 causes a defect (read disturb defect) that causes the charge in the floating gate 12 to disappear. However, in this embodiment, since no voltage is applied to the control gate electrode 24 of such an unselected cell, the loss of the charge in the floating gate 12 can be suppressed to a remarkably low level.

In this case, both the source side and the drain side of the select gate transistor are formed on the first side of the silicon layer surface side.
A channel and a second channel on the back side of the silicon layer,
Although an example of using both of them at the same potential has been described, the present invention is not limited to this, and on both the source side and the drain side, a gate electrode is provided only on one side of the front surface and the back surface, and only one channel is formed. Alternatively, for example, 0 V may be applied to any one of the gate electrodes, and only one of the channels may be turned on to operate.

Next, a method of manufacturing the nonvolatile semiconductor memory device according to this embodiment will be described. FIG. 7 (a),
17B to 17A and 17B are cross-sectional views of respective manufacturing steps showing a method for manufacturing the nonvolatile semiconductor memory device according to this embodiment.

First, as shown in FIGS. 7A and 7B,
An element isolation region 6 is formed on the silicon layer 10, and a third gate insulating film 2 is formed in the element region surrounded by the element isolation region 6.
6 is formed, for example, with a silicon oxide film to a thickness of 150 Å. On this third gate insulating film 26, for example, L
A polycrystalline silicon film 28 is formed to a thickness of 2000 angstroms by the PCVD method.

Subsequently, phosphorus (P) is introduced as an impurity into the polycrystalline silicon film 28 by a heat treatment in a gas to which POCl 3 is added. Further, a resist pattern 40 as shown in FIGS. 7A and 7B is formed by lithography.

Then, using the resist pattern 40 as a mask material, the polycrystalline silicon film 28 into which phosphorus has been diffused by RIE is processed, and as shown in FIGS. The gate electrode 28 of the FET 16 is formed.

Subsequently, as shown in FIGS. 9A and 9B, the insulating film 30 is formed to 10000 angstroms. This insulating film 30 is formed of, for example, a silicon oxide film by a CVD method. Further, as shown in FIGS. 10A and 10B, the insulating film 30 is etched back to flatten the surface of the insulating film 30. This planarization is performed, for example, by CMP.
It may be performed by a method.

Next, as shown in FIGS. 11A and 11B, the surface of the insulating film 30 on the silicon layer 10 and the surface of the separately prepared silicon substrate 32 are bonded. After that, annealing is performed at, for example, 800 ° C. or more in order to increase the strength of the bonding interface.

Further, as shown in FIGS. 12A and 12B, the silicon layer 10 is thinned. This is because, for example, the silicon layer 10 is thinned by polishing, etc.
Etching is performed by the P method or the like, and the etching is completed when the surface of the element isolation region 6 is exposed. Through this process, island-shaped SOI (Silicon on Ins)
(ulator) type SDG section 2 is formed.

Thereafter, the non-volatile semiconductor memory device is formed by a normal NAND flash memory manufacturing process. The steps will be described briefly below. FIG.
As shown in (a) and (b), a first gate insulating film 20 having a tunnel oxide film is formed on the surface of the SDG portion 2, and further, for example, LP on the first gate insulating film 20 is formed.
The polycrystalline silicon film 12 is formed to 1500 angstroms by the CVD method. Subsequently, phosphorus (P) is introduced as an impurity into the polycrystalline silicon film 12 by, for example, a heat treatment in a gas to which POCl3 is added. Thereafter, slits 42 are formed in the cell array portion by a normal lithography method.
To form

Subsequently, as shown in FIGS. 14A and 14B, the surface of the polycrystalline silicon film 12 is oxidized to form an oxide film having a thickness of 50 Å.
A 100 .ANG. Silicon nitride film is formed by the VD method, and a 50 .ANG. Silicon oxide film is formed on the silicon nitride film. The ONO film 22 is formed by these three films.

Thereafter, for example, L
The polycrystalline silicon film 24 is formed to 4000 angstroms by the PCVD method. Subsequently, the polycrystalline silicon film 24 is subjected to a heat treatment in a gas to which POCl3 is added.
Phosphorus (P) is introduced therein as an impurity. Although not shown here, a high melting point metal silicide such as tungsten silicide may be laminated on the polycrystalline silicon film 24.

Subsequently, for processing the cell portion, a resist pattern 44 as shown in FIGS. 15A and 15B is formed by lithography. Then, FIG.
As shown in (b), the polycrystalline silicon film 2 in which phosphorus has been diffused using the resist pattern 44 as a mask material.
4. The ONO film 22 and the polycrystalline silicon film 12 in which phosphorus is diffused are sequentially processed by RIE to form the control gate electrode 24 and the floating gate electrode 12.

Further, as shown in FIGS. 17A and 17B, arsenic (A) is formed using the control gate electrode 24 as a mask.
By ion implantation of s), an n @ + diffusion layer 18 is formed. Thereafter, the non-volatile semiconductor storage device is manufactured according to a normal process.

In the above embodiment, as shown in FIG. 7B, the element isolation region 6 is partially formed in the silicon layer 10.
And has a raised structure on the silicon layer 10. However, the surface of the silicon layer 10 does not need to be raised particularly. For example, as shown in FIG. It is also possible to use an element isolation region 50 having a trench structure in which the insulating film is buried. FIG. 19 shows a nonvolatile semiconductor memory device manufactured using the element isolation region 50 having the trench structure.

Although the method of manufacturing the select gate transistor is not specifically described in the above embodiment, the first and second MOs are manufactured in the same manufacturing process as that of the memory cell.
A structure having an S-FET can be employed. In this case, since the select gate transistor and the cell can be formed in the same process, there is an advantage that the processing in the cell array becomes easy.

As described above, according to the nonvolatile semiconductor memory device of this embodiment, the electric field is not applied to the tunnel oxide film of the non-selected cell at the time of reading the selected cell without increasing the area of the memory cell. Therefore, it is possible to suppress occurrence of a defect (read disturb defect) due to missing stored data in a non-selected cell due to a read operation.

Further, a transistor on the back gate side (second M
Since the bit line voltage can be transferred by the OS-FET 16),
Improves resistance. Further, by using a similar structure for the select gate transistor, the current driving capability of the select gate transistor is improved and the operation performance is improved. Also,
In the cell, an intermediate potential is transferred at the time of writing "1". However, since the cell has an SOI structure and has no dependency on the substrate voltage with respect to the threshold voltage, the potential can be easily transferred. An intermediate potential can be transferred by applying a low voltage. Thereby, a cell design margin is improved.

Incidentally, in the manufacturing method described above, n +
The diffusion layer 18 is formed in a self-aligned manner with respect to the floating gate electrode 12 and the control gate electrode 24, but is not formed in a self-aligned manner with respect to the gate electrode 28. Therefore, when the misalignment at the time of lithography is large, the second MOS having the gate electrode 28 as a gate is used.
-The case where the FET 16 cannot be formed, that is, the case where an offset type MOS-FET is formed occurs. In order to prevent the offset-type MOS-FET from being formed, it is preferable to design the memory cell according to the following dimensional relationship of the memory cells.

In the following, a description will be given of the dimensional relationship of memory cells for increasing the margin of lithography alignment margin in the process of manufacturing the nonvolatile semiconductor memory device of the above embodiment.

FIG. 20 is a cross-sectional view of a nonvolatile semiconductor memory device showing the dimensional relationship of memory cells for increasing the margin of lithography alignment margin. As shown in FIG. 20, a first gate insulating film 20, which is a tunnel oxide film, a floating gate electrode 12, an ONO insulating film 22, and a control gate electrode 24 are sequentially provided on the upper surface side of the silicon layer 10, In the silicon layer 10 on both sides of the control gate electrode 24, a stacked first MOS-FET 14 having an n @ + diffusion layer 18 serving as a source and a drain is formed. Further, a second MO having a third gate insulating film 26 and a gate electrode 28 on the lower surface side of the silicon layer 10 is formed.
An S-FET 16 is formed.

Here, assuming that the misalignment by the lithography method is δ, as shown in FIG. 20, this misalignment δ is the amount of misalignment between the control gate electrode 24 and the gate electrode 28 on the drawing. Further, the gate length of the control gate electrode 24 is set to L
1. Assuming that the gate length of the gate electrode 28 is L2 and the difference between them is ΔL, the nonvolatile semiconductor memory device of the above embodiment satisfies ΔL = L2−L1> 2δ (1) Upper control gate electrode 24 and gate electrode 28
If the centers in the channel length direction match, the second
MOS-FET 16 is an offset type MOS-FET
It does not become. Therefore, the second MOS-FET 16
As long as the difference ΔL between the gate length L2 of the first MOS-FET 14 and the gate length L1 of the first MOS-FET 14 satisfies the expression (1), the second MO
The S-FET 16 does not become an offset type MOS-FET, and a desired operation can be realized.

That is, the memory cell side (the first MOS-
FET 14) is MOS-FE to the stack gate.
Although the source and drain of T (n @ + diffusion layer 18) can be formed by self-alignment, the pass transistor on the back channel side (second MOS-FET 16 side) cannot be formed by self-alignment. Therefore, in this case, if the alignment margin with the diffusion layer is not very strictly managed, there is a possibility that the MOS-FET will be an offset type MOS FET, and if the alignment margin is not large, the management is difficult. Therefore, by making the gate length L2 on the back channel side longer than the gate length L1 on the memory cell side so as to have the above-described dimensional relationship, the alignment margin is expanded to facilitate management, and an offset type MOS-FET is obtained. Possibilities can be eliminated.

[0055]

As described above, according to the present invention, by reducing the electric field applied to the tunnel oxide film of a non-selected cell at the time of reading, the occurrence of a read disturb failure can be suppressed. It is possible to provide a storage device.

[Brief description of the drawings]

FIG. 1 is a diagram showing a layout pattern of a memory cell in a nonvolatile semiconductor memory device according to an embodiment of the present invention;

2A is a cross-sectional view along AA 'in FIG. 1, and FIG. 2B is a cross-sectional view along BB' in FIG.

FIG. 3 is a schematic circuit diagram of a memory cell in the nonvolatile semiconductor memory device according to the embodiment of the present invention;

FIG. 4 is a diagram showing a control signal for causing an erasing operation to be performed.

FIG. 5 is a diagram showing control signals for executing a write operation.

FIG. 6 is a diagram showing a control signal for executing a read operation.

FIG. 7 is a cross-sectional view of a manufacturing step showing the method for manufacturing the nonvolatile semiconductor memory device of this embodiment.

FIG. 8 is a cross-sectional view of a manufacturing step showing a method for manufacturing the nonvolatile semiconductor memory device of the embodiment.

FIG. 9 is a cross-sectional view of a manufacturing step showing a method for manufacturing the nonvolatile semiconductor memory device of this embodiment.

FIG. 10 is a cross-sectional view of a manufacturing step showing the method for manufacturing the nonvolatile semiconductor memory device of this embodiment.

FIG. 11 is a cross-sectional view of a manufacturing step showing the method for manufacturing the nonvolatile semiconductor memory device of this embodiment.

FIG. 12 is a cross-sectional view of a manufacturing step showing a method for manufacturing the nonvolatile semiconductor memory device of this embodiment.

FIG. 13 is a cross-sectional view of a manufacturing step showing the method for manufacturing the nonvolatile semiconductor memory device of this embodiment.

FIG. 14 is a cross-sectional view of a manufacturing step showing a method for manufacturing the nonvolatile semiconductor memory device of this embodiment.

FIG. 15 is a cross-sectional view of a manufacturing step showing the method for manufacturing the nonvolatile semiconductor memory device of this embodiment.

FIG. 16 is a cross-sectional view of a manufacturing step showing the method for manufacturing the nonvolatile semiconductor memory device of this embodiment.

FIG. 17 is a cross-sectional view of a manufacturing step showing a method for manufacturing the nonvolatile semiconductor memory device of this embodiment.

FIG. 18 is a cross-sectional view showing a manufacturing step of the nonvolatile semiconductor memory device according to the modification of the embodiment.

FIG. 19 is a cross-sectional view of a nonvolatile semiconductor memory device according to a modification of the embodiment.

FIG. 20 is a cross-sectional view of a nonvolatile semiconductor memory device showing a dimensional relationship of a memory cell for expanding a margin of lithography alignment allowance.

FIG. 21 is a sectional view of a memory cell in a conventional NAND flash memory.

FIG. 22 is a diagram showing typical stress leak current characteristics due to deterioration of a tunnel oxide film.

[Explanation of symbols]

2 SDG part 4 Word line 6 Element isolation region 10 First silicon semiconductor layer (silicon layer) 12 Floating gate electrode 14 Stack gate type MOS structure field effect transistor (first MOS-FET) 16... A transistor having a MIS-FET structure (second transistor)
18 n + diffusion layer 20 first gate insulating film 22 second insulating film (ONO insulating film) 24 control gate electrode 26 third gate insulating film 28 gate electrode 30 Insulating film 32 second silicon substrate 40 resist pattern 42 slit 44 resist pattern 50 element isolation region

Claims (6)

[Claims] 1. An electrically rewritable nonvolatile semiconductor memory device comprising a memory cell having a charge storage layer, wherein the memory cell is formed on a first main surface of a semiconductor layer. A first transistor of a stack gate type having a layer and an M formed on a second main surface of the semiconductor layer.
A nonvolatile semiconductor memory device comprising a second transistor having an IS-FET structure, wherein the first transistor and the second transistor share a diffusion layer with each other. 2. The gate length of the first transistor is L
1. The gate length of the second transistor is L2 (L1 <
L2), when ΔL is the difference between the two, and δ is the displacement between the gate electrode of the first transistor and the gate electrode of the second transistor, ΔL = L2−L1> 2δ. The nonvolatile semiconductor memory device according to claim 1, wherein 3. The memory cell according to claim 1, wherein the memory cell is an SOI (Silicon on Silicon).
3. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is formed in an element region having an Insulator structure. 4. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device has a structure in which two or more memory cells are connected in series. 5. A memory cell having a structure in which two or more memory cells are connected in series, and a select gate transistor on a bit line side and a source line side of the memory cell is a first gate of the semiconductor layer.
And a second transistor formed on a second main surface of the semiconductor layer. The first transistor and the second transistor are diffused with each other. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device shares a layer. 6. When reading data from a selected memory cell,
The data of a selected memory cell connected in series with the non-selected memory cell is read by applying a voltage to the gate electrode of the second transistor to make the non-selected memory cell conductive. Or the nonvolatile semiconductor memory device according to 5.