JP2815079B2 - Semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to power saving.

[0002]

2. Description of the Related Art There is known a flash memory of a virtual ground array structure which does not require a contact in a cell array and can reduce a cell size. The virtual ground array structure means that when memory cells are arranged in a matrix, a source region of a certain memory cell and a drain region of a memory cell arranged in a column adjacent to the memory cell are shared.

FIG. 12B shows an equivalent circuit 61 of a flash memory having a virtual ground array structure. As shown in the figure,
The source region of the memory cell C22 and the drain region of the memory cell C21 arranged in an adjacent column are shared, and these shared regions constitute a bit line B2.

FIG. 12A shows a structure of a nonvolatile memory 50 constituting each memory cell. The nonvolatile memory 50 has an n ⁺ -type drain 3 and an n ^{+ -type} source 4 provided in a p-type silicon well 2 provided in a substrate. A channel region 16 is provided between the drain 3 and the source 4. A tunnel oxide film 8 is provided on channel region 16. further,
On the tunnel oxide film 8, a floating gate 12 made of polysilicon, an interlayer insulating film 13, and a control gate electrode 14 are sequentially provided.

[Writing, erasing, and reading principle] Writing and erasing of information in the nonvolatile memory 50 will be described. When writing information "1", a high voltage is applied to the control gate electrode 14 and the drain 3,
In addition, a ground potential is applied to the source 4 and the well 2. As a result, hot electrons generated near the drain 3 jump over the potential barrier of the tunnel oxide film 8 and flow into the floating gate 12.

The threshold value of the control gate voltage for forming a channel in the channel region 16 rises due to the electrons thus flowing. This state is a state where the information “1” is written in the flash nonvolatile memory 50 (hereinafter, referred to as a write state).

On the other hand, when storing (erasing) information "0" in the nonvolatile memory 50, the floating gate 1
In order to return the electrons flowing into the well 2 to the well 2, a high voltage is applied between the floating gate 12 and the well 2 in a direction opposite to that in writing information. As a result, an electric field is generated in the direction opposite to that during writing, and the FN (Fowler-Nordh
eim) Electrons are pulled back to well 2 by tunneling.

[0008] By drawing back the electrons,
The threshold value of the control gate voltage for forming a channel in the channel region 16 drops. This state
This is a state where information “0” is stored in the nonvolatile memory 50 (hereinafter, referred to as a non-write state).

Next, the operation of reading information from the nonvolatile memory 50 will be described. First, a sense voltage Vs is applied to the control gate electrode 14. The sense voltage Vs is an intermediate voltage between the threshold voltage in a write state and the threshold voltage in a non-write state.

When the nonvolatile memory 50 is in a write state, the sense voltage is set higher than the threshold voltage of the nonvolatile memory 50.
Since Vs is lower, no channel is formed in the channel region 16. Therefore, even when the potential of the drain 3 is higher than the potential of the source 4, no current flows between the drain 3 and the source 4.

On the other hand, when the non-volatile memory 50 is in the non-writing state, the sense voltage Vs is higher than the threshold voltage of the non-volatile memory 50.
A channel is formed in the channel. Therefore, by making the potential of the drain 3 higher than the potential of the source 4, a current flows between the drain 3 and the source 4.

As described above, in the nonvolatile memory 50, at the time of reading, the control gate electrode 14
By applying a sense voltage Vs, which is a voltage between the threshold voltages of the write state and the non-write state, whether or not a channel is formed in the channel region 16 is detected, and the write state or the non-write state is detected. Determine the status.

[Operation when Combined in Matrix] By the way, when the nonvolatile memory 50 is arranged in a virtual ground array structure, memories other than memory cells desired to be written or read (hereinafter referred to as selected cells) There is a possibility that writing or reading is performed on the cell. Therefore, in the equivalent circuit 61, the selection cell can be reliably selected as described below. (Note that a cell other than the selected cell is hereinafter referred to as an unselected cell).

First, writing will be described. A high voltage is applied to the word line W2 and the bit line B3, and the bit lines B1 and B4 are opened.
2. The word lines W1, W3 and well 2 are set to the ground potential. Looking at the selected cell C22, a high voltage is applied to the control gate electrode 14 and the drain 3, and a ground potential is applied to the source 4 and the well 2. As a result, hot electrons are generated in the vicinity of the drain 3 and a write state is set.

As for the unselected cells C21 and C23, since the source or the drain is open, no hot electrons are generated and no writing state occurs.
For the other unselected cells C11 to C13 and C31 to C33, the control gate electrode 14 is at the ground potential,
There is no write state. Thus, only the selected cell can be written.

Reading is performed as follows.
When the cell C22 is selected, the word line W2
And the bit lines B1 and B4 are opened, the word lines W1, W3 and well 2 are set to the ground potential, a potential difference is generated between the bit lines B3 and B2, and a sense amplifier is connected to the bit line B2. I do.

When the cell C22 is in a write state, no channel is formed in the channel region 16 as described above, and no current flows between the drain 3 and the source 4. On the other hand, in a non-writing state, a channel is formed in the channel region 16 and a current flows between the drain 3 and the source 4. This can be read by a sense amplifier connected to the bit line B2.

Since the source or drain of the unselected cells C21 and C23 is open, no current flows between the drain 3 and the source 4 even if the cell is in a non-writing state. Other unselected cells C11 to C13, C3
For 1 to C33, since the control gate electrode 14 is at the ground potential, no channel is formed in the channel region 16. Therefore, no current flows between the drain 3 and the source 4. In this way, only the information of the selected cell can be read.

For erasing, the word lines W1 to W4 are set to the ground potential, and a high voltage is applied to the well 2 in the direction opposite to the direction of writing. This causes the electrons to be pulled back to source 4,
The memory cells are collectively erased.

As described above, by forming the nonvolatile memory 50 with a virtual ground array structure, no contact is required, and the cell area can be reduced.

[0021]

However, the above-mentioned flash memory has the following problems. At the time of writing, since the hot electron injection method is used, the tunnel oxide film 8 is deteriorated. For this reason, there was a possibility that the reliability as an element might be reduced.
Also, in the hot electron injection method, only a very small amount (about 1%) of the electrons flowing between the source and the drain flow into the floating gate 12, so that the injection efficiency is poor. For this reason, power consumption increases.

An object of the present invention is to provide a semiconductor memory device which solves the above-mentioned problems and has low power consumption and improved reliability.

[0023]

According to a first aspect of the present invention, there is provided a semiconductor memory device comprising: A) a1) to a10), a single memory cell arranged in a matrix, a1) a first region, and a2) a first memory cell. A first circuit-forming area formed adjacent to the area; a3) a third circuit-forming area formed adjacent to the first circuit-forming area
Region, a4) a second electric circuit formable area formed adjacent to the third area, a5) a second electric circuit formable area formed adjacent to the second electric circuit formable area
Region, a6) a first insulating film provided above the first electric circuit forming area, a7) a second insulating film provided above the second electric circuit forming area, a8) second insulating film A2) a second control electrode for the second electrical path forming area provided above the film, a9) a floating electrode provided above the first electrical path forming area via the first insulating film, a10) A third insulating film provided above the second control electrode and the floating electrode, a11) a third insulating film provided above the floating electrode via the third insulating film for the first electric path forming area. B) the second control electrode of a single memory cell arranged in the same row is electrically connected to form a second control electrode line; and C) the second control electrode is arranged in the same column. The first region of the single memory cell is electrically connected to form a first region line, and D) in the same column. A second region line of the single memory cell placed is electrically connected to form a second region line; and E) a first region line of the single memory cell arranged in an adjacent column. F) the first control electrode of a single memory cell arranged in the same column is electrically connected to form a first control electrode line, while the second region line is shared as a region line. , Is characterized.

According to a second aspect of the present invention, there is provided a semiconductor memory device comprising: A) a1) to a10), a single memory cell arranged in a matrix, a1) a first region, and a2) a first region adjacent to the first region. A3) a second electric path forming area formed adjacent to the second electric path forming area;
Region, a4) a first insulating film provided above the first electric circuit forming area, a5) a second insulating film provided above the second electric circuit forming area, a6) second insulating film A7) a fourth insulating film provided above the second control electrode, a8) a second control electrode provided above the film for the second electrical path forming area, a8) a fourth insulating film provided above the second control electrode. A9) a third insulating film provided above the floating electrode, a10) a third insulating film provided above the floating electrode, and provided over the part where the electrical path can be formed; B) a first control electrode for a first electric circuit formable region provided above the floating type electrode via the insulating film of B), B) a second control electrode of a single memory cell arranged in the same row C) the first region of a single memory cell arranged in the same column is electrically connected to form a second control electrode line. To form a first region line. D) The second region of a single memory cell arranged in the same column is electrically connected to form a second region line. E) the first region line and the second region line of the single memory cell arranged in the adjacent column are shared as the region line; and F) the first control of the single memory cell arranged in the same column. The electrodes are electrically connected to form a first control electrode line.

According to a third aspect of the present invention, a semiconductor memory device comprises:
The region is a source, the second region is a drain,
The control electrode line is a select gate electrode line, and the first control electrode line is a control gate electrode line.

In the method of using the semiconductor memory device according to the fourth aspect of the present invention, A) When writing, a1) Apply a writing voltage only to the control gate electrode line to which the memory cell to be written is connected; ) A write inhibit voltage is applied to a region line to which a source of a memory cell not desired to be written is connected, and a3) The write inhibit voltage is not transferred to a first electric path formable region of a memory cell desired to be written. The write inhibit voltage cut-off voltage is applied to the select gate electrode line of the memory cell to be written. B) When reading, b1) To the control gate electrode line to which the memory cell to be read is connected. B2) Select gate voltage connected to the memory cell desired to be read A voltage is applied to only the pole lines to make the second conductive path formable region conductive.b3) A difference is provided between the voltages applied to the source and the drain only in the memory cells desired to be read, and whether or not a current flows Reading, using the semiconductor memory device.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, comprising: A) arranging a single memory cell manufactured in a process including the following steps a1) to a8) in a matrix. A1) a step of forming an insulating film having a thin film portion on a first conductivity type region of a semiconductor substrate; a2) a floating type film above the thin film portion as a first insulating film; Forming an electrode and forming a second control electrode thereabove using a portion other than the thin film portion as a second insulating film, a3) using the floating electrode and the control electrode for forming a circuit as a mask to remove impurities. By implanting and diffusing, a third region of the second conductivity type is formed in the region of the first conductivity type between the floating electrode and the second control electrode, and a lower region of the second control electrode is sandwiched therebetween. The second region of the second conductivity type on the opposite side Area
Forming a first region of the second conductivity type on the side opposite to the lower region of the floating electrode; a4) forming a third insulating film above the floating electrode and the second control electrode; a5) The first insulating film is provided above the floating electrode via the third insulating film.
Forming a control electrode; B) for single memory cells arranged in the same column, the first regions are electrically connected and formed simultaneously; C) for single memory cells arranged in the same column. D) the second region is electrically connected and formed simultaneously; and D) for a single memory cell arranged in an adjacent column, the first region and the second region are shared and formed; For single memory cells arranged in a row, the first control electrodes are electrically connected and formed simultaneously; F) For single memory cells arranged in the same column, the second control electrode is electrically connected And formed at the same time.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, comprising: A) arranging a single memory cell manufactured in a process including the following steps a1) to a8) in a matrix. A1) a step of forming a second insulating film on a surface of a first conductivity type region in a semiconductor substrate; a2) a step of forming a second control electrode on a part of the second insulating film; a3) forming a fourth insulating film above the second control electrode; a4) setting the surface of the first conductivity type region below the second control electrode as a second electric path formable region; Forming a first insulating film above the first conductive path forming region using a first conductive type semiconductor region adjacent to the first electric path forming region as a first conductive path forming region; Floating formed above the first electrical path forming area via the first insulating film Forming an electrode, a floating electrode covering a part of the control electrode for forming an electrical path via the fourth insulating film; a6) forming a third insulating film above the floating electrode; A7) Impurities are implanted and diffused by using the floating type electrode and the control electrode for forming a circuit as a mask, and the first conductive type region and the second conductive type region are formed in the first conductive type region on the floating type electrode side.
Forming a second region of the second conductivity type in the region of the first conductivity type on the control electrode side; a8) forming a first region above the floating electrode through the third insulating film;
B) forming a first control electrode for an electric circuit formable region, B) for a single memory cell arranged in the same column, the first region is electrically connected and formed simultaneously, C) in the same column For a single memory cell arranged, the second region is electrically connected and formed simultaneously; D) For a single memory cell arranged in an adjacent column, the first region and the second region are E) For a single memory cell arranged in the same row, the first control electrode is electrically connected and formed simultaneously; F) For a single memory cell arranged in the same column, The second control electrode is electrically connected and formed at the same time.

[0029]

The semiconductor memory device according to the present invention functions as follows when operated.

[Write] At the time of writing, a write voltage is applied only to the control gate electrode line to which the memory cell to be written is connected. As a result, an electric field is generated between the floating electrode and the semiconductor substrate in the memory cell where writing is desired, and the FN (Fowler-N) is generated.
ordheim) Tunneling moves electrons to the floating electrode.

For a memory cell for which writing is not desired, writing is prevented as follows. Of the memory cells that do not want to write, the memory cells connected to the control gate electrode line to which the memory cell that wants to write is connected have a write inhibit voltage applied to the first region. This write prohibition voltage is transferred to the first electric circuit formable area. As a result, an electric field sufficient to cause FN tunneling between the floating electrode and the semiconductor substrate is not generated, and writing is not performed.

For the other memory cells,
Since no write voltage is applied, no data is written.

Each memory cell has a second control electrode for a second area in which a path can be formed. Therefore, for the memory cell desired to be written, the second electric path forming area can be made non-conductive at the time of writing. With this, with respect to a single memory cell arranged in an adjacent column, even if the first region and the second region are shared, the write prohibition applied to the first region of the memory cell for which writing is not desired. The voltage can be prevented from being transferred to the first path-formable region of the memory cell desired to be written.

[Reading] At the time of reading, information of a memory cell desired to be read is read as follows. A sense voltage is applied only to a control gate electrode line to which a memory cell desired to be read is connected. In addition, a voltage is applied to the select gate electrode line to which the memory cell desired to be read is connected so as to make the second conductive path formable region conductive. Further, a difference is provided between voltages applied to the source and the drain of the memory cell desired to be read, and whether or not a current flows is read.

As a result, the memory cell for which reading is desired is in the following state. A voltage is applied to make the second conductive path formable region conductive, and a difference is provided between voltages applied to the source and the drain. Here, by applying a sense voltage to the control gate electrode line, if electrons are not injected into the floating electrode, the first electric path formable region is in a conductive state. On the other hand, if electrons are injected into the floating electrode, the first circuit path formable region does not become conductive. Therefore, information of a memory cell desired to be read can be read depending on whether a current flows between the source and the drain.

The memory cells for which reading is not desired are in the following state. Of the memory cells that do not want to read, those memory cells that are connected to the select gate electrode line to which the memory cell that wants to read are connected have the second electrical path formable region in a conductive state. However, no current flows because there is no difference between the voltages applied to the source and the drain. The sense voltage is not applied to the other memory cells, and the first circuit path-formable region is in a non-conductive state. Therefore, no information is read out by mistake.

[0037]

【Example】

[Structure of Flash Memory 1] An embodiment of the present invention will be described with reference to the drawings. First, FIGS. 2 to 4 show a flash memory 1 according to an embodiment of the present invention. FIG. 4 is a plan view of the flash memory 1, and FIG.
FIG. 2B is a cross section taken along line BB of FIG. 4, and FIG. 3 is a cross section taken along line CC of FIG.

As shown in FIG. 2A, the flash memory 1
In, the nonvolatile memory 50 forming a single memory cell is arranged in a virtual ground array structure. The non-volatile memory 50 includes, in a p-type silicon well 2 provided in a substrate, an n ⁺ -type drain 3 as a second region and a first region.
An n ^{+ type} source 4 as a region is provided. Between the drain 3 and the source 4, there are a channel region 16 which is a region where a first electric circuit can be formed, and a channel region 17 which is a region where a second electric circuit can be formed.

Above the channel region 17, a gate oxide film 18 as a second insulating film is provided.
Above 8, a select gate electrode 22 as a second control electrode is provided. The surface of the select gate electrode 22 is covered with a silicon oxide film 10 as a fourth insulating film.

Above the channel region 16, a tunnel oxide film 8 as a first insulating film is provided. Above the tunnel oxide film 8, a floating gate 12 as a floating electrode is provided. Gate 12
Covers a part of the select gate electrode 22 via the silicon oxide film 10. Above the floating gate 12, a control gate electrode 14 as a first control electrode is provided via an interlayer insulating film 13 as a third insulating film.

As shown in FIGS. 4 and 2B, select gate electrode 22 of a single memory cell arranged on the same row
Are electrically connected to form a select gate electrode line S1. Select gate electrode lines S1, S
2, S3 are provided for each column as shown in FIG.

As shown in FIGS. 4, 2A, and 3, the sources 4 of the single memory cells arranged in the same column are formed by being electrically connected. Similarly, the drains 3 of each single memory cell arranged in the same column are formed to be electrically connected. Further, the drain 3 of a single memory cell and the source 4 of a single memory cell arranged in a column adjacent to the single memory cell are formed in common, forming data lines D2 and D3 which are area lines. . For example,
In FIG. 4, the data line D3 is a non-volatile memory 5
One source 4 is formed, and the drain 3 of the nonvolatile memory 50 is formed.

The control gate electrode 14 of each single memory cell arranged in the same column is electrically connected to another single memory cell arranged in the same column, so that the control gate electrode line Has formed. For example, as shown in FIG. 4 and FIG. 2B, the control gate electrode 14 of the single memory cell 49 is electrically connected to other single memory cells 50 and 51 arranged in the same column to control the control. The gate electrode line CL1 is formed. Control gate electrode lines CL1,
CL2 and CL3 are provided for each row as shown in FIG. 2B.

[Operation of Flash Memory 1] Next, a method of using the flash memory 1 will be described with reference to FIGS. 5A and 5B. FIG. 5A shows an equivalent circuit 81 of the flash memory 1. FIG. 5B shows an example of a voltage applied at the time of writing and reading when the cell C22 is selected.

When writing to the cell C22, the data lines D1, D3 and D4 have a write inhibit voltage of 7V, the control gate electrode line CL2 has a voltage of 18V.
0 V is applied. Cells C21 to C23 in this state
Is shown in FIG. 1A. Control gate electrode line CL2
Is applied to each floating gate 12 of the cells C21 to C23, a voltage (approximately 12V in this case) corresponding to the coupling ratio between the well 2, the floating gate 12 and the control gate electrode 14 is applied. You. Thereby, each channel region 16 of the cells C21 to C23 is turned on. Here, since 0 V is applied to the data line D2, 0 V is transferred to the channel region 16 of the selected cell C22. Therefore, F
-Electron floating gate 1 by N tunneling
2 injected. As a result, the selected cell C22 enters the write state.

On the other hand, for the non-selected cells C21 and C23, 7V is transferred to the channel region 16 because the write inhibit voltage 7V is applied to the data lines D1 and D3. Therefore, since the voltage does not reach such a level as to cause FN tunneling, the non-selected cells C21 and C23 do not enter the write state.

Since 0 V is applied to each of the selection gate electrodes 22 of the non-selected cells C21 and C23, the channel region 17 is off. Therefore, the write inhibit voltage 7V transferred to the channel region 16 is maintained.

The other unselected cells C11 to C13, C
Regarding 31 to C33, since 0 V is applied to the control gate electrode lines CL1 and CL3, no writing state occurs. Thus, only the selected cell can be written. Next, reading will be described. When the cell C22 is set as the selected cell, V is applied to the control gate electrode line CL2 as a sense voltage.
s, 5V on select gate electrode line S2, data line D
2 is applied with 2 V and a sense amplifier is connected.
Further, the data lines D1 and D4 are opened, and the others are set to 0.
V is applied. FIG. 1C shows cells C21 to C23 in this state. Since the sense voltage Vs is applied to the control gate electrode line CL2, if the cell C22 is in the non-writing state, the channel region 16 of the selected cell C22 is turned on. On the other hand, select gate electrode line S
Since 5 V is applied to 2, the channel region 17 of the selected cell C22 is in the ON state. That is, both the channel regions 16 and 17 are turned on. Here, cell C22
2V to the drain 3 (data line D3) and the source 4
Since 0V is applied to (data line D2),
A current flows between the drain 3 (data line D3) and the source 4 (data line D2), which can be read by a sense amplifier connected to the data line D3.

On the other hand, when the cell C22 is in the write state, the channel region 16 of the selected cell C22 is turned off. Therefore, regardless of the state of the channel region 17 of the selected cell C22, the drain 3 (data line D
3), no current flows between the source 4 (data line D2).

In the non-selected cells C21 and C23, since the data lines D1 and D4 are in the open state, no current flows by mistake. Other unselected cell C
Regarding 11 to C13 and C31 to C33, since no sense voltage is applied to the control gate electrode lines CL1 and CL3, the channel region 16 is turned off, so that no current flows by mistake. In this way, only the information of the selected cell can be read.

For erasing, 0 V is applied to the control gate electrode line CL2, 18 V is applied to the well 2, and the others are kept open. This state is shown in FIG. 1B. By applying such a voltage, an electric field is generated in the direction opposite to that during writing, electrons are drawn back to the well 2 and erased collectively.

In this embodiment, each select gate electrode line is provided substantially in parallel with each data line. Therefore, the selection transistor can be provided without substantially increasing the cell area.

In this manner, information can be written to the flash memory having the virtual ground array structure by FN tunneling. This allows
It is possible to provide a semiconductor memory device in which power consumption is small and reliability is improved while reducing the cell area without requiring a contact.

[Method of Manufacturing Flash Memory 1] Next, a method of manufacturing the flash memory 1 will be described with reference to FIGS. First, as shown in FIG. 6A (plan view),
The field oxide layer 23 is formed by the LOCOS method to perform element isolation. FIG. 6B is a YY cross section of FIG. 6A,
FIG. 4 is a cross-sectional view of an element isolation region. The element isolation region is formed such that the field oxide layer 23 projects from the substrate surface. On the other hand, FIG. 6C is a cross-sectional view along the line XX of FIG. 6A and is a cross-sectional view of the element formation region.

Next, a 15 to 30 nm gate oxide film (SiO ₂ ) is formed on the entire surface by dilution oxidation, and a polysilicon layer is formed thereon by using a chemical vapor deposition (CVD) method. After oxidizing a silicon oxide film on the surface of the polysilicon layer, etching using a photoresist is performed, and as shown in FIG.
1, S2, S3 and a silicon oxide film 10 are formed.
FIG. 7B is a cross-sectional view taken along the line YY of FIG. 7A, which is a cross-sectional view of the element isolation region. FIG. 7C is a cross-sectional view taken along line XX of FIG. 7A.
FIG. 4 is a cross-sectional view of an element formation region.

Next, select gate electrode lines S1, S
2. A portion other than the gate oxide film under S3 is removed by etching, and a thin tunnel oxide film 8 is formed on the substrate surface by dilution oxidation (FIG. 7D). At this time, a silicon oxide film is also formed on the side walls of the select gate electrode lines S1, S2, S3.

A polysilicon layer is formed thereon by using the CVD method, and etching is performed using a photoresist, thereby forming a floating gate 12 as shown in FIG. 8A. FIG. 8B is a cross-sectional view of the element formation region, which is a cross section taken along line XX of FIG. 8A. Next, using the floating gate 12 and each select gate electrode line as a mask, an impurity is ion-implanted to form an n ⁺ layer. afterwards,
By performing the annealing, the data lines D1 to D4
Is formed (FIGS. 2 and 4).

Next, as shown in FIG. 9A, an interlayer insulating film 13 composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film is sequentially formed on the entire surface of the substrate. In this embodiment, the lowermost silicon oxide film is formed by dilution oxidation, the silicon nitride film is formed by low pressure CVD, and the uppermost silicon oxide film is formed by wet oxidation.

Next, as shown in FIG. 9B, a polysilicon layer is formed on the interlayer insulating film 13 by using the CVD method. Etching using a photoresist is performed to form an interlayer insulating film 13 and a control electrode 14. At this time, the floating gate 12 on the element isolation region is removed. Thus, a floating gate is formed for each memory cell (see FIGS. 2 to 4).

[Other Embodiment] FIG. 10 shows a flash memory 70 according to another embodiment. Flash memory 70
, The nonvolatile memory 71 is arranged in a virtual ground array structure.

In the nonvolatile memory 71, a drain 3 and a source 4, both of which are n ^{+ type} , are provided in a p-type silicon well 2 provided in a substrate. A channel region 16, an n-type region 72, and a channel region 17 are formed between the drain 3 and the source 4.

A gate oxide film 18 is provided above the channel region 17, and a select gate electrode 22 is provided above the gate oxide film 18. A tunnel oxide film 8 is provided above the channel region 16, and a floating gate 12 is provided above the tunnel oxide film 8. The surfaces of the floating gate 12 and the select gate electrode 22 are covered with an interlayer insulating film 13 serving as a third insulating film.
Covered with. Note that a control gate electrode 14 is provided above the floating gate 12 via an interlayer insulating film 13.

The structure of the select gate electrode line, control gate electrode line, and data line is the same as that of flash memory 1.

Since the method of using the flash memory 70 is the same as that of the flash memory 1, the description is omitted.

Next, a method of manufacturing the flash memory 70 will be described with reference to FIG. First, similarly to the flash memory 1, element isolation is performed by the LOCOS method (FIG. 1).
1A). A 20-nm silicon oxide film is formed on the entire surface by dilution oxidation, and a portion of the silicon oxide film that will be a tunnel oxide film is removed by etching using a photoresist. In this state, a 10-nm silicon oxide film is formed again by dilution oxidation. As a result, as shown in FIG. 11B, a 10 nm tunnel oxide film 8 and a 30 nm gate oxide film 18 are formed.

Next, after a polysilicon layer is formed by using the CVD method, etching is performed using a photoresist to form select gate electrode lines S1, S2, S3 and floating gate 12 (FIGS. 11C and 11D). .
FIG. 11C is a sectional view taken along line XX of FIG. 11D.

Next, using the floating gate 12 and each select gate electrode line as a mask, impurities are ion-implanted to form data lines D1 to D4, and then an interlayer insulating film 13 is formed on the entire surface of the substrate.

Next, the interlayer insulating film 1 is formed by the CVD method.
3, a polysilicon layer is formed, and etching is performed using a photoresist to form a control electrode line CL1.
To CL3 (see FIGS. 10A and 10B).

[Other Application Examples] In each of the above embodiments, the control gate electrode line is formed above the select gate electrode 22. However, since a voltage is applied to the select gate electrode, Even if 18 V is applied to the gate electrode line, the channel region 17 does not accidentally enter the conductive state.

In this embodiment, at the time of reading, a voltage for turning on the channel region 17 is applied to the select gate electrode line to which the memory cell desired to be read is connected. However, the present invention is not limited to this.
May be brought into a conductive state and read out in the same manner as in the prior art.

[0071]

According to the semiconductor memory device of the present invention,
A single memory cell is arranged in a matrix in a virtual ground array structure, and information can be written by FN tunneling. Therefore, a semiconductor memory device with low power consumption and improved reliability can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing an operation state of a flash memory 1;

FIG. 2 is a diagram showing a structure of a flash memory 1;

FIG. 3 is a diagram showing a structure of a flash memory 1;

FIG. 4 is a plan view showing the structure of the flash memory 1;

FIG. 5 is a diagram showing an example of an equivalent circuit 81 of the flash memory 1 and a voltage applied during operation.

FIG. 6 is a view showing a manufacturing process of the flash memory 1;

FIG. 7 is a view showing a manufacturing process of the flash memory 1;

FIG. 8 is a diagram showing a manufacturing process of the flash memory 1;

FIG. 9 is a diagram showing a manufacturing process of the flash memory 1;

FIG. 10 is a diagram showing a structure of a flash memory 70.

FIG. 11 is a diagram showing a manufacturing process of the flash memory 70.

FIG. 12 is a diagram showing a conventional flash memory having a virtual ground array structure. A is a sectional view of a main part, and B is a diagram showing an equivalent circuit 61.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 3 ... Drain 4 ... Source 8 ... Tunnel oxide film 10 ... Silicon oxide film 12 ... Floating gate 13 ... Interlayer insulating film 14 ... Control gate electrode 16 ... Channel region 17 channel region 18 gate oxide film 22 selection gate electrode D1 to D3 data line CL1 to CL3 control gate electrode line S1 to S3 selection gate electrode line

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/8247 G11C 17/00 H01L 27/115 H01L 29/788 H01L 29/792

Claims (6)

(57) [Claims] 1. A) a single memory cell comprising a1) to a10) and arranged in a matrix, a1) a first region, a2) a first circuit path formed adjacent to the first region. A3) a third region formed adjacent to the first circuit-formable region;
Region, a4) a second electric circuit formable area formed adjacent to the third area, a5) a second electric circuit formable area formed adjacent to the second electric circuit formable area
Region, a6) a first insulating film provided above the first electric circuit forming area, a7) a second insulating film provided above the second electric circuit forming area, a8) second insulating film A2) a second control electrode for the second electrical path forming area provided above the film, a9) a floating electrode provided above the first electrical path forming area via the first insulating film, a10) A third insulating film provided above the second control electrode and the floating electrode, a11) a third insulating film provided above the floating electrode via the third insulating film for the first electric path forming area. B) the second control electrode of a single memory cell arranged in the same row is electrically connected to form a second control electrode line; and C) the second control electrode is arranged in the same column. The first region of the single memory cell is electrically connected to form a first region line, and D) in the same column. A second region line of the single memory cell placed is electrically connected to form a second region line; and E) a first region line of the single memory cell arranged in an adjacent column. F) the first control electrode of a single memory cell arranged in the same column is electrically connected to form a first control electrode line, while the second region line is shared as a region line. A semiconductor memory device characterized by the above-mentioned. 2. A) A single memory cell comprising a1) to a10) and arranged in a matrix, a1) a first region, and a2) first and second memory cells sequentially formed adjacent to the first region. A3) a second circuit formed adjacent to the second circuit-forming area
Region, a4) a first insulating film provided above the first electric circuit forming area, a5) a second insulating film provided above the second electric circuit forming area, a6) second insulating film A7) a fourth insulating film provided above the second control electrode, a8) a second control electrode provided above the film for the second electrical path forming area, a8) a fourth insulating film provided above the second control electrode. A9) a third insulating film provided above the floating electrode, a10) a third insulating film provided above the floating electrode, and provided over the part where the electrical path can be formed; B) a first control electrode for a first electric circuit formable region provided above the floating type electrode via the insulating film of B), B) a second control electrode of a single memory cell arranged in the same row C) the first region of a single memory cell arranged in the same column is electrically connected to form a second control electrode line. To form a first region line. D) The second region of a single memory cell arranged in the same column is electrically connected to form a second region line. E) the first region line and the second region line of the single memory cell arranged in the adjacent column are shared as the region line; and F) the first control of the single memory cell arranged in the same column. The electrode is electrically connected to form a first control electrode line, wherein: 3. The semiconductor memory device according to claim 1, wherein the first region is a source, the second region is a drain, the second control electrode line is a select gate electrode line, The semiconductor memory device, wherein the electrode line is a control gate electrode line. 4. The method of using a semiconductor memory device according to claim 3, wherein: A) in writing, a1) applying a write voltage only to a control gate electrode line to which a memory cell to be written is connected; A2) a write inhibit voltage is applied to the region line to which the source of the memory cell not desired to be written is connected, and a3) the write inhibit voltage is applied to the first circuit-formable region of the memory cell desired to be written. A write-protection voltage cut-off voltage for preventing transfer is applied to a select gate electrode line of a memory cell to be written. B) When reading, b1) A control gate electrode to which the memory cell to be read is connected. Apply sense voltage only to the line, b2) Select gate electrode line connected to the memory cell you want to read Only to apply a voltage to make the second circuit path forming region conductive, and b3) provide a difference between the voltages applied to the source and the drain only in the memory cells desired to be read, and read whether or not a current flows. And a method of using the semiconductor memory device. 5. A method of manufacturing a semiconductor memory device by arranging a single memory cell manufactured by a process including the following steps a1) to a8) in a matrix, wherein: a1) a first conductive layer of a semiconductor substrate; Forming an insulating film having a thin film portion on the mold region , a2) forming a floating electrode above the thin film portion as a first insulating film, and forming a portion other than the thin film portion; Forming a second control electrode thereabove as a second insulating film. A3) Impurity is implanted and diffused by using the floating type electrode and the control electrode for forming an electric path as a mask, so that the floating type electrode and the second A third region of the second conductivity type is formed in the region of the first conductivity type between the control electrodes, and a second region of the second conductivity type is formed on a side opposed to the lower region of the second control electrode with the lower region interposed therebetween. To
Forming a first region of the second conductivity type on the side opposite to the lower region of the floating electrode; a4) forming a third insulating film above the floating electrode and the second control electrode; a5) The first insulating film is provided above the floating electrode via the third insulating film.
Forming a control electrode; B) for single memory cells arranged in the same column, the first regions are electrically connected and formed simultaneously; C) for single memory cells arranged in the same column. D) the second region is electrically connected and formed simultaneously; and D) for a single memory cell arranged in an adjacent column, the first region and the second region are shared and formed; For single memory cells arranged in a row, the first control electrodes are electrically connected and formed simultaneously; F) For single memory cells arranged in the same column, the second control electrode is electrically connected And simultaneously forming the semiconductor memory device. 6. A method for manufacturing a semiconductor memory device by arranging single memory cells manufactured in a process including the following steps a1) to a8) in a matrix, wherein: a1) a first memory cell in a semiconductor substrate; Forming a second insulating film on the surface of the conductive region; a2) forming a second control electrode on a portion of the second insulating film; a3) forming a fourth control electrode above the second control electrode; A4) forming a second conductive path forming area below the second control electrode as a second conductive path forming area; a4) forming a first conductive type area adjacent to the second conductive path forming area; Forming a first insulating film above the first electric circuit formable region using the semiconductor region as a first electric circuit formable region; a5) forming a first electric circuit through the first insulating film; A floating type electrode formed above the formable region, wherein the conductive type electrode is formed via the fourth insulating film. Forming a floating electrode covering a part of the electrode; a6) forming a third insulating film above the floating electrode; a7) using the floating electrode and the control electrode for forming a path as a mask, Is implanted and diffused into the first conductive type region on the floating type electrode side and the second conductive type first region and the second conductive type region.
Forming a second region of the second conductivity type in the region of the first conductivity type on the control electrode side; a8) forming a first region above the floating electrode through the third insulating film;
B) forming a first control electrode for an electric circuit formable region, B) for a single memory cell arranged in the same column, the first region is electrically connected and formed simultaneously, C) in the same column For a single memory cell arranged, the second region is electrically connected and formed simultaneously; D) For a single memory cell arranged in an adjacent column, the first region and the second region are E) For a single memory cell arranged in the same row, the first control electrode is electrically connected and formed simultaneously; F) For a single memory cell arranged in the same column, The method of manufacturing a semiconductor memory device, wherein the second control electrodes are electrically connected and formed at the same time.