JP3512206B2 - Nonvolatile storage device and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a flash EEPROM (Ele
ctrically Erasable Programmable Read On ly Memory)
Injecting and extracting charges on a single semiconductor substrate, etc.
The present invention relates to a non-volatile memory device in which non-volatile memory elements that store information by performing operations are arranged in a matrix along the row direction and the column direction.

[0002]

2. Description of the Related Art Conventionally, on a single semiconductor substrate, a plurality of nonvolatile memory elements for storing information by injecting and extracting charges are arranged and arranged in a matrix in a row direction and a column direction. Various non-volatile storage devices have been proposed. FIG. 9 shows a conventional nonvolatile memory element. As shown in FIG. 9, a conventional nonvolatile memory element includes a P-type silicon substrate 1, and an N ⁺ -type source region 2 and an N ⁺ -type drain region 3 formed on a surface layer of the silicon substrate 1 with a predetermined gap. And the ONO (o formed on the channel region 4 that is sandwiched between the source region 2 and the drain region 3
xide-nitride-oxide) film 5 and a gate 6 formed on the ONO film 5.

The ONO film 5 has a structure in which a nitride film 5b is sandwiched from above and below by oxide films 5a and 5c.
The bottom oxide film 5a has a function of tunneling electrons generated in the channel region 4, the nitride film 5b has a function of accumulating electrons tunneled through the bottom oxide film 5a, and the top oxide film 5c has a nitride film of electrons. Each of them has a function of keeping them in the 5b for a long time.

Now, with reference to FIGS. 9A to 9C, each operation of writing, reading, and erasing information of the nonvolatile memory element will be described. FIG (a) is an operation of when writing data, the (b) shows the operation when the information read, the (c) shows the operation when erasing information, respectively. When writing information, refer to FIG.
As shown in (a), the source region 2 is kept at a ground potential of 0 V, 9 V is applied to the drain region 3, and 1 is applied to the gate 6.
Apply 0V. Then, a high electric field is applied between the gate 6 and the drain region 3, and the source region 2 and the drain region 3
A saturated channel current flows between them. In the pinch off region near the drain region 3, electrons accelerated by the high electric field cause ionization (impact ionization), so-called channel hot electrons are generated,
The channel hot electrons are injected into the nitride film 5b of the ONO film 5.

When reading information, as shown in FIG. 9B, the source region 2 is set to the ground potential 0V,
1 V is applied to the drain region 3 and 3 V is applied to the gate 6. Then, if electrons are accumulated in the nitride film 5b of the ONO film 5, no channel is formed and no current flows between the drain region 3 and the source region 2. on the other hand,
Electrons accumulated in the nitride film 5b of the ONO film 5
Without it, the channel is formed, current flows between the drain region 3 a source region 2.

At the time of erasing information, as shown in FIG. 9C, the source region 2 is set to the ground potential 0V, 9V is applied to the drain region 3 and -6V is applied to the gate 6. Then, hot holes are generated near the drain region 3, and the hot holes are injected into the nitride film 5b of the ONO film 5. Therefore, with the accumulated electrons,
The injected holes are recombined and electrically neutralized.

[0007]

In the conventional nonvolatile memory element, since the hot electron injection method is adopted as shown in FIG. 9 (a) when writing information, the ONO film 5 is not formed. The electron injection efficiency is poor. This is because the source region 2-drain region 3
About 1% of the electrons flowing in between are only so-called hot. That is, most of the current used for writing is consumed between the source region 2 and the drain region 3. Therefore, in order to improve the injection efficiency of hot electrons, it is necessary to apply a high voltage between the gate 6 and the drain region 3. However, since the power consumption is too large, the booster circuit in one chip cannot be covered, and it is necessary to apply the write voltage by the external power supply circuit.

Therefore, in order to reduce the power consumption at the time of writing information, an FN (Fowler Nordheim) is used between the gate and the substrate.
A method of writing information by generating a tunnel current has been proposed. FIG. 10 shows an equivalent circuit diagram of a nonvolatile memory device that writes information by an FN tunnel current.
In this non-volatile memory device, as shown in FIG. 10, memory cells MC1, MC2, MC3, MC4 surrounded by dotted lines are arranged in a matrix in a row direction and a column direction, and each memory cell MC1, MC2, MC3, MC4 is , The nonvolatile memory elements MTr1, MTr2, MTr3, MTr shown in FIG.
It has a 1-cell / 1-transistor structure consisting of only four.

Nonvolatile memory elements MTr arranged in the row direction
The word line WL1 is connected to the gates of 1 and MTr2. Similarly, the word line WL2 is connected to the gates of the nonvolatile memory elements MTr3 and MTr4 arranged in the row direction. Nonvolatile storage elements M arranged in the column direction
The bit line BL1 is connected to the drains of Tr1 and MTr3. Similarly, the bit line BL2 is connected to the drains of the nonvolatile memory elements MTr2 and MTr4 arranged in the column direction.

Further, each nonvolatile memory element MTr1, MT
The source of r2, MTr3, MTr4 is the source line S
Commonly connected to L. Here, a method for writing information in the nonvolatile memory device will be described with reference to FIG. In this description, it is assumed that information is written in the memory cell MC1.

Word line WL2 and bit line B
L1 is set to ground potential 0V and the source line SL is opened (ope
n) state, write voltage 10V is applied to the word line WL1 connected to the memory cell MC1, and write inhibit voltage 6V is applied to the bit line BL2 connected to the non-selected memory cells MC2 and MC4. To do. Then, a high voltage is applied between the gate and the substrate of the nonvolatile memory element MTr1 in the memory cell MC1, and an FN current is generated. As a result, electrons are injected into the ONO film. Therefore, the information writing state is set.

However, according to the above nonvolatile memory device, although the power consumption can be reduced, the writing of information to the non-selected cells cannot be prohibited. In other words, although the memory cell MC 2 of unselected write inhibit voltage 6V is applied, since the source line SL is commonly connected, a cell current as indicated by the arrow flows. Therefore, the channel of the nonvolatile memory element MTr2 in the memory cell MC2 can not be charged to 6V. As a result, an FN current is generated between the gate of the nonvolatile memory element MTr2 and the substrate, and information is written.

FIG. 11 is a schematic sectional view of the nonvolatile memory device. In the figure, 7 is a nonvolatile memory element MTr.
1, a field oxide film that isolates MTr2 from each other, 8 is an interlayer insulating film that insulates the source line SL, the bit lines BL1 and BL2, and the word line WL1 from each other, and 9 protects the surface and prevents intrusion of contaminants from the outside. It is a passivation film to prevent.

As shown in FIG. 11, the nonvolatile memory device is
Since the adjacent nonvolatile memory elements MTr1 and MTr2 are element-isolated by the field oxide film 7, the element isolation region is large. Further, the source region 2 and the drain region 3 of each nonvolatile memory element MTr1, MTr2
The gate 6 has a source line SL and a bit line B.
Since L1 and BL2 and word line WL1 are in contact with each other, a margin for contact is required. That is, it cannot be applied to miniaturization.

In view of the above, the present invention provides a non-volatile memory device and a manufacturing method thereof which can sufficiently cover power consumption at the time of writing information with an internal booster circuit to prevent erroneous writing and can sufficiently cope with miniaturization. For the purpose of provision.

[0016]

According to a first aspect of the present invention, a single semiconductor substrate having a predetermined first conductivity type is used to inject or extract charges to obtain information. A non-volatile memory device in which a plurality of non-volatile memory elements for storing are arranged in a matrix along a row direction and a column direction, the non-volatile memory device comprising: Direction, a plurality of LOCOS insulating films thickly formed at predetermined intervals,
Directly below the COS insulating film and formed along the column direction, the channel stopper having the first conductivity type is joined to one side portion of each of the channel stoppers, and is formed along the column direction. It becomes the source region of the memory element,
And a source line shared by the nonvolatile memory elements arranged in the column direction, the first impurity diffusion layer having a second conductivity type opposite to the first conductivity type, and the channel stoppers. A non-volatile memory element that is joined to the other side portion, is formed along the column direction and at a predetermined distance from the first impurity diffusion layer, serves as a drain region of each non-volatile memory element, and is arranged in the column direction. The second impurity diffusion layer having the second conductivity type opposite to the first conductivity type, which is the drain line shared by the first impurity diffusion layer and the source region and the drain region of each nonvolatile memory element. A tunnel insulating film formed on each of the channel regions, which allows the charges generated in each channel region to pass therethrough, formed on each of the tunnel insulating films, and has passed through the tunnel insulating film. Charge storage layer for storing luggage, to the respective charge accumulating layer, is formed along the row direction, are arranged in the row direction has a word line shared nonvolatile memory element, between said semiconductor substrate A gate for injecting charges into the charge storage layer by generating an FN tunnel current is connected to the selected nonvolatile memory element.
Write voltage is applied to the selected word line and selected.
Between the gate of the nonvolatile memory element and the substrate
Means for generating a channel current, selected non-volatile memory element
The non-volatile memory is connected to the drain line connected to the child.
Generation of FN tunnel current between the gate of the storage element and the substrate
Non-volatile memory element that applies a predetermined voltage that allows
Non-selective non-volatile in the drain line connected to
FN tunnel current between gate and substrate of storage element
Means for applying a write inhibit voltage that can inhibit the occurrence of
Ravi and each source line are not connected to each other.
It includes means for applying a predetermined voltage to each spline .

[0017]

According to a second aspect of the present invention, the problem solving means is the first aspect.
A method for manufacturing a nonvolatile memory device according to claim 1, wherein a semiconductor substrate having a predetermined first conductivity type is formed,
A step of forming a plurality of dummy gates in a stripe shape along the column direction at a predetermined interval; a step of forming sidewalls on both sides of each dummy gate along the column direction; A step of implanting channel stop ions of the first conductivity type using the dummy gate as a mask, a plurality of LOCOS methods are provided on the surface layer of the semiconductor substrate at predetermined intervals in the column direction and in the row direction. And forming a channel stopper in a self-aligned manner directly below each LOCOS insulating film along the column direction, removing each sidewall and using each dummy gate as a mask. A step of implanting impurity ions having a second conductivity type opposite to that of the first conductivity type, and implanting ions of impurities having the second conductivity type After the step, a first impurity diffusion layer is formed on one side of each channel stopper and a second impurity diffusion layer is formed on the other side of each channel stopper in a self-aligned manner along the column direction by the LOCOS method. Step of removing each dummy gate to expose the surface of the semiconductor substrate in the element region and then forming a tunnel insulating film on the surface of the semiconductor substrate in the element region, accumulating charge on each tunnel insulating film A method of manufacturing a non-volatile memory device, comprising: a step of forming a film; and a step of forming a gate on each charge storage film along a row direction.

[0019]

In the means for solving the problems according to the first aspect, the impurity diffusion layers are formed and joined to the side portions of each channel stopper along the column direction, the gates are formed along the row direction, and the word line, Since the virtual ground array structure does not take contact with the source line and the drain line, the contact margin can be reduced, and the device can be sufficiently miniaturized. In addition, when writing information, the FN tunnel current
Therefore, the charge injection efficiency is improved,
Power is reduced, and power consumption during writing is increased by the internal booster circuit.
It becomes possible to fully cover. Therefore, the external power supply
You need only one.

Further , at the time of writing information, a high voltage is applied between the gate of the selected nonvolatile memory element and the substrate, and an FN tunnel current is generated from the substrate to the gate. As a result, charges pass through the tunnel insulating film and are injected into the charge storage film.

Since the source lines are not connected to each other and a predetermined voltage is applied to each source line, the non-selected non-volatile memory element sharing the word line with the selected non-volatile memory element. Then, the channel is surely charged by the write inhibit voltage applied to the drain line. Therefore, a current does not flow in the non-selected non-volatile memory element that shares the word line with the selected non-volatile memory element, and information is not erroneously written in the non-volatile memory element.

In the third aspect, the LOCOS oxidation is performed twice to form the channel stopper and the impurity diffusion layer directly under the LOCOS insulating film, so that the element isolation region can be made small and the channel length can be shortened. It can correspond to miniaturization. Also, sidewalls are formed on both sides of the dummy gate along the column direction, channel stop ions are implanted using the sidewalls and the dummy gate as masks, and then the sidewalls are removed, and impurity ions are used as masks with the dummy gates. Is being injected,
A margin for mask alignment for forming the buried impurity diffusion layer becomes unnecessary.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a block diagram showing an electrical configuration of a nonvolatile memory device according to an embodiment of the present invention. The electrical configuration of the nonvolatile memory device according to the present embodiment will be described with reference to FIG. It should be noted that in FIG. 1, an overline attached to a symbol representing a signal or the like indicates that it is of a negative logic, and the description of the overline is omitted in the specification.

The non-volatile memory device of this embodiment is a flash EEPROM, and as shown in FIG. 1, a memory array MA having a plurality of non-volatile memory elements for storing information in one chip, and a memory. Chip enable (CE), output enable (OE), provided around the peripheral array MA,
Write enable (WE) buffer 10, address buffer 11, I / O buffer 12, word line decoder 1
3, Y gate decoder 14, Y gate sense amplifier 1
5, the data load timing controller 16, erase, write timing control circuit 17, a negative high voltage generating circuit 18, a word line negative voltage Decorations over da 19, well driving circuit 20, the data pooling (DATA Polling) circuit 21, the page data Load latch circuit 22, data line negative voltage decoder 23, timer (I) 24, timer (II) 25, READY / BUS
It has a Y buffer 26, a write error prevention circuit 27, and a power supply voltage detection circuit 28.

In this non-volatile memory device, the CE signal, the OE signal, and the WE signal are all latched inside the EEPROM so that the internal timers 24 and 25 automatically rewrite old information to new information. Then, when writing information, the well driving circuit 20 and the data line negative voltage decoder 23 are driven with a negative high voltage, when erasing information, the word line decoder 13 is driven, and when reading information, the Y gate decoder 14 and the Y gate decoder 14 are driven. The Y gate sense amplifier 15 is driven.

The timers 24 and 25 calculate the rewriting time inside the EEPROM, and the data loading time automatically sets the erasing and writing times, respectively. In other words, the information is automatically rewritten inside the EEPROM by the timers 24 and 25, and it is not necessary to occupy the WE signal during the erasing and writing of information, so that the same timing as that of SRAM is apparently obtained. Information can be rewritten using.

The data pooling circuit 21, the page data load latch circuit 22 and the READY / BUSY buffer 26 are provided for indicating the end of rewriting of information. The READY / BUSY buffer 26 indicates that the chip is in the process of rewriting information. It has a hardware function of displaying in the output state of 1 pin, and displays the chip state by low level while rewriting information and by high impedance after rewriting. The data pooling circuit 21 has a software function which does not use an output pin for display or an external circuit in particular, and has a high impedance even when the outputs D ₀ to D ₄ are read during the information rewriting cycle. determination but output D ₂ has become a state capable of outputting, when I went to read the information of the last written address, during a write cycle if the actual information and inconsistency, the cycle is completed if they match To do.

The erroneous write prevention circuit 27 includes a noise canceller circuit of the WE, a WE internal signal / High fixed circuit, and a V _cc level judgment circuit so that the stored information is not accidentally rewritten by the malfunction of the internal booster circuit. It is built in. The noise canceller circuit of the WE is not sensitive to noise of a predetermined width or less on the write signal WE during reading or standby. The WE internal signal / High fixed circuit is READY, ST if each control pin (CE, OE, WE) is fixed to the ground or the power supply voltage V _cc.
POWER in any mode of ANDBY and WRITE
Enables ON / OFF. The V _cc level determination circuit is P
Ower ON / OFF at V _cc prohibits rewriting when less than the predetermined voltage.

FIG. 2 shows the structure of the memory array.
9A is a plan view showing a state in which the passivation film is peeled off, and FIG. 9B is a sectional view taken along the line I-I of FIG. The structure of the memory array MA will be described with reference to FIG. Memory array MA is as shown in FIG. 2, on a single P-type silicon substrate 30, a plurality of non-volatile storage elements to perform or injected electrons, the storage of information by or Eject MTr11, MTr12, MTr13 ，
The MTr 14 (enclosed by a dotted line in FIG. 2A) is in the row direction X.
And are arranged in a matrix along the column direction Y.

[0030] On the surface layer of the P-type silicon substrate 30, a plurality of LOCOS (l oc al oxidation ofsilicon) film 311,
312 and 313 are formed along the column direction Y and at predetermined intervals in the row direction. LOCOS films 311 and 3
12, 313 are made of SiO ₂ and have a film thickness of about 10
It is set relatively thick to around 000Å. Each LOC
Immediately below the OS insulating films 311, 312, 313, P-type channel stoppers 321, 322, 323 are formed along the column direction Y.

Channel stoppers 3 2 1, 3 2 2, 3 2
First N ⁺ -type buried impurity diffusion layers 331 and 332 are formed along the column direction Y and joined to one side (right side in the drawing) of No. 3 of FIG. That is, the first N ⁺ type buried impurity diffusion layers 331 and 332 are formed in the respective nonvolatile memory elements MTr1.
1, the non-volatile memory elements M which become the source regions of MTr12, MTr13, MTr14 and are arranged in the column direction Y.
The source lines SL1 and SL2 are shared by Tr11, MTr13 and MTr12, MTr14.
Further, on the other side (left side in the figure) of each channel stopper 3 21, 3 2 2, 3 2 3, second N ⁺ type buried impurity diffusion layers 341, 342 are arranged along the column direction Y and The first N-type buried impurity diffusion layers 331 and 332 are formed at predetermined intervals and are joined to each other. That is, the second N ⁺ type buried impurity diffusion layers 341 and 342 serve as drain regions of the nonvolatile memory elements MTr11, MTr12, MTr13, MTr14, and are arranged in the column direction Y. And MTr12, M
The drain lines DL1 and DL2 are shared by Tr14.

Nonvolatile storage elements MT arranged in the row direction X
Each channel region 351 generated so as to be sandwiched between the source region and the drain region of r11 and MTr12.
A tunnel oxide film 361 that allows electrons generated in the channel regions 351 and 352 to pass therethrough is formed on the line 352.
362 is formed. Although not shown, the nonvolatile memory elements MTr1 arranged in the row direction X are similarly provided.
3, a tunnel oxide film is formed on each channel region formed so as to be sandwiched between the source region and the drain region of MTr14.

The tunnel oxide film is made of SiO ₂ and has a thickness of about 20Å so that electrons can pass therethrough.
It is set to be extremely thin. Then, the tunnel oxide film 36 of the nonvolatile memory elements MTr11, MTr12.
On the film thickness of the tunnel oxide film including 1,362, a nitride film 37 for accumulating electrons that have passed through the tunnel insulating film is formed.

The nitride film 37 is made of Si ₃ N ₄ , and its film thickness is set to about 80 Å in consideration of charge retention characteristics and the like. A block oxide film 38 is formed on the nitride film 37 for confining the electrons injected into the nitride film 37 for a long time. The block oxide film 38 is
It is made of SiO ₂ , and its film thickness is set to about 50 Å so that electrons can be effectively blocked. Gates 391 and 392 are formed on the block oxide film 38 along the row direction X.

The gates 391 and 392 are made of a conductive material such as polysilicon, which is doped with phosphorus at a high concentration to reduce its resistance, and is arranged in the row direction X.
The word lines WL1 and WL2 are shared by Tr11 and MTr12 and MTr13 and MTr14.
The nonvolatile memory element MTr1 adjacent to the column direction Y
1, MTr13, MTr12, MTr14 are provided in the boundary region (indicated by a cross in FIG. 2B), the nonvolatile memory elements MTr11, MTr13 and MTr12, MT.
Channel stop ions are implanted for element isolation of r14.

In the above structure, each channel stopper 3
N ⁺ -type buried impurity diffusion layers 331, 332 and 341, 342 are formed and joined along the column direction on the side portions of 2, 1, 3 2, 2, 3 23, and gates 391, 392 are arranged in the row direction. Formed, word lines WL1, WL2, source line S
L1 and SL2 and drain lines DL1 and DL2 are not contacted.
Since it has an (array) structure, the contact margin can be reduced and it is possible to sufficiently miniaturize.

FIG. 3 is an equivalent circuit diagram of the memory array.
The electrical configuration of the memory array MA will be described with reference to FIG. The memory array MA is as shown in FIG.
Memory cells MC11, MC12, MC1 surrounded by dotted lines
3, MC14 are arranged in a matrix, and each memory cell MC11, MC12, MC13, MC14 has 1
Nonvolatile memory elements MTr11, MTr12, MTr
It has a one-cell / one-transistor structure composed of only 13 and MTr14.

Nonvolatile memory elements MTr arranged in the row direction
The word line WL1 is connected to the gates of the memory cells 11 and MTr12, and the word line W1 is connected to the gates of the nonvolatile memory elements MTr13 and MTr14 arranged in the row direction.
L2 is connected. The source line SL1 is connected to the sources of the nonvolatile memory elements MTr11 and MTr13 arranged in the column direction, and the drain line DL1 is connected to the drain. The sources of the nonvolatile memory elements MTr12 and MTr14 arranged in the column direction are
The source line SL2 is connected, and the drain is connected to the drain line DL2.

Now, with reference mainly to FIG. 2 and Table 1, information writing, erasing and reading operations of information in the nonvolatile memory device will be described. In Table 1, it is assumed that the memory cell MC11 is selected.

[0040]

[Table 1]

<Write (WRITE)> Information is written by driving the well drive circuit 20 and the data line negative voltage decoder 23 shown in FIG. That is, the word line WL2 is set to the ground potential 0V, the source line SL2 is opened, and the write inhibit voltage 6V is applied to the drain line DL2.
Memory cell MC for writing information by applying
In order to select 11, the source line SL1 and the drain line DL1 are set to the ground potential 0V, and the word line WL1
Is applied to 10V.

Then, as shown in FIG. 4, the non-volatile memory element MTr11 in the selected memory cell MC11.
Then, a high voltage is applied between the gate 391 and the substrate 30, and an FN tunnel current is generated from the substrate 30 toward the gate 391. As a result, electrons tunnel through the tunnel oxide film 361 and are injected into the nitride film 37, and the state of writing information “1” is obtained.

On the other hand, in the non-volatile memory element of the non-selected memory cell, without FN tunnel current occurs between the gate and the substrate, does not electrons are injected into the nitride film. At this time, the erroneous write prevention circuit 27 shown in FIG. 1 makes the source lines SL1 and SL2 unconnected to each other and applies a predetermined voltage to each of the source lines SL1 and SL2, so that they are connected to the word line WL1. In the non-volatile memory element MTr12 in the memory cell MC12 being operated, the write inhibit voltage 6 applied to the drain line DL2 is applied.
V ensures that the channel is charged. as a result,
Since the cell current does not flow in the memory cell MC2, information is not accidentally written in the nonvolatile memory element MTr12.

The gate voltage required for conducting between the source and the drain of the nonvolatile memory element changes between the state in which the electone is accumulated in the nitride film and the state in which it is not accumulated. That is, the source of the nonvolatile memory element
The threshold voltage V _TH for conducting the drain has a high threshold voltage V1 when electrons are injected into the nitride film, and has a low threshold voltage V2 when electrons have not been injected. Thus, by setting the threshold voltage V _TH to two types, binary data of “1” or “0” can be stored in the nonvolatile memory element. <Erase> Information is erased by driving the word line decoder 13 shown in FIG. That is, the word line WL2 is set to the ground potential 0V, the source line SL2 and the drain line DL2 are left open, and the source line SL1 and the drain line DL1 are left open to select the memory cell MC11 for erasing information. -10V is applied to the line WL1.

Then, as shown in FIG. 5, the non-volatile memory element MTr11 in the selected memory cell MC11.
Then, a bias reverse to that at the time of writing is applied between the gate 391 and the substrate 30, and an FN tunnel current is generated from the gate 391 toward the substrate 30. As a result, the electrons accumulated in the nitride film 37 tunnel through the tunnel oxide film 361 and flow into the substrate 30, and the electrons are extracted from the nitride film 37. Therefore, the information is erased, that is, the information "0" is written.

As described above, since the rewriting of information is performed by the FN tunnel current, the electron injection efficiency is improved, the power consumption is reduced, and the power consumption at the time of rewriting can be sufficiently covered by the internal booster circuit. Becomes
Therefore, since the power supply from the external power supply may be 5 V, only one external power supply is required. <Read (READ)> Information is read by the Y gate decoder 14 and the Y gate sense amplifier 1 shown in FIG.
And 5 are driven. That is, the word line WL2 is set to the ground potential 0V, the source line SL2 and the drain line DL2 are left open, and the source line SL1 is set to the ground potential 0V and the drain line DL1 is set to 1V in order to select the memory cell MC11 to be read. Then, the sense voltage 2V is applied to the word line WL1.

Then, as shown in FIG. 6A, if electrons are accumulated in the nitride film 37 of the nonvolatile memory element MTr11 in the memory cell MC11, the gate 3
The positive charge of 91 is canceled by the electrons accumulated in the nitride film 37, and the influence of this positive charge is the substrate 30.
Does not reach the surface of. Therefore, no channel is formed in the nonvolatile memory element MTr11, and no current flows.
On the other hand, as shown in FIG. 6B, the nonvolatile memory element MT
If no electrons are accumulated in the nitride film 37 of r11, the positive charge of the gate 391 extends to the surface of the substrate 30, a channel is formed in the nonvolatile memory element MTr11, and a current flows. In this state, the Y gate decoder 14
By sensing with the Y gate sense amplifier 15, the information stored in the non-volatile memory element MTr11 is read.

By the way, the sense voltage is an intermediate voltage between two kinds of V1 and V2 of the threshold voltage V _TH .
Therefore, when this sense voltage is applied, conduction / non-conduction of the nonvolatile memory element is determined by whether or not electrons are accumulated in the ONO film. 7 and 8 are schematic cross-sectional views showing a method of manufacturing the nonvolatile memory device in the order of steps. A method of manufacturing the nonvolatile memory device will be described with reference to FIGS. 7 and 8. 7 and 8, only one nonvolatile memory element is shown for convenience of description.

First, a dummy gate is formed. That is, as shown in FIG. 7A, the P-type silicon substrate 30 is thermally oxidized at about 900 to 1000 ° C. to form a pad oxide film 40 of about 1000 Å, and then the CVD is performed.
(C h emical Vapor Deposition) nitride film 41 is formed about 1000Å under the law, further oxide film serving as an etching stopper in the subsequent step by thermal oxidation (hereinafter, referred to as "etching stopper") 42 to about 1000Å is formed.

Then, as shown in FIG. 7B, a resist pattern (not shown) is formed on the etching stopper 42, and the etching stopper 42 and the nitride film 41 are etched using this resist as a mask to form a dummy gate. The stripes are formed along the column direction. When the dummy gate forming process is completed, a LOCOS film and a channel stopper are formed. That is, as shown in FIG. 7C, the silicon oxide film 43 is deposited on the entire surface by the CVD method. Subsequently, the silicon oxide film 43 is etched back until the upper surface of the etching stopper 42 is exposed, and the sidewalls 44, 42 are formed on both sides (left and right in the figure) of the etching stopper 42 and the nitride film 41.
45 is deposited along the column direction.

Next, as shown in FIG. 7D, the sidewalls 44 and 45, the etching stopper 42, and the nitride film 41 are used as masks for implantation and the like, which is a P-type impurity such as boron. Implant channel stop ions. Then, as shown in FIG. 7E, the silicon substrate 30 is exposed to water vapor (H ₂
O) LOCOS oxidation is performed in an atmosphere for about 6 to 7 hours, and a LOCOS film 31 of about 10000 Å is formed along the column direction on the surface of the silicon substrate 30 not covered with the sidewalls 44 and 45, the etching stopper 42 and the nitride film 41. To grow. At this time, channel stoppers 32 are formed immediately below the LOCOS film 31 along the column direction.

When the process of forming the LOCOS film and the channel stopper is completed, a buried impurity diffusion layer is formed. That is, as shown in FIG. 7F, after removing the sidewalls 44 and 45, N is formed by implantation using the etching stopper 42 and the nitride film 41 as a mask.
Ions such as As, which is a type impurity, are implanted.
Then, as shown in FIG. 8A, LOCOS oxidation is performed again to form N ⁺ type buried impurity diffusion layers 33 and 34 on both sides of the channel stopper 32 in the column direction.

When the step of forming the buried impurity diffusion layer is completed, a tunnel oxide film and a charge storage film are formed. That is, as shown in FIG. 8B, the etching stopper 4
2. The nitride film 41 and the pad oxide film 40 are removed to expose the surface of the silicon substrate 30 in the element region. And
As shown in FIG. 8C, an extremely thin tunnel oxide film 36 of about 20 Å is formed on the silicon substrate 30 with the exposed element region at about 900 to 1000 ° C. Continuing, C
A VD method is used to deposit a nitride film 37 on the entire surface by about 80Å, and a CVD method is used to deposit a block oxide film 38 on the nitride film 37 by about 50Å.

When the steps of forming the tunnel oxide film and the charge storage film are completed, the gate is formed. That is, as shown in FIG. 8 (d), LPCVD (Low Pressure C h em
Polysilicon is deposited on the entire surface by the ical vapor deposition method, and the conductive material such as phosphorus is doped in high concentration to the polysilicon. Subsequently, the gate 39 is formed by patterning polysilicon in a stripe shape along the row direction. Then, in the region indicated by X in FIG. 2B, channel stop ions are implanted using the LOCOS film 31 as a mask, and the nonvolatile memory elements MTr11, MTr13 and MTr12, MTr1 adjacent in the column direction are implanted.
Element 4 is separated.

When the gate forming process is completed, a passivation film is formed. That is, as shown in FIG. 8E, a nitride film (Si ₃ N ₄ ) is formed on the entire surface by the CVD method.
An insulating material such as is deposited to form the passivation film 46. In this way, LOCOS oxidation is performed twice, and LO
Since the channel stopper 32 and the buried impurity diffusion layers 33 and 34 are formed immediately below the COS film 31, the element isolation region can be made small and the channel length can be shortened. Therefore, miniaturization can be sufficiently dealt with.

Further, sidewalls 44 and 45 are formed on both sides of the etching stopper 42 and the nitride film 41 along the column direction, and channel stop ions are formed by using the sidewalls 44 and 45, the etching stopper 42 and the nitride film 41 as a mask. After injection, the sidewall 44,
45 is removed, and the etching stopper 42 and the nitride film 4 are removed.
Since impurity ions are implanted using 1 as a mask,
A margin for mask alignment for forming the buried impurity diffusion layers 33 and 34 becomes unnecessary, which also contributes to miniaturization.

The present invention is not limited to the above embodiments, and it goes without saying that many modifications and changes can be made within the scope of the present invention. For example, in the above embodiment, the case where the P-type silicon substrate is used is described, but the N-type silicon substrate may be used. Further, the charge storage film may have a structure including a floating gate.

[0058]

As is apparent from the above description, according to the first aspect of the present invention, since the structure can be such that the word line, the source line and the drain line are not contacted with each other, the contact margin can be increased and the device can be sufficiently miniaturized. it can. Further, since the writing of information is performed by the FN tunnel current, the charge injection efficiency is improved, the power consumption is reduced, and the power consumption at the time of writing can be sufficiently covered by the internal booster circuit. Therefore, a single external power supply is sufficient. Furthermore , since the source lines are not connected to each other and a predetermined voltage is applied to each source line,
In the non-selected non-volatile memory element that shares the word line with the selected non-volatile memory element, the channel is reliably charged by the write inhibit voltage applied to the drain line. Therefore, a current does not flow in the non-selected non-volatile memory element that shares the word line with the selected non-volatile memory element, and information is not erroneously written in the non-volatile memory element.

In the second aspect , the LOCOS oxidation is performed twice to form the channel stopper and the impurity diffusion layer immediately below the LOCOS insulating film, so that the element isolation region can be made small and the channel length can be shortened. It can correspond to miniaturization. Also, sidewalls are formed on both sides of the dummy gate along the column direction, channel stop ions are implanted using the sidewalls and the dummy gate as masks, and then the sidewalls are removed, and impurity ions are used as masks with the dummy gates. Is being injected,
A margin for mask alignment for forming the buried impurity diffusion layer becomes unnecessary, which also contributes to miniaturization.

[Brief description of drawings]

FIG. 1 is a block diagram showing an electrical configuration of a nonvolatile memory device according to an embodiment of the present invention.

FIG. 2 shows the structure of a memory array, which is shown in FIG.
Is a plan view showing a state in which the passivation film is peeled off, and FIG. 4B is a sectional view taken along line I-I of FIG.

FIG. 3 is an equivalent circuit diagram of a memory array.

FIG. 4 is a diagram schematically showing an operation of a nonvolatile memory element at the time of writing information.

FIG. 5 is a diagram schematically showing the operation of the nonvolatile memory element when erasing information.

FIG. 6 is a diagram schematically showing the operation of the nonvolatile memory element at the time of reading information.

FIG. 7 is a schematic cross-sectional view showing the method of manufacturing the nonvolatile memory device in the order of steps.

FIG. 8 is a schematic cross-sectional view showing the method of manufacturing the nonvolatile memory element following step in FIG. 7 in order of steps.

FIG. 9 is a diagram schematically showing operations of writing, reading and erasing information in a conventional nonvolatile memory element,
FIG. 7A shows the operation at the time of writing information, and FIG.
Shows the operation at the time of reading information, and FIG. 7C shows the operation at the time of erasing information.

FIG. 10 is an equivalent circuit diagram of a nonvolatile memory device according to a prior art.

FIG. 11 is a schematic sectional view of the same.

[Explanation of symbols]

MA memory array 13 word line decoder 20 well drive circuit 23 data line negative voltage decoder 27 erroneous write prevention circuit 30 P-type silicon substrate MTr11, MTr12, MTr13, MTr14 non-volatile memory element 31, 311, 312, 313 LOCOS film 32, 321, 322, 323 Channel stoppers 33, 331, 332 First N ⁺ type buried impurity diffusion layers 34, 341, 342 Second N ⁺ type buried impurity diffusion layers 351, 352 Channel regions 361, 362 Tunnel oxide film 37 Nitride film 38 Block oxide film 391, 392 Gate word line WL1, WL2 Source line SL1, SL2 Drain line DL1, DL2 40 Pad oxide film 41 Nitride film 42 Etching stopper 44, 45 Side wall

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (2)

(57) [Claims] 1. A plurality of nonvolatile memory elements for storing information by injecting and extracting charges on a single semiconductor substrate having a predetermined first conductivity type are arranged in rows and columns. A non-volatile memory device arranged in a matrix along a direction, the plurality of LOCOS being formed thick on a surface layer of the semiconductor substrate along a column direction at predetermined intervals in a row direction.
An insulating film, a channel stopper formed directly below each of the LOCOS insulating films in the column direction and having the first conductivity type, and bonded to one side portion of each of the channel stoppers,
Opposite to the first conductivity type, the first conductivity type is formed along the column direction and serves as a source region of each non-volatile memory element and serves as a source line shared by the non-volatile memory elements arranged in the column direction. A first impurity diffusion layer having a conductivity type of 2 is joined to the other side portion of each channel stopper, and
The drain line is formed along the column direction and at a predetermined distance from the first impurity diffusion layer to serve as a drain region of each nonvolatile memory element, and also serves as a drain line shared by the nonvolatile memory elements arranged in the column direction. A second impurity diffusion layer having a second conductivity type opposite to the first conductivity type, and on each channel region formed so as to be sandwiched between the source region and the drain region of each nonvolatile memory element. A tunnel insulating film that is formed and allows the charges generated in each channel region to pass therethrough, a charge storage layer that is formed on each of the tunnel insulating films and stores the charges that have passed through the tunnel insulating film, and each of the charge storage layers, The word lines are formed along the row direction and shared by the nonvolatile memory elements arranged in the row direction, and generate a FN tunnel current with the semiconductor substrate. Wadora connected to the gate, the selected nonvolatile memory element to inject the charge to the charge storage layer by
The write voltage is applied to the IN and the selected non-volatile
Generation of FN tunnel current between the gate of the storage element and the substrate
Means, drain connected to the selected non-volatile storage element
In the line, between the gate of the nonvolatile memory element and the substrate
Apply a predetermined voltage that can generate an FN tunnel current at
Drain driver connected to non-selected non-volatile storage element
In the non-selected non-volatile memory element, the gate and substrate
Write inhibit that can inhibit the generation of FN tunnel current between
The means for applying the stop voltage and the source lines are not connected to each other, and
A non-volatile memory device comprising means for applying a predetermined voltage to each memory. 2. A method for manufacturing a non-volatile memory device according to claim 1, wherein a plurality of dummy gates are provided along a column direction and on a semiconductor substrate having a predetermined first conductivity type. A step of forming a stripe shape with a space between them, a step of forming sidewalls on both sides of each dummy gate along the column direction, each sidewall and dummy gate as a mask,
Implanting channel stop ions of the first conductivity type, a plurality of LOCs are formed on the surface layer of the semiconductor substrate along the column direction and at predetermined intervals in the row direction by the LOCOS method.
A step of forming a thick OS insulating film and forming a channel stopper directly below each LOCOS insulating film in a self-aligned manner along the column direction. Each sidewall is removed, and each dummy gate is used as a mask. The step of implanting impurity ions having a second conductivity type opposite to that of the second conductivity type, and the step of implanting the ions having impurities having the second conductivity type, followed by LOCOS method at one side of each channel stopper. A step of forming a first impurity diffusion layer on the other side of each channel stopper in a self-aligned manner along the column direction, and removing each dummy gate to form a semiconductor substrate in the element region. A step of forming a tunnel insulating film on the surface of the semiconductor substrate in the element region after exposing the surface of the device, a step of forming a charge storage film on each tunnel insulating film, and A method of manufacturing a non-volatile memory device, comprising the step of forming a gate on each charge storage film along a row direction.