JPS616858A - Semiconductor memory storage and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase memory-cell reading voltage, and to reduce a soft-error rate by forming an insulator region on the bottom of an MIS type field-effect transistor and shaping a storage capacitance element to a section nearer to the surface than an insulating film shaped to the surface of a semiconductor substrate. CONSTITUTION:An MIS transistor constituting a memory cell is composed of a word line electrode 15, a first gate oxide film 11, an islant silicon region 34, a source diffusion region 16, and a drain diffusion region 17, and an insulator region 33 is formed to the bottom of the MIS transistor. A storage capacitance element is constituted by a storage-capacitance element lower electrode 32, a storage-capacitance element insulating film 35 and the cell plate electrode 15, and shaped to a section nearer to the surface than insulating films - that is, a field oxide film 23 and the first gate oxide film 11 - formed to the surface of an silicon substrate 10, and the MIS transistor and the storage capacitance element are connected through a storage-capacitance element contact window 31.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to the structure of semiconductor integrated circuits (hereinafter referred to as LSI), particularly high-density, high-integration LSI storage devices.

Structures of conventional floor examples and their problems Recently, LSIs have become more and more densely packed and high-performance.
This tendency is remarkable in dynamic memories (hereinafter referred to as DRAMs) whose constituent elements are transistors (S).

One of the problems in high-density DRAMs is how to secure read signal voltages from memory cells. FIG. 1 shows a circuit diagram around the DRAM memory section. In this circuit, the memory 7 read signal voltage V immediately before amplification is
sig is available (for example, Nikkei Electronics 19
(See July 18, 1983 issue, page 177).

Here, Cs is the storage capacitance of the storage capacitance element 2, Co is the parasitic capacitance 5 of the data line, Vs is the signal voltage stored in the storage capacitance element 2, and η is a coefficient (approximately 0.5). LSI
When the density is increased, the storage capacitor element 2 is also reduced in size, causing a decrease in the storage capacitance Os. For this reason, proposals have been made to obtain a large storage capacity Os even in the storage capacitance element 2 having a small area.

FIG. 2 shows that a groove is dug in the silicon substrate 1o and a first
DR with a conventional structure in which after forming the gale oxide film 11, the buried polycrystalline silicon 12 is buried in the trench.
FIG. 3 is a cross-sectional view of a λM memory cell portion. In the structure shown in FIG. 2, the storage capacitance Os is the buried polycrystalline silicon 12
and a MIS capacitor and a pn junction capacitor formed between the cell plate electrode 13 and the silicon substrate 10.

Still, the parasitic capacitance 5 of the data line is constituted by the capacitance that the data line electrode 19 and the drain diffusion region 17 have with respect to the cell plate electrode 13 and the silicon substrate 10;
This is mainly due to the pn junction capacitance formed between the two.

As mentioned above, the read signal voltage from the DRAM memory cell is dependent on the storage capacitance GS and the data line parasitic capacity 1" (On
However, if the storage capacitance is increased only by the conventional method, the parasitic capacitance CD of the data line increases as the number of memory cells per data line increases, leading to a drop in the read signal voltage. There are limits to how much capacity can be accommodated.

From the viewpoint of soft error rate, if we look at the conventional DRAM memory shown in FIG. There is a high possibility that electron-hole pairs generated by the incident α rays are captured in the memory cell diffusion region 2o and cause a rough 1 to error.

However, the inventor of the present invention has discovered that MI
By forming an insulator region at the bottom of the S-type field effect transistor and forming a storage capacitor element on the surface of the semiconductor substrate rather than an insulating film, the read voltage of the DRAM memory cell/v7 is increased. At the same time, we discovered a method to reduce the soft error rate and developed DRA.
It has been found that it is possible to achieve higher density and larger capacity of M.

Purpose of the Invention In view of these conventional problems, the present invention provides a semiconductor memory device that increases the read signal voltage of a DRAM memory cell by reducing the parasitic capacitance of the data line, and is suitable for higher density and larger capacity. The purpose is to provide a method for producing the same.

Structure of the Invention The present invention provides a semiconductor memory device including an MIS field effect transistor and a storage capacitor, in which the source or drain of the MIS field effect transistor is connected to one electrode of the storage capacitor. Said MIS
forming an insulator region at the bottom of the type field effect transistor;
By forming the storage capacitance element on the surface of the semiconductor substrate rather than the insulating film, it is possible to reduce the parasitic capacitance of the data line and increase the read signal voltage of the memory cell, while at the same time reducing the soft error rate. It is therefore possible to provide a semiconductor memory device and a method for manufacturing the same that also realizes a reduction in .

DESCRIPTION OF EMBODIMENTS FIG. 3 is a plan view of a memory cell portion of a DRAM according to an embodiment of the present invention, and FIG. 4 is a plane view taken along line A-A' in FIG.
6 is a sectional view taken along B-B' in FIG. 3.
FIG.

As shown in Figure 4, the MIS (MIS) that constitutes the memory cell
The transistor has a word line electrode 15 and a first gate oxide film 11.
, an island silicon region 34, a source diffusion region 16, and a drain diffusion region 17, and an insulator region 33 is formed at the bottom thereof. Further, the storage capacitor element is composed of a storage capacitor element lower electrode 32, a storage capacitor element insulating film 36, and a cell plate electrode 15, and an insulating film formed on the surface of the silicon substrate 10, that is, a field oxide film 23 and the first gate oxide film 11.
Connected throughout.

Next, Fig. 5(a) to (f'l) and Fig. 7(a) to (f'l)
A method for manufacturing a semiconductor memory device according to an embodiment of the present invention will be described using the manufacturing process cross-sectional view shown in e).

As shown in FIG. 5(2L) and FIG. 7(a), a field oxide film 23 is formed in the silicon substrate 10.

Note that it is assumed here that the silicon substrate 1o is of P type. Next, as shown in FIG. 5(1)) and FIG. 7(b), an insulator region 33 is formed by implanting oxygen ions at a dose of IXlo(m2) at an acceleration voltage of 80 Kv. It goes without saying that the accelerating voltage and dose of ion implantation may be varied to control the depth and thickness of the insulator region 33. Also, nitrogen ions may be used instead of oxygen ions. Through the above steps, the island silicon region 34 is formed.

Next, a first gate oxide film 11 is formed, and the word line electrode 1
5, a source diffusion region 16 and a drain diffusion region 17 are formed, for example, by implanting arsenic ions at a dose of 3×1o Crn at an acceleration voltage of 40 Kv. After that, an interlayer insulating film 14 is deposited, and then a storage capacitor element contact window 31 is opened. This state is shown in FIG. 5(0) and FIG. 7(C).

Next, a polycrystalline silicon film that will become the storage capacitor element lower electrode 32 is deposited to form a desired pattern.

It is desirable for the polycrystalline silicon film to contain N-type impurities in order to simplify the process. Next, the surface of the storage capacitor element lower electrode 32 is oxidized, and the storage capacitor element insulating film 3
6 is formed and born. This is shown in Figures 5(d) and 7(d).
Shown below.

Next, a polycrystalline silicon film that will become the cell plate electrode 13 is deposited. It is desirable for this polycrystalline silicon film to also contain N-type impurities in order to simplify the process. Next, Figure 5 (
el) and FIG. 7(e), a desired pattern of the cell plate electrode 13 is formed. Next, see Figure 5 (
0, a second interlayer insulating film 25 is deposited and a data line contact window 3Q is opened. Thereafter, by forming data lines, the structures shown in FIGS. 4 and 6 are obtained. Although FIGS. 4 and 6 show an example in which an island silicon region remains on the lower surface of the source and drain diffusion regions 16 and 1γ, the insulator region 33 is the source.

It goes without saying that it may be in contact with the drain diffusion regions 16 and 17.

According to the above embodiment, by forming an insulator region at the bottom of the MIS field effect transistor, it is possible to reduce the parasitic capacitance of the data line and increase the memory cell read voltage.

In addition, by forming the storage capacitor element on the surface of the semiconductor substrate rather than the insulating film formed on the surface of the semiconductor substrate, it is possible to realize a memory cell that is less susceptible to soft errors caused by electron-hole arrays generated in the semiconductor substrate by alpha rays, etc. It became possible.

In the embodiments described above, the insulator region 33 was formed by implanting oxygen or nitrogen ions, but it can also be realized by other methods, which will be shown as a second embodiment. 8th
What is shown in the figure is a cross-sectional view of the memory cell portion in the second embodiment, showing a cross section taken along line BB' in the plan view of the memory cell portion shown in FIG. The manufacturing process for the cross section shown in FIG. 8 will be explained using the manufacturing process cross-sectional views shown in FIGS. 9(L) to (d). First, as shown in FIG. 9(&), a groove is formed in the silicon substrate 1o, and a base oxide film 41 and a silicon nitride film 42 are formed on the surface other than the bottom of the groove by a well-known method.
form. Next, as shown in FIG. 9(b), when the silicon substrate 1o is etched using an isotropic etching solution, the cavity at the bottom of the groove 43 is enlarged. Next, when oxidation is carried out, the portion where the silicon nitride film 42 is deposited is not oxidized, but the exposed surface portion of the silicon substrate 10 is oxidized to form an insulator region 33, and an island silicon region. 3
4 is formed. This is shown in FIG. 9(C).

Next, for example, polycrystalline silicon or a GVD oxide film is buried to a thickness of 40 to flatten the surface. This is shown in FIG. 9(li).

Thereafter, the structure shown in FIG. 8 is obtained by the steps shown in the first embodiment.

In the second embodiment, since the insulator region is formed using a normal oxidation method, the high dose implantation of oxygen ions shown in the first embodiment is not necessary, and the throughput of the manufacturing process is increased. It is possible to obtain the effects shown in the first embodiment without reducing the performance.

Effects of the Invention As described above, the present invention makes it possible to reduce the parasitic capacitance of the data line and increase the memory cell read voltage by forming an insulator region at the bottom of the MIS type field effect transistor. Furthermore, by forming the storage capacitance element on the surface of the insulating film formed on the surface of the semiconductor substrate, it is possible to realize an excellent semiconductor memory device that can obtain the effect of reducing the soft error rate.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a memory cell portion of a DRAM, FIG. 2 is a sectional view of a memory cell portion of a conventional DRAM, and FIG. 3 is a plan view of a memory cell portion of a DRAM according to an embodiment of the present invention.
FIG. 4 shows the DR in one embodiment of the present invention shown in FIG.
A cross-sectional view taken along the line AA' of the memory cell portion of the AM, FIG.
2L) to (0 is a cross-sectional view of the manufacturing process of the memory cell portion of the DRAM in one embodiment of the present invention shown in FIG. 4, and FIG. 6 is a cross-sectional view of the DRAM memory in one embodiment of the present invention shown in FIG. 3. BB' line cross section m1 diagram of cell part, Figure 7(a)~
(e) is the DRA in one embodiment of the present invention shown in FIG.
FIG. 8 is a cross-sectional view of the memory cell portion of the DRAM according to the second embodiment of the present invention, and FIGS. FIG. 2 is a cross-sectional view of a memory cell portion of a DRAM in an embodiment of the present invention. 1...Switch transistor, 2...Storage capacitor element, 3...J゛-evening line, 4...Word line, 5...Tail line Parasitic capacitance, 1o...
・Silicon substrate, 11... 1st gate ・Oxide film,
12...Embedded polycrystalline silicon, 13...
... Cell plate electrode, 14 ... Interlayer insulating film, 15 ... Word line electrode, 16 ... Source diffusion region, 17 ... Drain diffusion region, 18・
...Second gate oxide film, 19...Data line electrode, 20...Memory cell diffusion region, 23...
...Field oxide film, 25...Second interlayer insulating film, 30...Data line contact window, 31...
...Storage capacitance element ml non-tact window 32...
storage capacitor element lower electrode, 33... insulator region,
34. River... Island silicon region, 36... Storage capacitor element insulating film, 4o... Burying material, 41.
...Base oxide film, 42...Silicon nitride film, 43
・・・・・・Groove of silicon substrate. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure C9) Figure 3 [ Dimensions
Shoes Figure 5 @ Figure 5 Figure 5 Figure 7? 3 No. 71-1 Fig. 9 4241 a3

Claims (5)

[Claims] (1) An MIS type field effect transistor and a storage capacitor element are included on a semiconductor substrate, the source or drain of the MIS type field effect transistor and one electrode of the storage capacitor element are connected, and the MIS type field effect transistor is connected to one electrode of the storage capacitor element. 1. A semiconductor memory device, wherein an insulating region is formed at the bottom of the transistor, and the storage capacitor element is formed on the surface of the semiconductor substrate, rather than an insulating film formed on the surface of the semiconductor substrate. (2) The semiconductor memory device according to claim 1, wherein the semiconductor substrate is silicon and the insulator region is silicon dioxide or silicon nitride. (3) forming a groove in a semiconductor substrate, forming a film that is oxidation-resistant and resistant to etching means of the semiconductor substrate on a surface other than the bottom surface of the groove, and forming a film in a direction other than the bottom surface of the groove; forming an insulating region through a step of etching the semiconductor substrate and a step of oxidizing the structure obtained by the above steps, and forming a storage capacitor element on the surface above the insulating film formed on the surface of the semiconductor substrate; A method for manufacturing a semiconductor memory device, characterized by: (4) The semiconductor substrate is silicon, an insulator region is formed by implanting an oxygen or nitrogen ion beam into the semiconductor substrate, and the storage capacitor element is formed on the surface of the semiconductor substrate through an insulating film. 4. The method of manufacturing a semiconductor memory device according to claim 3, wherein the semiconductor memory device is formed on the surface. (5) The method for manufacturing a semiconductor memory device according to claim 3, wherein the semiconductor substrate is silicon.