JP3224904B2 - Semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, particularly to a DRAM (Dynammic RAM).

[0002]

2. Description of the Related Art FIG. 5 is a sectional view showing a structure of a conventional DRAM cell. This structure has been described by T. Kaga et al.
Was announced at the IEDM in 1998 ("A 4.2 μm ² Ha
lf-Vccsheath-plate capacitor DRAM Cell with self-a
ligned buried plate-wiring. "Proceedings P. 332).

[0003] 41 is a bit line and 42 is a word line. The potential applied to the bit line 41 is transmitted to the diffusion layer 43, and is transmitted to the diffusion layer 44 by selecting the word line. The diffusion layer 44 is connected to a storage electrode 45, which is a capacitor insulating film 46.
And the capacitor electrode 47. The capacitor electrode 47 is connected to the buried impurity layer 48, and the buried impurity layers 48 are connected to each other to form a plate electrode, and have a potential of 1/2 Vcc in this paper.

[0004] Such a configuration has the following problems. A thick insulating film 50 on the inner surface of the trench 49 formed in the substrate,
A capacitor electrode 47, a capacitor insulating film 46, and a storage electrode 45 are formed. When the diameter d1 of the trench is 0.4 μm, the thickness d2 of the thick insulating film on its inner surface is 0.05 μm.
m and the thickness d3 of the capacitor electrode is 0.1 μm, the diameter of the storage electrode portion is 0.4− (0.05 + 0.1) ×
2 = 0.1 μm, and the surface area of the capacitor portion becomes small. In addition, a contact must be made to apply a potential to the buried impurity layer 48, but the processing may be difficult because the depth may be large.

[0005]

As described above, conventionally, there is a disadvantage that the surface area of the capacitor portion is reduced due to the presence of the thick insulating film formed on the inner surface of the trench and the capacitor electrode connected to the buried impurity layer. is there.

The present invention has been made in view of the above circumstances, and has as its object to increase the surface area of a capacitor portion while forming a trench having the same diameter as that of the prior art, and furthermore, to embed a trench. An object of the present invention is to provide a semiconductor memory device that facilitates external contact with an impurity layer (plate electrode).

[0007]

According to a semiconductor memory device of the present invention, a semiconductor substrate of a first conductivity type connected to a reference potential; a second conductivity type impurity layer formed on the semiconductor substrate; a first <br/> trench is opened in the second conductivity-type impurity layer of which is formed on a sidewall of the first trench min
A separation wall, formed in the semiconductor substrate;
A second trench having a diameter substantially equal to the diameter;
Capacitor formed on wall and inner surface of second trench
An insulating film, and the first and second insulating films covering the capacitor insulating film .
The electrode material of the first conductivity type to fill the trenches, are formed before Symbol second conductivity type impurity layer of, prior to said separation wall upper
Contacting the serial electrode material and the impurity region of the transfer transistor
And a connecting portion that continues .

In a method for manufacturing a semiconductor memory device in which one cell is constituted by one transfer transistor and one capacitor, a step of forming a second conductivity type impurity layer on a first conductivity type semiconductor substrate is provided. Forming a first opening where the semiconductor substrate is exposed at the bottom in the second conductivity type impurity layer, forming a separation wall on a side wall of the first opening, Forming a second opening in the semiconductor substrate with the dimensions as a mask and forming a trench over the second conductivity type impurity layer and the semiconductor substrate; and forming a capacitor insulating film on the inner surface of the trench. A step of covering, a step of covering the capacitor insulating film with a first conductive type electrode material and filling the trench, and a step of partially etching the electrode material to expose at least a part of the second conductive type impurity layer. And depositing a first conductivity type electrode material on the etched electrode material again, and contacting the second conductivity type impurity layer with the active region of the transfer transistor. It is characterized by.

[0009]

According to the present invention, after forming the first opening, a separating wall is formed on the side wall of the first opening. A second opening, that is, a trench is formed using the separation wall as a mask.
This prevents thick separation walls from being within the dimensions of the trench.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 shows a DRAM according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the configuration of the cell of FIG. A P-type substrate (P-type epitaxial layer) 12 is formed on an N-type substrate 11.
A trench 13 extends between the P-type substrate 12 and the N-type substrate 11.
Is opened. The inner surface of the trench 13 is covered with a capacitor insulating film. Polycrystalline silicon 15 serving as a capacitor electrode covers capacitor insulating film 14 and fills trench 13.

A side wall 16 made of an oxide film is formed on the side of the trench 13 on the side of the P-type substrate 12, so that the distance between the P-type substrate 12 and the polycrystalline silicon 15 is increased. Through the upper edge of the side wall 16, the conductive material of the polycrystalline silicon 15 becomes a P-type substrate.
It is connected to a source region 24 constituting a transfer transistor 21 via 12 diffusion layers 20.

The transfer transistor 21 has a gate oxide film 22 on the P-type substrate 12, a gate electrode (word line) 23 on the gate oxide film 22, and the source on the surface of the P-type substrate 12 so as to straddle the gate electrode 23. A region 24 and a drain region 25 are formed. The drain region 25 is connected to a wiring (bit line) 30 on the interlayer insulating film 29.

The storage operation of the above configuration is as follows. The potential applied to bit line 30 is transmitted to drain region 25 of transfer transistor 21. Here, if the word line 23 is selected, the word line 23 is transmitted to the source region 24, and a potential is accumulated between the polycrystalline silicon 15 serving as a capacitor electrode and the N-type substrate 11.

Next, a method of manufacturing a trench capacitor portion which is a main portion of the above structure will be described with reference to FIGS.
Will be described with reference to the sectional views of FIG. First, as shown in FIG. 2A, a P-type substrate 12 is formed on an N-type substrate 11 by epitaxial growth, and a silicon oxide film 17, a silicon nitride film 18, and a CVD oxide film 19 (not shown) are formed thereon. ) Are sequentially formed. These three-layer films are processed by a well-known lithography technique, and only a trench forming portion is removed. Furthermore, the above 3
Using the layer film as a mask, a shallow trench 13-1 is formed in the P-type substrate 12. At this time, the bottom of the shallow trench 13-1 is an N-type substrate
Try to reach 11.

Next, a CVD oxide film 16-1 is deposited on the entire surface of the substrate. Thereafter, the entire surface of the substrate is etched back using an anisotropic etching technique such as RIE. As a result, the above C
The VD oxide film 19 also disappears, and the CVD oxide film 16-1 remains as a side wall in the shallow trench 13-1 (side wall 16 in FIG. 1).

Next, as shown in FIG. 2B, a deep trench 13-2 is formed in the N-type substrate 11 at the bottom of the shallow trench 13-1 using the silicon nitride film 18 and the CVD oxide film 16-1 as a mask. Form. Subsequently, a capacitor insulating film 14 is formed on the inner surface of the trench 13-2 by thermal oxidation or the like, and the trench 13
-2 is filled with N-type polycrystalline silicon 15-1 and deposited on the silicon nitride film 18.

Next, as shown in FIG. 2C, the polycrystalline silicon 15-1 is etched back, and a part of the upper portion of the side wall 16 closer to the active layer of the transfer transistor is removed, and the P-type substrate is removed.
An N-type diffusion layer 20 is formed on the 12 exposed portions. Such a process is performed by controlling the direction of etching and the direction of ion implantation. Then, re-Doe Tchibakku polysilicon 15-2 N type, further peeling off the silicon nitride film 18.

Next, as shown in FIG. 2D, a transfer transistor 21 and the like are formed. The source region 24 is the diffusion layer 20
And is electrically connected. According to the above embodiment,
In the step of FIG. 2A, after forming the shallow trench 13-1, a thick side wall 16 (CVD oxide film 16-1) is formed on the side wall of the shallow trench 13-1. Thereafter, in the step of FIG. 2B, a deep trench 13-2 is formed using the side wall 16 as a mask, so that a thick isolation wall does not enter the dimensions of the trench.

Therefore, a large capacitor area can be obtained. According to the present invention, the diameter of the shallow trench 13-1 is equal to 0.
When the thickness is 4 μm and the thickness of the side wall 16 is 0.05 μm, the diameter of the deep trench 13-2 is 0.3 μm. In the conventional case shown in FIG. 5, since the thick insulating film is present on the inner surface of the trench, the actual diameter of the trench at the storage electrode portion is about 0.1 μm. Therefore, according to the present invention, the capacitor area is about three times larger.

Further, according to the present invention, the N-type substrate 11 has a structure in which the capacitor electrode 47 and the buried impurity layer 48 in FIG. 5 are used, and the N-type substrate 11 as a plate electrode is formed in a shallow place. I have. For this reason, contact processing of wiring for applying a voltage to the N-type substrate 11 becomes easier as compared with the related art.

Further, according to the above embodiment, FIG.
Process, shallow trench with minimum design rules
If the trench 13-1 is formed, the deep trench 13-2 in the process of FIG. 2B is formed smaller than the minimum design rule, and there is an advantage that it contributes to miniaturization.

FIG. 3 is a sectional view of a trench capacitor portion showing a first application example. The active region (source region 24) of the transfer transistor 21 and the polysilicon on the upper surface of the P-type substrate 12
Reference numeral 15 denotes a configuration connected by the diffusion layer 20. This is achieved by controlling the etching in the step of FIG.

FIG. 4 is a sectional view of a trench capacitor portion showing a second application example. In this configuration, a part of the capacitor is extended above the trench 13. Polysilicon 15-3 is formed on the side wall 16 in contact with the N-type substrate 11, and this is trenched.
13 is formed as the upper side wall, and the capacitor insulating film 14 is extended. According to this configuration, it is possible to obtain a wider capacitor area. In the step of FIG.
This is achieved by adding a step of forming polycrystalline silicon 15-3 on the 16 wall surfaces.

In each of the above embodiments and application examples, the P-type substrate 12 on the N-type substrate 11 is formed by epitaxial growth. However, the present invention is not limited to this. It is also conceivable to form them using ion implantation.

[0025]

As explained above, according to the present invention,
By using substrates of different conductivity types and dividing the trench into two steps, it is possible to provide a semiconductor memory device capable of securing a maximum capacitor area with a trench having a small diameter.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing method of a main part of the configuration of FIG. 1 in the order of steps;

FIG. 3 is a sectional view showing a configuration of a first application example.

FIG. 4 is a sectional view showing a configuration of a second application example.

FIG. 5 is a cross-sectional view showing a configuration of a cell of a conventional DRAM.

[Explanation of symbols]

11: N-type substrate, 12: P-type substrate, 13: trench, 14: capacitor insulating film, 15: polycrystalline silicon, 16: side wall, 17: silicon oxide film, 18: silicon nitride film, 20: diffusion layer, 21 …
Transfer transistor, 22 gate oxide film, 23 gate electrode (word line), 24 source region, 25 drain region, 29
... interlayer insulating film, 30 ... wiring (bit line).

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 27/04

Claims (2)

(57) [Claims] A first conductive type semiconductor substrate connected to a reference potential; a second conductive type impurity layer formed on the semiconductor substrate; and a hole opened in the second conductive type impurity layer . A first trench, a separation wall formed on a side wall of the first trench, and an inner diameter of the separation wall formed in the semiconductor substrate and substantially equal to an inner diameter of the separation wall.
A second trench having an equal diameter, and a key formed on the inner surface of the separation wall and the second trench.
And Yapashita insulating film, the capacitor insulating the first covering the membrane, and the electrode material of the first conductivity type to fill the second trench is formed before Symbol second conductivity type impurity layer of the separation wall on
A semiconductor memory device, comprising: a connection portion that connects the electrode material of the transfer transistor to an impurity region of the transfer transistor. 2. A method of manufacturing a semiconductor memory device in which one cell is constituted by one transfer transistor and one capacitor, comprising: forming a second conductivity type impurity layer on a first conductivity type semiconductor substrate; Forming a first opening in which the semiconductor substrate is exposed at the bottom in the second conductivity type impurity layer; forming a separation wall in a side wall of the first opening; Forming a second opening in the semiconductor substrate with the dimensions as a mask and forming a trench over the impurity layer of the second conductivity type and the semiconductor substrate; and forming a capacitor insulating film on the inner surface of the trench. Covering the capacitor insulating film with a first conductive type electrode material and filling the trench; partially etching the electrode material to expose at least a part of the second conductive type impurity layer; And depositing a first conductivity type electrode material on the etched electrode material again, and contacting the second conductivity type impurity layer with the impurity region of the transfer transistor. A method for manufacturing a semiconductor memory device, comprising: