KR960026933A - Columnar bipolar transistor and method of manufacturing the same - Google Patents

Columnar bipolar transistor and method of manufacturing the same Download PDF

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KR960026933A
KR960026933A KR1019950025696A KR19950025696A KR960026933A KR 960026933 A KR960026933 A KR 960026933A KR 1019950025696 A KR1019950025696 A KR 1019950025696A KR 19950025696 A KR19950025696 A KR 19950025696A KR 960026933 A KR960026933 A KR 960026933A
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polysilicon
pillar
region
base
emitter
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KR0149130B1 (en
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이규홍
이진효
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양승택
한국전자통신연구소
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41708—Emitter or collector electrodes for bipolar transistors

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  • Power Engineering (AREA)
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  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)

Abstract

본 발명은 기둥형 바이폴라 트랜지스터 및 그의 제조방법에 관한 것으로, 반도체기판에 형성된 트렌치로 한정되는 제1및제2기둥에서 에미터영역, 베이스영역 및 콜렉터영역이 형서되는 활성영역이 제1기둥으로 한정되고, 베이스 접속부에 의해베이스영역과 폴리실리콘 베이스전극의 일부분이 전기적으로 연결되므로 접촉면적을 감소하여 베이스의 회성영역이 증가되는 것을 방지하며, 또한, 트랜지스터의 역방향동작시 콜렉터영역으로 사용되는 고농도의 에미터영역과 베이스영역이 고농도 접합을 이루지 않는다.The present invention relates to a columnar bipolar transistor and a method for manufacturing the same, wherein an active region in which emitter regions, a base region and a collector region are formed in the first and second pillars defined by trenches formed in a semiconductor substrate is defined as a first pillar. Since the base connection part is electrically connected to the base region and a part of the polysilicon base electrode, the contact area is reduced to prevent the increase of the gray region of the base, and the high concentration of the emi used as the collector region during the reverse operation of the transistor. The terminator area and the base area do not form a high concentration junction.

그리고, 에미터 영역의 상부에 CMP방법으로 자기정렬된 넓은 표면적을 갖는 폴리실리콘 에미터전극을 형성한다.Then, a polysilicon emitter electrode having a large surface area self-aligned by the CMP method is formed on the emitter region.

따라서, 트랜지스터의 활성영역이 제1기둥으로 한정되므로 에미터 및 콜렉터와 베이스 사이의 기생접합 캐패시턴스를 감소시킬 수 있으며, 베이스영역과 폴리실리콘 베이스전극 사이의 접촉면적을 감소시키므로 베이스의 외성영역이 증가되는것을 방지하여 트렌지스터의 동작특성을 향상시킬 수 있고, 또한, 트랜지스터의 역방향동작시 순방향동작시와 유사한 전류이득을 얻을 수 있다.Therefore, since the active region of the transistor is limited to the first pillar, parasitic capacitance of the emitter and the collector and the base can be reduced, and the outer area of the base is increased because the contact area between the base region and the polysilicon base electrode is reduced. The transistor can be prevented from being improved to improve the operating characteristics of the transistor, and a current gain similar to that of the forward operation in the reverse operation of the transistor can be obtained.

그리고, 넓은 표면적을 갖는 폴리실리콘 에미터전극이 에미터영역과 자기정렬되므로 에미터전극을 형성하기 위한 접촉 개구의 형성이 용이하다.In addition, since the polysilicon emitter electrode having a large surface area is self-aligned with the emitter region, it is easy to form contact openings for forming the emitter electrode.

Description

기둥형 바이폴라 트랜지스터 및 그의 제조방법Columnar bipolar transistor and method of manufacturing the same

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 기둥형 바이폴라 트랜지스터의 단면도.3 is a cross-sectional view of the columnar bipolar transistor according to the present invention.

Claims (11)

소자영역을 한정하는 소정 깊이의 트렌치와, 이 트렌치 내에 제1및 제2기둥을 갖는 제1도전형의 반도체기판; 상기 반도체기판 트렌치 내의 제1기둥 하단 주변과 제2가둥의 전영역에 형성된 고농도의 제2도전형의 불순물확산영역; 상기 제1기둥의 상부에 형성된 고농도의 제2도전형의 에미터영역; 상기 제1기둥의 상기 불순물확산영역과 에미터영역의중간 부분에 형성된 제1도전형의 베이스영역; 상기 제2기둥에 형성된 불순물 확산영역인 고농도의 제2도전형의 싱크; 상기 트렌치 내에 기둥 보다 소정의 깊이 만큼 낮게 매립된 제1도전형의 폴리실리콘 베이스전극; 상기 폴리실리콘 베이스전극과 상기 반도체기판을 전기적으로 격리시키기 위해 상기 트랜치 내에 형성된 제1절연산화막; 상기 베이스영역과 폴리실리콘 베이스전극 사이를 부분적으로 연결하도록 형성된 제1도전형의 베이스 접속부; 상기 에미터영역과 자기정렬되게 형성된 고농도의 제2도전형의 폴리실리콘 에미터전극; 상기 폴리실리콘 에미터전극과 폴리실리콘 베이스전극이 전기적으로연결되는 것을 방지하는 제2절연산화막; 상기 폴리실리콘 에미터전극, 폴리실리콘 베이스전극 및 싱크의 상부에 형성된에미터금속전극, 베이스금속전극 및 콜렉터금속전극을 구비하는 기둥형 바이폴라 트랜지스터.A first conductive semiconductor substrate having a trench having a predetermined depth defining an element region, and having first and second pillars in the trench; A high concentration of second conductivity type impurity diffusion region formed around the lower end of the first pillar and in the entire region of the second pillar in the semiconductor substrate trench; An emitter region of a high concentration second conductivity type formed on the first pillar; A base region of a first conductivity type formed in a middle portion of the impurity diffusion region and the emitter region of the first pillar; A highly concentrated second conductive type sink that is an impurity diffusion region formed in the second pillar; A polysilicon base electrode of a first conductivity type buried in the trench by a predetermined depth lower than the pillar; A first insulating oxide film formed in the trench to electrically isolate the polysilicon base electrode and the semiconductor substrate; A base connection portion of a first conductivity type formed to partially connect between the base region and the polysilicon base electrode; A high concentration of the second conductive polysilicon emitter electrode formed in self alignment with the emitter region; A second insulating oxide film which prevents the polysilicon emitter electrode and the polysilicon base electrode from being electrically connected to each other; And a polysilicon emitter electrode, a polysilicon base electrode, and an emitter metal electrode, a base metal electrode, and a collector metal electrode formed on the sink. 제1항에 있어서, 상기 제1및 제2기둥은 직경이 0,3~2μm, 높이가 0.7~1.5μm인 기둥형 바이폴라 트랜지스터.The columnar bipolar transistor of claim 1, wherein the first and second pillars have a diameter of 0,3 to 2 μm and a height of 0.7 to 1.5 μm. 제1항에 있어서, 상기 제1절연산화막이 1500~2500Å의 두께로 형성된 기둥형 바이폴라 트랜지스터.The columnar bipolar transistor according to claim 1, wherein the first insulating oxide film is formed to a thickness of 1500 to 2500 Å. 제1항에 있어서, 상기 제1절연막은 트렌치 및 제2기둥의 측면보다 제1기둥의 측면이 1000~3000Å가 낮게형성된 기둥형 바이폴라트랜지스터.The pillar-shaped bipolar transistor of claim 1, wherein the first insulating layer has a lower side of the first pillar than the side of the trench and the second pillar by 1000 to 3000 μs. 제1항 내지 제4항 중 어느 한 항에 있어서, 상기 트랜치 내에 한개 이상의 제1기둥이 형성된 기둥형 바이폴라 트랜지스터.The columnar bipolar transistor according to any one of claims 1 to 4, wherein at least one first pillar is formed in the trench. 제1도전형의 실리콘기판에 소자영역을 한정하여 제1및 제2기둥이 형성되도록 트렌치 에칭하는 공정; 상기제1기둥 하단의 주변영역과 제2기둥에 고농도의 제2도전형의 불순물확산영역과 싱크를 형성하는 공정; 상기 반도체기판의전면에 제1절연산화막과 제1도전형의 폴리실리콘을 증착힌 후 상기 폴리실리콘을 상기 반도체기판의 에칭되지 않은 부분에 증착된 상기 제1절연산화막이 노출되도록 제거하여 상기 트렌치 내부에 매립하는 공정; 상기 폴리실리콘층을 트렌치내부의 소정 깊이가 되도록 에칭하여 폴리실리콘 베이스전극을 한정하는 공정; 상기 노출된 제1기둥의 주위의 제1절연산화막을 소정 깊이로 에칭하고, 이 에칭된 부분에 제1도전형의 폴리실리콘을 채워서 베이스 접속부를 형성하는 공정; 상기반도체고판의 전면에 제2절연산화막과 폴리실리콘을 증착하고 상기 제2절연산하막을 연마중지막으로 이용하여 상기 폴리실리콘을 제거하여 평탄화하는 공정; 상기 제1기둥 상부의 제2산화막을 선택적으로 제거하여 제1기둥의 표면을 노출시키는 공정; 상기 노출된 제1기둥에 제1도전형의 불순물과 제2도전형의 불순물을 순차적으로 이온주입하고 열처리하여 상기베이스 접속부와 연결되는 제1도전형의 베이스영역과 제2도전형의 에미터영역을 형성하는 공정; 상기 에미터영역의 상부에 이 에미터영역의 표면적 보다 넓은 표면적을 갖고 자기정렬된 제2도전형의 폴리실리콘 에미터전극을 형성하는 공;상기 제2절연산화막과 폴리실리콘 에미터전극의 상부에 보호막을 형성한 후 상기 폴리실리콘 베이스전극, 폴리실리콘 에미터전극 및 싱크가 노출되도록 구멍을 형성하고, 전극을 형성하는 공정을 구비하는 기둥형 바이폴라 트렌지스터의 제조방법.Trench-etching the first and second pillars by forming a device region in the first conductive silicon substrate; Forming a sink with an impurity diffusion region having a high concentration of a second conductivity type in the peripheral region and the second pillar at the bottom of the first pillar; After depositing a first insulating oxide film and a polysilicon of the first conductive type on the front surface of the semiconductor substrate, the polysilicon is removed to expose the first insulating oxide film deposited on the unetched portion of the semiconductor substrate to expose the inside of the trench. Buried in; Etching the polysilicon layer to a predetermined depth in the trench to define a polysilicon base electrode; Etching the first insulating oxide film around the exposed first pillar to a predetermined depth, and filling the etched portion with polysilicon of a first conductivity type to form a base connection portion; Depositing a second insulating oxide film and polysilicon on the entire surface of the semiconductor solid plate and removing and planarizing the polysilicon using the second insulating underlayer as a polishing stop film; Selectively removing the second oxide film on the first pillar to expose the surface of the first pillar; The first conductive type base region and the second conductive type emitter region which are connected to the base connection part by ion implantation and heat treatment of the first conductive type impurity and the second conductive type impurity sequentially on the exposed first pillar. Forming a; A ball having a surface area larger than that of the emitter area and forming a self-aligned second type of polysilicon emitter electrode on the emitter area; on the upper portion of the second insulating oxide film and the polysilicon emitter electrode And forming a hole so that the polysilicon base electrode, the polysilicon emitter electrode, and the sink are exposed after forming the passivation layer, and forming the electrode. 제6항에 있어서, 상기 제1기둥의 상부에 상기 트렌치 에칭시 마스크로 이용되는 산화막과 측면에 확산 마스크로 이용되는산화막을 잔류시키고 상기 제2도전형의 불순물을 확산하여 상기 불순물확산영역 및 싱크를 형성하는 기둥형 바이폴라 트랜지스터의 제조방법.The impurity diffusion region and the sink of claim 6, wherein an oxide film used as a mask during the trench etching and an oxide film used as a diffusion mask are left on the side of the first pillar and the impurities of the second conductive type are diffused. Method of manufacturing a columnar bipolar transistor to form a. 제7항에 있어서, 상기 불순물매립영겨 및 싱크 형성시 확산 마스크로 사용되는 산화막을 1500~3000Å의 두께로 형성하는 기둥형 바이폴라 트랜지스터의 제조방법.The method of manufacturing a columnar bipolar transistor according to claim 7, wherein an oxide film, which is used as a diffusion mask when forming the impurity buried bran and the sink, is formed to a thickness of 1500 to 3000 GPa. 제6항에 있어서, 상기 제1절연산화막을 연마중지막으로 이용하여 기계화학적 연마(Chimical MechanicalPolishing)방법으로 상기 폴리실리콘을 트렌치 내부에 한정하는 기둥형 바이폴라 트랜지스터의 제조방법.The method of claim 6, wherein the polysilicon is limited to the inside of the trench by a mechanical mechanical polishing method using the first insulating oxide film as a polishing stop film. 제6항에 있어서, 상기 노출된 제1기둥의 주위의 제1산화막을 선택적으로 1000~3000Å정도 습식 에칭하고,이 에칭된 부분에 제1도 전형의 폴리실리콘을 채우는 기둥형 바이폴라 트랜지스터의 제조방법.The method of manufacturing a pillar bipolar transistor according to claim 6, wherein the first oxide film around the exposed first pillar is selectively wet etched at about 1000 to 3000 Pa, and the etched portion is filled with polysilicon of first degree typical. . 제6항 내지 제10항 중 어느 한 항에 있어서, 상기 트렌치 내에 한개 이상의 제1기둥을 형성하는 기둥형바이폴라 트랜지스터의 제조방법.The method of manufacturing a columnar bipolar transistor according to any one of claims 6 to 10, wherein at least one first pillar is formed in the trench. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950025696A 1994-12-19 1995-08-21 A pillar bipolar transistor and method for manufacturing the same KR0149130B1 (en)

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KR19940035161 1994-12-19
KR94-35161 1994-12-19

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KR0149130B1 KR0149130B1 (en) 1998-10-01

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Publication number Priority date Publication date Assignee Title
CN110739305A (en) * 2018-07-19 2020-01-31 株式会社村田制作所 Semiconductor device with a plurality of semiconductor chips

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110739305A (en) * 2018-07-19 2020-01-31 株式会社村田制作所 Semiconductor device with a plurality of semiconductor chips
CN110739305B (en) * 2018-07-19 2023-10-03 株式会社村田制作所 Semiconductor device with a semiconductor device having a plurality of semiconductor chips

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