JPH0321056A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable forming a high-performance, high-speed, and high-function and highly integrated reliable semiconductor integrated circuit by forming specific element separation regions. CONSTITUTION:Element separation regions are formed by first insulating films 4 containing impurities and formed selectively, second insulating films 5 not containing an impurity and formed on the sidewalls of said first insulating films 4 self-alignedly, and impurity channel stopper regions 2 made by diffusing the impurities contained in said first insulating films 4 into a semiconductor substrate 1 thereunder. Therefore, the element separation regions without a bird's beak storing away stress can be made. Thereby high integration by forming fine element regions can be achieved, the performance can be improved by improving the dielectric strength of a gate oxide film, and the reliability can be improved by making electrons or holes hard to trap and lengthening the lifetime of carriers.

Description

[Detailed Description of the Invention] [Summary] An element isolation region provided on a semiconductor substrate includes a selectively provided impurity-containing first insulating film, and a sidewall of the first insulating film subjected to RIE (reaction reaction). A second insulating film that does not contain impurities is provided on the Selfa line by a method (chemical ion etching), and a second insulating film is provided on the semiconductor substrate directly under the first insulating film by diffusion of impurities contained in the first insulating film. Since the first insulating layer has a structure formed by an impurity channel stopper region, it is possible to form a structure without bird's beaks, thereby achieving miniaturization of the device region, improvement of gate oxide film breakdown voltage, and improvement of carrier life. It is possible to form a wiring body with good step coverage by reducing the film step difference with the second insulating film formed on the sidewall, and to reduce the junction capacitance and improve the junction breakdown voltage by forming the source/drain region and the channel stopper region separately.
A semiconductor device that makes it possible to reduce wiring capacitance by making an insulating film for forming an element isolation region thicker without impairing element characteristics.

There is a need for a means to achieve separation.

[Industrial Application Field] The present invention relates to MIS and bibolar semiconductor devices, and particularly relates to a semiconductor device that enables the formation of highly integrated semiconductor integrated circuits having element isolation regions without bird's beaks. Formation of element isolation regions in circuits has traditionally been carried out by selective oxidation using a nitride film, the so-called LOCOS method, but today, with the degree of integration increasing dramatically,
It is difficult to miniaturize the element formation area due to the bird's beak that induces stress that always occurs with the LOCOS method.
Problems such as deterioration of the withstand voltage of thinned gate oxide films and deterioration of lifetime due to easy trapping of electrons or holes have become prominent, and these problems are becoming a hindrance to higher integration. Therefore, a highly integrated device that does not have a bird's beak, can reduce the level difference in the device isolation region, and can form a self-aligned channel stopper region separated from the source/drain region [Conventional technology 1 Figure 6 shows a conventional semiconductor device] In the schematic side sectional view, 51 is p
- type silicon (Si) substrate, 52 is a p-type well region, 5
3 is an n-type well region, 54 is a p-type channel stopper region, 55 is an n-type channel stopper region, 56 is a field oxide film, 57 is an n-type source drain region, 58 is a p-type source-drain region, and 59 is a gate Oxide film, 60
61 is a gate electrode, 61 is a block oxide film, 62 is a phosphosilicate glass (PSG) film, and 63 is an A1 wiring.

In the same figure, a p-type well region 52 and an n-type well region 53 are selectively provided on a p-type silicon (Si) substrate 51, and the p-type well region 52 has an N-channel transistor and the n-type well region 52 has a p-type well region 52 and an n-type well region 53. P-channel transistors are selectively formed in each type well region 53. The element isolation region is formed by the Locos method, and has a bird's beak that contains stress. The LOCOS method has the advantage that the step difference in the element isolation region can be alleviated by the bird's beak, and a wiring body with good stepping force barrier can be formed. There are disadvantages such as the breakdown voltage of the thinned gate oxide film deteriorates and the lifetime deteriorates due to easy trapping of electrons or holes. In addition, in element isolation using the LOCOS method, the element isolation insulating film cannot be easily thickened, resulting in increased interconnect capacitance, and the source train region and channel stopper region cannot be separated, resulting in increased junction capacitance. It also has the disadvantage that it is disadvantageous in achieving higher functionality because it cannot increase the withstand voltage.

[Problems to be Solved by the Invention] The problems to be solved by the present invention are that, as shown in the conventional examples, it is difficult to miniaturize the element formation area due to the presence of bird's beaks in the LOCOS method, and However, it has not been possible to improve the problems such as deterioration of the withstand voltage of the gate oxide film and deterioration of the life span due to easy trapping of electrons or holes. Furthermore, in device isolation using the LOCOS method, the device isolation insulating film cannot be easily thickened, resulting in a large wiring capacitance, and the source/drain region and channel stopper region cannot be separated, resulting in a large junction capacitance. In some cases, high functionality has not been achieved due to the inability to increase the level of performance.

[Means for Solving the Problem] The above problem is solved by the first insulating film containing impurities provided on the semiconductor substrate, and the second insulating film not containing impurities provided on the sidewall of the first insulating film. The present invention is solved by a semiconductor device in which an element isolation region is formed by an insulating film and an impurity channel stopper region provided in the semiconductor substrate immediately below the first insulating film.

[Function] That is, in the semiconductor device of the present invention, the element isolation region provided in the semiconductor substrate 2 is formed on the sidewall of the selectively provided impurity-containing first insulating film and the first insulating film. R.I.
an impurity-free second insulating film provided in the self-line by the E method and an impurity channel provided in the semiconductor substrate immediately below the first insulating film by diffusion of impurities contained in the first insulating film; It has a structure formed by a stopper region. Therefore, since the element isolation region can be formed without using the so-called LOCOS method using selective oxidation, that is, it can be formed in a structure without bird's beaks that cause stress, high integration can be achieved by forming fine element regions. The first insulating film step is formed on the sidewall of the 9-point insulating film, which can improve performance by improving the withstand voltage of the gate oxide film, and improve reliability by making it difficult for electrons or holes to be trapped and improving carrier life. Since the step force can be relaxed by the second insulating film formed in the second insulating film, it is also possible to form a wiring body with good stepping force variation.

Furthermore, the capacitance of the wiring body can be reduced because the film burr of the insulating film for forming the element isolation region can be minimized by shaping the etching stopper film, and the capacitance of the wiring body can be reduced. Since the regions can be separated by self-line, it is possible to reduce the junction capacitance, thereby increasing the speed, and increasing the junction breakdown voltage, thereby making it possible to improve the functionality. That is, it is possible to obtain a semiconductor device that enables the formation of extremely high performance, highly reliable, high speed, highly functional and highly integrated semiconductor integrated circuits. explain. FIG. 1 is a schematic side sectional view of a first embodiment of the semiconductor device of the present invention, FIG. 2 is a schematic side sectional view of the second embodiment of the semiconductor device of the present invention, and FIG. 3 is a schematic side sectional view of the semiconductor device of the present invention. 4 is a schematic side sectional view of the third embodiment of the device; FIG. 4 is a schematic side sectional view of the fourth embodiment of the semiconductor device of the present invention; FIG.
Figures (a) to (e) are process cross-sectional views of an embodiment of the method for manufacturing a semiconductor device of the present invention.

Identical objects are indicated by the same reference numerals throughout the figures.

FIG. 1 is a schematic side sectional view of the first embodiment of the semiconductor device of the present invention when a p-type silicon substrate is used, and 1 is 10
2 is a p-type channel stopper region of about 10 cm, 3 is an n-type source drain region of about 10 cm, and 4 contains impurities of about 0.8/Jm. The first insulating film (BSG), 5 is the second insulating film (sidewall oxide film) that does not contain impurities of about 0.5/Am, 6 is the gate oxide film of about 20 nm, and 7 is the gate electrode of about 300 nm. ,
8 is a block oxide film of about 50 nm, 9 is 0.8 ym
A phosphosilicate glass (PSG) film with a thickness of about 1.0 μm is shown, and 10 indicates an A1 wiring with a thickness of about 1.0 μm.

In the figure, a first insulating film 4 selectively containing impurities is provided on a p-type silicon (Si) substrate 1, and impurities are added to the self-alignment lines by RIE on the side walls of the first insulating film 4. A second insulating film 5 not containing is provided, and a channel stopper region 2 is provided in the semiconductor substrate directly below the first insulating film by diffusion of impurities contained in the first insulating film 4. The first insulating film 4
, has a structure in which an element isolation region is formed by the second insulating film 5 and the channel stopper region 2,
Further, the n+ type source/drain region 3 and the channel stopper region 2 are formed separately. (However, the etching stopper film is not shown.) Therefore,
Since the device isolation region can be formed by selective oxidation without using the so-called LOCOS method, in other words, it can be formed in a structure that does not have bird's beaks that cause internal stress. High performance can be achieved by improving the breakdown voltage of the film, and high reliability can be achieved by making it difficult for electrons or holes to be trapped and improving carrier life. Further, a second insulating film step is formed on the side wall of the first insulating film.
It is also possible to form a wiring body with a good step force barrier because the step force can be relaxed by the insulating film. moreover,
By forming an etching stopper film, the film erosion of the insulating film for forming the element isolation region can be minimized, so the capacitance of the wiring body can be reduced, and the source/drain region and the channel 1 heparium region can be separated by self-line. Therefore, it is possible to increase the speed by reducing the junction capacitance, and to increase the functionality by increasing the junction breakdown voltage.

FIG. 2 is a schematic side sectional view of a second embodiment of the semiconductor device of the present invention, and 1 to 3 and 5 to 10 are the same as in FIG.
4a is a first insulating film (base oxide film) that does not contain impurities;
4b indicates a first insulating film containing impurities.

In this figure, the first insulating film is formed in the same ellipse as in FIG. 1, except that the first insulating film has a laminated structure of an insulating film 4a that does not contain impurities and an insulating film 4b that contains impurities.

In addition to the same effect as in Figure 1, insulation g that does not contain impurities
Since the impurity is diffused through 4a, a shallower channel region 1 and heparium region 2 can be formed, allowing higher integration.

FIG. 3 is a schematic side sectional view of the third embodiment of the semiconductor device of the present invention, where 1 to 3 and 5 to 10 are the same as in FIG. 1, and 4a is the same as in FIG. , 4bp is a first insulating film (BSG) containing p-type impurities, 4bn is a first insulating film (psG) containing n-type impurities, 11 is a p-type well region, 1
2 is an n-type well region, 13 is an n-type channel/thumper region, and 14 is a p-type source/drain region.

The figure shows a C-MOS type semiconductor device, in which a p-type well region 11 and an n-type well region 12 are selectively formed on a p-type silicon (Si) substrate 1. On the p-type well region 11, a first insulating film (4bp, 4a) is selectively provided on the base oxide film 4a and containing p-type impurities. )
A second insulating film 5 that does not contain impurities in the self-line is provided on the side wall of the cell line by RIE method, and directly under the first insulating film (4bp, 4a.), the first insulating film 5 is
Boron contained in A/Ibp is diffused to provide a p-type channel stopper region 2, and the first insulating film (4
bp, 4a), an element isolation region is formed by the second insulating film 5 and the p-type channel stopper region 2, and an N-channel transistor consisting of an n-type source train region 3, a gate oxide film 6, and a gate electrode 7. is formed. On the other hand, a base oxide film 4a is formed on the n-type well region 12.
The ↓th insulating film (psG) 4 containing n-type impurities is laminated on
bn is selectively provided, and the first insulating film (4
A second insulating film 5 that does not contain impurities in the self-line is provided on the side wall of the cell line (4bn, 4a) by the RIE method, and directly below the first insulating film (4bn, 4a) is the first insulating film 5. Phosphorous contained in the insulating film 4bn is diffused to provide an n-type channel stopper region 13, and the first insulating film (4bn, 4a), the second insulating film 5 and the n-type channel stopper region 13 are provided.
An element isolation region is formed by a p-type channel stopper region 13, and a p-type channel stopper region 13 is formed by a p-type source/drain region 14, a gate oxide film 6, and a gate electrode 7. The effects shown in FIGS. 1 and 2 can also be obtained in a C-MOS type semiconductor device in which a helangistor is formed.

FIG. 4 is a schematic side sectional view of a fourth embodiment of the semiconductor device of the present invention, where 1- to 3, 5 to 10 are the same as in FIG. The same thing as in Figure 3,
4al is the first thin insulating film (base oxide film) that does not contain impurities, and 4a2 is the first thick insulating film (base oxide film) that does not contain impurities.
Base oxide film> is shown.

In the same figure, a 4bp first insulating film (BSG) containing p-type impurities is also used in the element isolation region of the P-channel transistor.
is used, n-type channel stopper region 1
3 is not provided, and a thin base oxide film 4a1 is formed on the N-channel transistor side, and a thick base oxide film 4a2 is formed on the P-channel transistor side.
9 (The structure on the N-channel transistor side is exactly the same as in FIG. 3.) In this case, the p-type channel stopper region 2 on the N-channel transistor side is doped with p-type impurities. First insulation M (BSG) containing
Boron is formed by diffusing boron from llbp through a thin base oxide film 4a1, and on the other hand, the first . insulation film (BSG) 4bl)
A thick base oxide film 4a2 is formed to suppress the diffusion of boron from the substrate, and the slightly high concentration n-type well region 12 also serves as an n-type channel stopper. That is, the first insulating film can be unified to the insulating film (Bsc) abp containing p-type impurities, and the manufacturing process can be simplified. Of course, the effects shown in FIG. 3 can also be obtained.9 Next, FIG.
) to (e) and FIG. 1.9 FIG. 5(a) By applying conventional techniques, p-type silicon (S
i) A borosilicate glass (BSG) film 4 and a nitride film 1 on a substrate 1
5 in order of growth.

FIG. 5(b) Next, using a normal photolithography technique, the nitride film 15 and the borosilicate glass (BSG) film 4 are selectively etched and removed one after another to form a first region forming a part of the element isolation region. An insulating film 4 and a film burr prevention film (nitride film) 15 are formed. Next, the chemical vapor grown oxide film 5 is grown in order to form a second insulating film 5 constituting a part of the element isolation region.

FIG. 5(c) Next, the chemical vapor grown oxide film 5 is anisotropically dry etched by RIE, leaving a second insulating film (side wall oxide film) 5 on the side wall of the first insulating layer M4 with self-alignment. Forming an element isolation region 9 FIG. 5(d) Next, the film edge prevention M (nitride film) 15 is removed by etching with boiled phosphoric acid. Next, a gate oxide film 6 and a polycrystalline silicon film are sequentially grown (9).Then, the polycrystalline silicon film is patterned using a normal photolithography technique to form a gate electrode 7. Next, high-temperature heat treatment is performed to diffuse impurities from the borosilicate glass (BSG) film 4 to form a p-type channel stopper region 2.

FIG. 5(e) Next, using a normal photolithography technique, using a resist (not shown), the first insulating film 4, the second insulating film (sidewall oxidation M) 5 and the gate electrode 7 as mask layers, Arsenic ions are implanted to selectively define n+ type source train regions 3.

Figure 1 Next, unnecessary portions of the gate oxide film 6 are removed by etching.

Next, a block oxide film 8 and a phosphosilicate glass (PSG) film 9 are sequentially grown. Next, a slightly high-temperature process is performed to form an n-type source/drain region 3 having a desired depth.Next, by applying normal techniques, electrode contact windows are formed, AI wiring 10, etc. are formed, and the semiconductor device is completed. Complete.

In the above manufacturing method, a film burr prevention film (nitride film) is provided on the first insulating film, but when forming the second insulating film on the sidewall of the first insulating film, If it is possible to perform etching that leaves a sufficient amount of the film, the anti-film slippage film (nitride film) may be omitted.Also, the anti-film slippage film (nitride fIIi.) may be left as it is and the first layer for forming the element isolation region. It may also be part of the insulating film.

As shown in the following two embodiments, according to the semiconductor device of the present invention, the element isolation region can be formed by selective oxidation without using the so-called LOCOS method. Because it can be formed into
High integration is achieved by forming fine device regions, and high performance is achieved by improving the breakdown voltage of gate oxide films.
Electrons or poles are less likely to be trapped, and carrier life can be improved, making it possible to achieve high reliability. Furthermore, it is possible to form a wiring body with a good stepping force barrier because the step of the first insulating film can be relaxed by the second insulating film formed on the side wall. Furthermore, by forming an etching stopper film, the film burr of the insulating film for forming the element isolation region can be minimized, so the capacitance of the wiring body can be reduced, and the source drain region and channel stopper region can be separated by self-line. Therefore, it is possible to increase the speed by reducing the junction capacitance, and to increase the functionality by increasing the junction breakdown voltage.

[Effects of the Invention] As described above, according to the present invention, in MIS and bibolar semiconductor devices, the first insulating film containing impurities,
A second insulating film that does not contain impurities is provided on the side wall of the first insulating film in a self-aligned manner, and a second insulating film that does not contain impurities is provided directly under the first insulating film by diffusion of impurities contained in the first insulating film. Since the device isolation region is formed by the channel stopper region formed by the first insulating film, it is possible to form a structure without bird's beaks, thereby achieving miniaturization of the device region, improvement of gate oxide film breakdown voltage, and improvement of carrier life. The formation of a wiring body with a good stepping force barrier by reducing the step difference with the second insulating film formed on the side wall,
Reduced junction capacitance and improved junction breakdown voltage by being able to separate the channel stopper region and source drain region formed by self-line formation, and reduced wiring capacitance by making the insulating film for forming the device isolation region thicker without impairing device characteristics. can be made possible. In other words, it is possible to obtain a semiconductor device that enables the formation of extremely high performance, highly reliable, high speed, highly functional, and highly integrated semiconductor integrated circuits9.

[Brief explanation of the drawing]

FIG. 1 is a schematic side sectional view of a first embodiment of a semiconductor device of the present invention, FIG. 2 is a schematic side sectional view of a second embodiment of a semiconductor device of the present invention, and FIG. 3 is a semiconductor device of the present invention. FIG. 4 is a schematic side sectional view of the third embodiment of the device; FIG. 4 is a schematic side sectional view of the fourth embodiment of the semiconductor device of the present invention; FIGS. 5(a) to (e) are the manufacturing method of the present invention. FIG. 6 is a schematic side sectional view of a conventional semiconductor device. In the figure, 1 is a p-type silicon (Si) substrate, 2 is a p-type channel stopper region, 3 is an n-type source train region, 4 is a first insulating film (BSG) containing impurities, and 4a is a first insulating film containing impurities. 4al is the first thin insulating film (base oxide film) that does not contain impurities, 4a2 is the first thick insulating film (base oxide film) that does not contain impurities, 4b is the first thick insulating film (base oxide film) that does not contain impurities. First insulating film (BSG) containing impurities, 4bl)
is the first insulating film (BSG) containing p-type impurities, 4bn is the first insulating film (1) SG) containing n-type impurities, 5 is the second insulating film (sidewall oxidation M) containing no impurities, 6 is a gate oxide film, 7 is a gate electrode, 8 is a block oxide film, 9 is a phosphosilicate glass (PSG) film, 10 is an A1 wiring, 11 is a p-type well region, 12 is an n-type well region, 13 is an n-type well region 14 is a p-type source train region 15 is a nitride film for an etching stopper.

Claims (3)

[Claims] (1) A first insulating film containing impurities provided on a semiconductor substrate, a second insulating film not containing impurities provided on the side wall of the first insulating film, and directly below the first insulating film A semiconductor device, wherein an element isolation region is formed by an impurity channel stopper region provided in the semiconductor substrate. (2) The semiconductor device according to claim 1, wherein the first insulating film has a laminated structure of a film containing impurities and a film not containing impurities. (3) The semiconductor device according to claim 1, wherein the impurity channel stopper region is provided by diffusion of impurities contained in the first insulating film.