JPH0358470A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make a semiconductor device high in performance, reliability, operation speed, and integration by a method wherein an element isolating region is formed of a second insulating film which is provided onto a first insulating film and its side wall in a self-aligned manner, and an impurity well region is demarcated by a trench filled with a third insulating film. CONSTITUTION:An element isolating region provided onto a semiconductor substrate 1 is formed of a second insulating film 5b which is formed in a self- aligned manner on a selectively formed first insulating film 5a and its side wall, on the other hand, a P-type and an N-type impurity well region, 2 and 3, provided onto the semiconductor substrate 1 are formed into structures demarcated with a trench 4a filled with a third insulating film 4b. In this case, an element isolating region can be formed without using a selective oxidation method, that is, the region concerned can be formed in a structure without a bird beak in which a stress is present, so that a fine element isolating region can be formed. By this setup, a semiconductor device can be made high in performance, reliability, operation speed, and integration.

Description

Detailed Description of the Invention [Summary] An element isolation region provided on a semiconductor substrate is provided with a first insulating film selectively provided and a sidewall of the first insulating film.
The second insulating film is formed on the self-line by IE (reactive ion etching) method, while the two types of impurity well regions provided on the semiconductor substrate are
Since it has a structure defined by a trench filled with the third insulating film, it can be formed into a structure without bird's beaks, resulting in miniaturization of the device area, improvement of gate oxide film breakdown voltage, and improvement of carrier life. The wiring body can be formed with a good stepping force barrier because the step of the first insulating film can be alleviated by the second insulating film formed on the sidewall. Semiconductor device N9 that enables high speed by reducing capacitance and high integration by forming impurity well region boundaries with fine trenches [Industrial Application Field] The present invention relates to an MIS type semiconductor device, In particular, it relates to a semiconductor device that enables the formation of highly integrated semiconductor integrated circuits having fine element isolation regions and impurity well isolation regions. Conventionally, for the formation of element isolation regions in semiconductor integrated circuits, nitride films have been selected. So-called LOCO due to oxidation
Although this is carried out using the S method, it is difficult to miniaturize the element formation area due to the stress-inducing bird's beak that always occurs with the LOCOS method, the withstand voltage of the thinned gate oxide film deteriorates, and electrons or holes are easily generated. Regarding problems such as deterioration of lifetime due to traps and separation of impurity well regions, problems such as impurity diffusion in the lateral direction are extremely large and miniaturization is not possible because the impurity well regions cannot be formed in self-alignment lines. , is becoming a hindrance to higher integration. Therefore, there is a need for a means that can realize the formation of element isolation regions without bird's beaks and the formation of fine impurity well regions using 1: Luffa lines.9 [Prior Art] Figure 5 shows a schematic side of a conventional semiconductor device. FIG. 51
52 is a p-type silicon (Si) substrate, 52 is a p-type well region, 53 is an n-type well region, 54 is a p-type channel stopper region, 55 is an n-type channel stopper region, 56 is a field oxide film, and 57 is an n-type well region. type source drain region, 5
8 is a p-type source/drain region, 59 is a gate oxide film,
60 is a gate electrode, 61 is a block oxide film, 62 is a phosphosilicate glass (PSG) film, and 63 is an old wiring.

In the figure, p-type silicon (S1) base W. A p-type well region 52 and an n-type well region 53 are selectively provided in the p-type well region 52, and a p-channel transistor is selectively provided in the n-type well region 53. It is formed in The element isolation region is formed by the LOCOS method, and there is a bird's beak that contains stress.
According to the S method, steps in the element isolation region can be alleviated by the bird's beak, and it has the advantage of forming a wiring body with a good stepping force barrier. There are disadvantages such as deterioration of the withstand voltage of the gate oxide film and deterioration of the lifespan due to easy trapping of electrons or holes.

Furthermore, element isolation using the LOCOS method has the disadvantage that the element isolation insulating film cannot be easily made thick, resulting in a large interconnect capacitance, which is disadvantageous for increasing speed. On the other hand, since the impurity well region is not formed in the self-alignment line, the boundary region is formed with a considerable space in consideration of the lateral diffusion of the impurity well region, and the degree of integration is not increased.

[Problems to be Solved by the Invention] The problems to be solved by the present invention are that, as shown in the conventional example, it is difficult to miniaturize the element formation region due to the presence of a bird's beak in the LOCOS method; The breakdown voltage of the thinned gate oxide film deteriorates, the lifetime deteriorates due to easy trapping of electrons or holes, etc., which could not be improved, and the interconnect capacitance increases because the element isolation insulating film cannot be easily thickened. 9 [Means for solving the problem] The above problems are as follows: A first selectively provided on a semiconductor substrate.
and a second insulating film provided on the side wall of the first insulating film.
an element isolation region is formed by an insulating film, and an impurity well region is defined by a trench filled with a third insulating film that is selectively provided in the semiconductor substrate under the first insulating film. 9 [Function] That is, in the semiconductor device of the present invention, the element isolation region provided on the semiconductor substrate is formed by the selectively provided first insulating film and A second insulating film is formed on the side wall of the first insulating film in a self-aligned manner by an RIE (reactive ion etching) method, and two types of impurity well regions provided in the semiconductor substrate are formed on the sidewall of the first insulating film. 9. Therefore, the element isolation region is formed by selective oxidation.
Because it can be formed without using the so-called LOCOS method, that is, it can be formed into a structure without bird's beaks that cause stress, it is possible to achieve high integration by forming fine device regions, and high integration by improving the withstand voltage of the gate oxide film. In addition, the second insulating film forms the step of the first insulating film into a side wall. 9 Furthermore, by forming an etching stopper film, the film warping of the insulating film for forming the element isolation region can be minimized by forming an etching stopper film. By reducing the capacitance of the device, it is possible to increase the speed.9 Furthermore, by forming an impurity well region in the self-alignment line using a trench filled with an insulating film, it is possible to achieve high integration. ．． That is, it is possible to obtain a semiconductor device that enables the formation of extremely high-performance, highly reliable, high-speed, and highly integrated semiconductor integrated circuits.9 [Embodiments] The present invention will be specifically explained below with reference to illustrated embodiments. FIG. 1 is a schematic side sectional view of a first embodiment of the semiconductor device of the present invention, FIG. 2 is a schematic side sectional view of the second embodiment of the semiconductor device of the present invention, and FIG. 3 is a schematic side sectional view of the semiconductor device of the present invention. A schematic side sectional view of the third embodiment of the device, FIGS. 4(a) to (
d) is a process cross-sectional view of an embodiment of the manufacturing method for a semiconductor device of the present invention.9 The same objects are indicated by the same reference numerals throughout the figures. 1 is a schematic side sectional view of a first embodiment of a semiconductor device, where 1 is tO cm
P-type silicon (Si) substrate of approximately 10 cm
3 is a p-type well region of about 10 cm, 3 is an n-type well region of about 10 cm, 4a is a trench for impurity well head isolation, 4b is a third insulating film for burying the trench, 5a
5b is a first insulating film for forming an element isolation region with a width of about 0.8F, and 5b has a width of 0.8F. The second one for element isolation/area formation.
insulating film ((1!L wall insulating film), 5C is a base oxide film of about 20 nm, 6 is an n+ type source drain region of about 10'' CI-3, 7 is a p+ type source drain region of about 10 cm) , 8 is a gate oxide film of about 20 nm, 9 is a gate electrode of about 300 nm, 10 is a block oxide film of about 1 Son, 11 is a phosphosilicate glass (PSG) film of about 0.87 nm, and 12 is a phosphosilicate glass (PSG) film of about 0.87 nm. A1 wiring of about 1 Pl is shown. In the figure, a first insulating film 5a is selectively provided on a p-type silicon (Si) substrate 1, and the first insulating film 5a
A second insulation B is applied to the self-line by RIE method on the side wall of
sb is provided, and an element isolation region is formed by the first insulating film 5a and the second insulating film 5b. Further, the p-type well region 2 and the n-type well region 2 are formed by the trenches 4a filled with the third insulating film 4b, which are selectively provided in the p-type silicon (Si) substrate 1 under the first insulating film 5a. Region 3 is formed separately. A trench 4 in which adjacent n-type well regions 3 are filled with a third insulating film 4b
The separation by a indicates that the potentials applied to each n-type well region 3 are different.
Therefore, the element isolation region is subjected to LOCOS by selective oxidation.
Because it can be formed without using a method, that is, it can be formed into a structure that does not have a bird's beak that causes internal stress.
High integration is achieved by forming fine device regions, and high performance is achieved by improving the breakdown voltage of gate oxide films.
Electrons or holes are less likely to be trapped, and carrier life can be improved, thereby making it possible to achieve high reliability. Further, since the first insulating film step difference can be relaxed by the second insulating film formed on the sidewall, it is possible to form a wiring body with a good stepping force barrier. Furthermore, by forming an etching stopper film, the film deterioration of the insulating film for forming the element isolation region can be minimized, and the capacitance of the wiring body can be reduced, thereby increasing speed. Furthermore, high integration can be achieved by forming an impurity well region in a self-alignment line using a trench filled with an insulating film. In this example, a channel stopper region is not formed, and rather high concentration p-type and n-type well regions also serve this role. 7 FIG. 2 is a schematic side sectional view of a second embodiment of the semiconductor device of the present invention, where 1 to 4b and 5b to 12 are the same as in FIG. 1, and 5ar+ is phosphosilicate glass for forming an element isolation region. (P
SG) film, 5ap is a borosilicate glass (BSG) film for forming an element isolation region, 13 is an n-type channel stopper region, 1
4 indicates a p-type channel stopper region. In the figure, the first insulating film forming the element isolation region is composed of a phosphosilicate glass (PSG) film 5an containing n-type impurities and a borosilicate glass (BSG) film 5ap containing p-type impurities. The same ellipse as in FIG. 1 except that an n-type channel stopper region 13 is formed under the phosphosilicate glass (PSG) film San, and a p-type channel stopper region 14 is formed under the borosilicate glass (BSG) film Sap. It forms a structure. In addition to the effect shown in Figure 1, since the n-type and p-type channel stopper regions can be formed independently, the n-type and p-type
Since the impurity concentration in the mold well region can be formed at a low concentration,
This reduces the junction capacitance and increases the mobility, which is further advantageous for speeding up. FIG. 3 is a schematic side sectional view of the third embodiment of the semiconductor device of the present invention, and 1 to 12 are It shows the same thing as Figure 1. In the figure, a first insulating film 5a forming an element isolation region is formed including a third insulating film 4b directly above a trench 4a provided by burying a third insulating film 4b. The same structure as in FIG. 1 is formed except that the second insulating film 5b formed on the side wall of the first insulating film 5a is the same as the third insulating film 4b and is formed at the same time. There is. In addition to the effect shown in FIG.
Forming an insulating film and forming a trench> Since the element forming region and the impurity well region can be formed in self-alignment lines, it is further advantageous for high integration.

Next, an embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 4(a) to 4(d) and FIG. 1.

Figure 4(a) By applying conventional techniques, p-type silicon (S)
i) Sequentially grow an oxide film and a nitride film on the substrate 1. Next, using a normal photolithography technique, the nitride film, oxide film, and p-type silicon (Si) substrate 1 are selectively formed.
A trench 4a having a depth of about 5P is formed by drilling a hole. Next, insulation Jl! is performed using the chemical vapor phase method. (Oxidation!
), and a chemical vapor deposition insulating film (FyA oxide) 4b is buried in the trench 4a by anisotropic dry etching. Then, using normal photolithography techniques,
Resist (not shown) and trench-buried insulating film 4b
Using this as a mask layer, boron ions are implanted to define a p-type well region 2, and phosphorus ions are implanted to selectively define an n-type well region 3, respectively. Next, a p-type well region 2 and an n-type well region 3 having a desired depth are formed by running at a high temperature.
form. Next, the nitride film and oxide film are removed by etching.

FIG. 4(b) Next, an oxide film (base oxide film) 5c, a chemical vapor phase oxide film (first insulating film) 5a, and a nitride M (film edge prevention film) 5d
The precepts will be given in order. Next, using a normal photolithography technique, the nitride film 5d, chemical vapor deposition oxide film (first insulating film) 5a and oxide M (base oxidation!) 5 are selectively formed.
The first insulating film 5a constituting a part of the element isolation region is formed by sequentially etching away the first insulating film 5a. Next, a chemical vapor deposition oxide film is grown to form a second insulating film 5b that covers a part of the element isolation region, and anisotropic dry etching is performed using the RIE method to form a second insulating film 5b on the sidewalls of the first insulating film 5a. Next, a second insulating film (sidewall insulating film>5b) is left on the self-line to form an element isolation region. FIG. 4(C) Next, a gate oxide film 8 and a polycrystalline silicon film are sequentially grown. Using a technique, the polycrystalline silicon film is patterned to form a gate electrode 9. FIG. 4(d) Next, using a normal photolithography technique, a resist (not shown) and a first insulating film are formed. 5a, second insulating film (
(!11 Using the wall insulating film>5b and the gate electrode 9 as a mask layer, arsenic is ion-implanted to selectively form the n-type source/drain region 6, and boron is ion-implanted to selectively form the p-type source/drain region 7. Next, the film edge prevention film (nitride film) 5d is removed by etching with boiled phosphoric acid.Then, unnecessary portions of the gate are oxidized f.
yJ. 8 is removed by etching. Next, a blocking filO oxide film and a phosphosilicate glass (PSG) film 11 are sequentially grown. Next, a slightly high temperature process is performed to form n+ type source/drain regions 6 and p+ type source/drain regions 7 having desired depths. Next, by applying conventional techniques, electrode contact windows, AI wiring 12, etc. are formed, and the semiconductor device is completed. In the above manufacturing method, a film anti-slip film (nitride film) is provided on the first insulating film, but when forming the second insulating film on the side wall of the first insulating film, If it is possible to perform etching that leaves a sufficient amount of the film, the JlK (nitride film) to prevent film slippage may be omitted. In addition, an anti-slip film (
The nitride film) may be left as is and used as a part of the first insulating film for forming the element isolation region. In the above embodiment, a base oxide film is provided under the first insulating film, but the present invention can be achieved without providing the base oxide film. As shown in the embodiments above, according to the semiconductor device of the present invention, the element isolation region can be formed by selective oxidation without using the so-called LOCOS method, that is, it can be formed in a structure in which there is no bird's beak that causes stress. As a result, it is possible to achieve higher integration by forming a fine device area, higher performance by improving the withstand voltage of the gate oxide film, and higher reliability by improving the lifetime of carriers by making it difficult for electrons or holes to be trapped. It can be done. Further, since the step of the first insulating film can be relaxed by the second insulating film forming the sidewall, it is possible to form a wiring body with a good stepping force barrier. Further, since the film burr of the insulating film for forming the element isolation region can be minimized by forming the etching stopper film, the capacitance of the wiring body can be reduced, thereby increasing the speed. Furthermore, high integration can be achieved by forming an impurity well region in a self-alignment line using a trench filled with an insulating film. [Effects of the Invention] As described above, according to the present invention, in a MIS type semiconductor device, an element isolation region is formed in a first insulating film and a second insulating film provided in a self-alignment line on a side wall of the first insulating film. and an insulating film, and the impurity well region is defined by a trench filled with the third insulating film, so that it is possible to form a structure in which no bird's beak exists, resulting in miniaturization of the element region. Improvement of gate oxide film withstand voltage and carrier life is achieved by forming a wiring body with a good step force barrier by forming a twill phase with a second insulating film formed on the sidewall of the first insulating film step, and by forming a wiring body with a good step force barrier. It is possible to increase the speed by minimizing the film distortion of the insulating film and reduce the capacitance of the wiring body, and it is also possible to achieve high integration by forming the boundary of the impurity well region with a fine trench. In other words, it is possible to obtain a semiconductor device that enables the formation of extremely high-performance, highly reliable, high-speed, and highly integrated semiconductor integrated circuits9.

[Brief explanation of drawings]

FIG. 1 is a schematic side sectional view of a first embodiment of the semiconductor device of the present invention, and FIG. 2 is a schematic side sectional view of a second embodiment of the semiconductor device of the present invention.
FIG. 3 is a schematic side sectional view of the third embodiment of the semiconductor device of the present invention, and FIGS.
(d) is a process cross-sectional view of an embodiment of the manufacturing method for a semiconductor device of the present invention, and FIG. 5 is a schematic side cross-sectional view of a conventional semiconductor device. In the figure, 1 is a p-type silicon (Si) substrate; 2 is a p-type well region, 3 is an n-type well region, 4a is a trench for impurity well region isolation, 4b is a third insulating film for filling the trench, 5a is a first insulating film for forming an element isolation region, 5an 5ap is phosphosilicate glass (PSG) for forming element isolation regions J&I, 5ap is borosilicate glass (BSG) for forming element isolation regions
) film, 5b is a second insulating M (side wall insulating film) for forming an element isolation region, 5C is a base oxide film, 5d is a film-skipping film (nitride film), 6 is an n-type source/drain region, 7 10 is a p-type source drain region, 8 is a gate oxide film, 9 is a gate electrode, 10 is a blocking oxide film, 11 is a phosphosilicate glass (PSG) film, 12 is an AI wiring, 13 is an n-type channel stopper region, 14 indicates a p-type channel stopper region.

Claims (4)

[Claims] (1) An element isolation region is formed by a first insulating film selectively provided on a semiconductor substrate and a second insulating film provided on a side wall of the first insulating film, and A semiconductor device characterized in that an impurity well region is defined by a trench filled with a third insulating film that is selectively provided in the semiconductor substrate under an insulating film. (2) The first insulating film contains impurities, the second and third insulating films do not contain impurities, and the semiconductor substrate directly below the first insulating film has an impurity channel stopper region. 2. A semiconductor device according to claim 1, further comprising a semiconductor device. (3) The first insulating film forming the element isolation region is formed including the third insulating film directly above the trench provided by burying the third insulating film. A semiconductor device according to claim 1. (4) The semiconductor device according to claim 1, wherein the first insulating film is composed of a plurality of different insulating films.