JPH0382033A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize a refined element region and improve both breakdown strength of a gate oxide film and the life-time of carriers and form a gate electrode wiring body which is superior in step coverage and contrive speeding up and the like through increase of transfer conductance by providing a conductive film which is in contact with a gate electrode at the side wall of a field insulating film directly under the gate electrode and further, taking similar steps. CONSTITUTION:This device is equipped with: a field insulating film 4 that is provided selectively on a semiconductor board 1; gate oxide films 7 that are provided selectively at regions where the field insulating film 4 is not formed; a gate electrode 9 that is provided selectively on both gate oxide films 7 and a field insulating film 4; an electric conductive film 8 that is provided at the side walls of the field insulating film 4 directly under the electrode 9 and moreover, is in contact with the gate electrode 9. Further, for example, an element isolation region is formed by the thick field oxide film 4 having stepped parts and, in the gate electrode wiring body 9 which is extending on the field oxide film 4, the electric conductive film 8 is provided according to a self-alignment process with anisotropic dry etching at the sidewalls of the field oxide film 4 directly under the gate electrode 9; besides, it is formed into a construction which comes directly into contact with the gate electrode 9.

Description

[Detailed Description of the Invention] [Summary] An element forming region is defined by a thick field insulating film having steps, and a gate electrode provided in the element forming region via a gate oxide film extends over the field insulating film. The conductive film is formed by anisotropic dry etching on the side wall of the field insulating film that intersects with the gate electrode, and is in direct contact with the gate electrode. It is possible to miniaturize the device area, improve the breakdown voltage of the gate oxide film, and improve the carrier life by forming a structure in which the gate electrode wiring body has good step coverage by reducing the step difference in the field insulating film by forming a conductive film on the sidewall. Formation of an upper layer wiring body with good step coverage is achieved by making the sidewall conductive film a part of the gate electrode. A semiconductor device that enables higher speeds by increasing transfer conductance.

[Industrial Field of Application] The present invention relates to a MIS type semiconductor device, and particularly to a semiconductor device that enables the formation of a high-speed semiconductor integrated circuit having an element isolation region without bird's beaks.

Conventionally, element isolation regions of semiconductor integrated circuits have been formed using LOCO, which is a method of selective oxidation using a nitride film, with the aim of alleviating the step difference in the element isolation region and forming a flat upper layer wiring body.
However, as the degree of integration has increased dramatically, it has become difficult to miniaturize the device formation area due to the bird's beak that induces stress that inevitably occurs with the LOCO8 method. Problems such as deterioration of breakdown voltage, deterioration of life due to easy trapping of electrons or holes, and deterioration of transfer conductance have become prominent, and these problems are becoming a hindrance to higher integration. Therefore, there is a need for a means for realizing highly integrated element isolation in which bird's beak does not exist and the level difference in the element isolation region is reduced.

[Prior Art] FIG. 4 is a schematic side sectional view of a conventional semiconductor device. 51
52 is a p-type silicon (Si) substrate, 52 is an n-type well region, 53 is an n-type well region, 54 is a p-type channel stopper region, 55 is an n-type channel stopper region, 56 is a field oxide film, and 57 is an n-type well region. type source drain region, 5
8 is a p-type source/drain region, 59 is a gate oxide film,
60 is a gate electrode, 61 is a block oxide film, 62 is a phosphosilicate glass (PSG) film, and 63 is an AI wiring.

In the figure, a p-type silicon (Si) substrate 51 is selectively provided with an n-type well region 52 and an n-type well region 53, and the n-type well region 52 has an N-channel transistor and the n-type P channel transistors are selectively formed in each well region 53. The element isolation region is formed by the LOCO3 method, and has a bird's beak that contains stress. LOCO3
This method has the advantage that the step difference in the element isolation region can be reduced by bird's beak stitching, and a wiring body with good step coverage can be formed. There are disadvantages such as the breakdown voltage of the thinned gate oxide film deteriorates, the lifetime deteriorates due to easy trapping of electrons or holes, and the channel width decreases, resulting in a decrease in transfer conductance.

[Problems to be Solved by the Invention] The problems to be solved by the present invention are that, as shown in the conventional example, it is difficult to miniaturize the element formation region due to the presence of bird's beaks in the LOCO8 method, and it is difficult to reduce the thickness of the film. It was not possible to improve the problems such as deterioration of the breakdown voltage of the gate oxide film, deterioration of the lifetime due to easy trapping of electrons or holes, and reduction of transfer conductance due to narrowing of the channel width. 9 [Means for solving the problem] The above problem is that the field insulating film is selectively provided on the semiconductor substrate, and the area where the field insulating film is not formed is selectively removed. a gate oxide film provided on the gate oxide film, a gate electrode selectively provided on the gate oxide film and the field insulating film, and a gate electrode provided on the side wall of the field insulating film directly below the gate electrode and in contact with the gate electrode. The problem is solved by the semiconductor device of the present invention, which includes a conductive film.

[Function] That is, in the semiconductor device of the present invention, an element formation region is defined by a thick field insulating film having steps, and a gate electrode provided in the element formation region via a gate oxide film extends over the field insulating film. A conductive film is formed by anisotropic dry etching on the side wall of the field insulating film that intersects with the gate electrode, and is in direct contact with the gate electrode. Therefore, since the element isolation region can be formed without using the so-called LOCO9 method by selective oxidation, that is, it can be formed in a structure without bird's beaks that cause stress, high integration can be achieved by forming fine element regions. High performance can be achieved by improving the breakdown voltage of the gate oxide film, and high reliability can be achieved by making it difficult for electrons or holes to be trapped and improving carrier life. In addition, the step difference in the field insulating film can be alleviated by the conductive film formed on the sidewall, and high reliability can be achieved by forming a gate electrode wiring body with good step coverage. High reliability can be achieved by forming an upper layer wiring body with good step coverage, which can be relaxed by an insulating film, and by making the sidewall conductive film part of the gate electrode, it is possible to improve channel width reduction and increase transfer conductance. It is also possible to speed up the process. That is, it is possible to obtain a semiconductor device that enables the formation of extremely high-performance, highly reliable, highly integrated, and high-speed semiconductor integrated circuits.

[Examples] The present invention will be specifically described below with reference to illustrated examples. 1(a) and (b) are schematic diagrams of a first embodiment of the semiconductor device of the present invention, and FIGS. 2(a) and (b) are schematic diagrams of a second embodiment of the semiconductor device of the present invention, Figure 3(a)-(
e) is a process sectional view of an embodiment of the manufacturing method for a semiconductor device of the present invention.

Identical objects are indicated by the same reference numerals throughout the figures.

FIG. 1 is a schematic diagram of a first embodiment of a semiconductor device of the present invention using a p-type silicon substrate, with (a) showing a side sectional view and (b) showing a plan view.

1 is a p-type silicon (Si) substrate of about 10 c-,
2 is a p-type well region of about 1616 cr3, 3 is 101
6C1-3 in region, 6 is a p-type source drain region of about 10 c-, 7 is a gate oxide film of about 20 n-,
8 is a sidewall conductive film with a width of about 0.3/Jl, 9 is 300 n
10 is a block oxide film of about 50n-, 11 is a phosphosilicate glass (PSG) of about Q8/Jl
) film, 12 shows an AI wiring of about 1P-9 In the figure, a p-type well region 2 and an n-type well region 3 are selectively provided on a p-type silicon (Si) substrate 1. , an N-channel transistor is selectively formed in the p-type well region 2, and a p-channel transistor is selectively formed in the n-type well region 3. The element isolation region is formed by a thick field oxide film 4 with steps, but in the gate electrode wiring body 9 extending on the field oxide film 4, there is a difference in the field oxide film 4@wall directly under the gate electrode 9. The conductive film 8 is provided on the self-line by directional dry etching, and is formed in a structure in direct contact with the gate electrode 9.9 Therefore, the element isolation region can be formed by selective oxidation without using the LOCOS method. In other words, it is possible to form a structure that does not have bird's beaks that cause stress, so it is possible to achieve high integration by forming a fine device area, high performance by improving the breakdown voltage of the gate oxide film, and it is difficult for electrons or holes to be trapped. This makes it possible to improve reliability by improving carrier life. In addition, the field oxide film step can be alleviated by the conductive film formed on the sidewall, and high reliability can be achieved by forming a gate electrode wiring body with good step coverage, since the sidewall conductive film can be made a part of the gate electrode. It is also possible to improve the reduction in channel width and increase the transfer conductance, thereby making it possible to increase the speed.

FIG. 2 is a schematic diagram of a second embodiment of the semiconductor device of the present invention, in which (a) shows a side sectional view and (b) shows a plan view. 1 to 12 are the same as in FIG. 1, 13 is a sidewall insulating film, and 14 is a base oxide film.

In this figure, the structure is the same as that in FIG. 1, except that an insulating film 13 (including a base oxide film 14) is provided on the sidewalls of the stepped gate electrode 9 and field oxide film 4. In addition to the same effect as shown in Fig. 1, since all the stepped portions are relaxed by the sidewall conductive film or the sidewall insulating film, it is possible to form an upper layer wiring body with even better step coverage, making it possible to achieve high reliability. .

Next, an embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 3(a) to 3(e) and FIG. 2(a).

Figure 3(a) By applying conventional techniques, p-type silicon (S)
i) growing an ion implantation oxide film (not shown) on the substrate 1; then using conventional photolithography techniques;
Using a resist (not shown) as a mask layer, boron ions are implanted to selectively define the p-type well region 2, and phosphorus ions are implanted to selectively define the n-type well region 3, respectively. p-type well region 2 with a depth of
Then, the oxide film for ion implantation, which forms the n-type well region 3, is removed by etching. Next, a thick thermal oxide film 4 is grown. 9 Next, using a conventional photolithography technique and using a resist (not shown) as a mask layer, the thick thermal oxide film 4 is selectively etched to form an element isolation region (field oxide film). 4) and define an element region.

FIG. 3(b) Next, a gate oxide film 7 and a first polycrystalline silicon film are sequentially grown.Then, the polycrystalline silicon film is anisotropically dry etched to form a self-line polycrystalline film only on the sidewalls of the field oxide film 4. A silicon film (sidewall conductive film) 8 is left.

Figure 3 (C) Next, a second polycrystalline silicon film is grown.

Then, it was annealed at 900°C in a N2 atmosphere for about 20 minutes.
The interface level of the gate oxide film 7 is restored. Next, using a normal photolithography technique, the second polycrystalline silicon film is etched using a resist (not shown) as a mask layer, and a gate electrode 9 is formed. do. At this time, over-etching is performed to completely remove the sidewall conductive film 8 remaining on the sidewall of the field oxide film 4 except directly below the gate electrode 9.

FIG. 3(d) Next, using a normal photolithography technique and using a resist (not shown), gate electrode 9, and field oxide film 4 as mask layers, arsenic ions are implanted to form n-half type source/drain regions 5. , boron ions are implanted to selectively define p-type source/drain regions 6, respectively.

FIG. 3(e) Next, unnecessary portions of the gate oxide film 7 are removed by etching 9
Next, a base oxide film 14 and a chemical vapor deposition oxide film are sequentially grown.9 Next, anisotropic dry etching is performed to leave a sidewall oxide film 13 on the sidewalls of the stepped field oxide film 4 and gate electrode 99. Oxide film for block 10, phosphosilicate glass (PSG)
The film 11 is sequentially grown (9) and then subjected to a slightly high temperature treatment to form an n-half type source/drain region 5 and a p-type source/drain region 6 having desired depths.

Next, by applying ordinary techniques, electrode contact windows, AI wiring 12, etc. are formed, and the semiconductor device is completed.

In the above embodiment, a sidewall insulating film for mitigating the step was formed independently on the sidewall of the field oxide film and the gate electrode with the step, but the so-called LDD (Lightly
A so-called sidewall insulating film, which is formed on the sidewall of the gate electrode when forming a doped drain (doped drain) II transistor, may be simultaneously formed on the sidewall of the horizontally laid field oxide film. A somewhat high concentration of p without forming a special channel stopper region.
This role is also played by the type and n-type well regions,
As shown in the nine or more embodiments, which may be formed by other methods, according to the semiconductor device of the present invention, the element isolation region can be formed by selective oxidation, without using the so-called LOCO3 method. Because it can be formed into a structure that does not have bird's beaks that cause stress, it is possible to achieve higher integration by forming fine device regions, higher performance by improving the breakdown voltage of the gate oxide film, and by making it difficult for electrons or holes to be trapped. High reliability can be achieved by improving carrier life. In addition, the field oxide film step can be alleviated by the conductive film formed on the sidewall, and the gate electrode wiring body has good step coverage. Furthermore, the field oxide film and the gate electrode wiring body step can be alleviated by the insulating film formed on the sidewall, and the step coverage is improved. High reliability is achieved by forming an upper-layer interconnection body with good performance, and by making the sidewall conductive film part of the gate electrode, it is possible to improve the reduction in channel width and increase the transfer conductance, which enables higher speeds. You can also do that.

[Effects of the Invention] As described above, according to the present invention, in a MIS type semiconductor device, the step of the field oxide film at the location where it intersects with the gate electrode is alleviated by the conductive film formed on the side wall, and the side wall conductive film and the gate Since the electrodes are directly connected, the device isolation region can be formed in a structure without bird's beaks, resulting in miniaturization of the device region, improvement of gate oxide film breakdown voltage, and improvement of carrier life. Formation of a gate electrode wiring body with good step coverage due to the step difference being alleviated by the conductive film formed on the fs wall, and good step coverage due to the step difference in the field insulating film and the gate electrode wiring body being able to be alleviated by the insulating film formed on the side wall. It is possible to speed up the formation of the upper layer wiring body by increasing the transfer conductance by making the sidewall conductive film part of the gate electrode. That is, it is possible to obtain a semiconductor device that enables the formation of extremely high-performance, highly reliable, highly integrated, and high-speed semiconductor integrated circuits.

[Brief explanation of drawings]

FIGS. 1(a) and 1(t) are schematic diagrams of a first embodiment of the semiconductor device of the present invention, and FIGS. 2(a) and (b) are schematic diagrams of a second embodiment of the semiconductor device of the present invention. , Figure 3 (a
) to (e) are process cross-sectional views of an embodiment of the manufacturing method for a semiconductor device of the present invention, and FIG. 4 is a schematic side cross-sectional view of a conventional semiconductor device. In the figure, 1 is a p-type silicon (Si) substrate, 2 is a p-type well region, 3 is an n-type well region, 4 is a field oxide film, 5 is an n-type source train region, 6 is a p-type source drain 7 is a gate oxide film, 8 is a sidewall conductive film, 9 is a gate electrode, 10 is a block oxide film, 11 is a phosphosilicate glass (PSG) film, 12 is an A1 wiring, 13 is a sidewall insulating film, 14 is a base Shows oxide film.

Claims (2)

[Claims] (1) A field insulating film selectively provided on a semiconductor substrate, a gate oxide film selectively provided in an area where the field insulating film is not formed, and a gate oxide film selectively provided on the gate oxide film and the field insulating film. 1. A semiconductor device comprising: a gate electrode provided on the field insulating film; and a conductive film provided on a side wall of the field insulating film directly below the gate electrode and in contact with the gate electrode. (2) An insulating film having a cross-sectional shape similar to that of the conductive film is provided on the side wall of the field insulating film other than directly under the gate electrode and the side wall of the gate electrode. 1. Semiconductor device described in Section 1.