TW492154B - Manufacturing method of self-aligned BiCMOS - Google Patents

Abstract

The present invention provides a method for forming PN junction of bipolar junction transistor (BJT) by self-aligning. The method comprises first sequentially forming a screen oxide layer, a stop layer, and a dielectric layer on the surface of a substrate, and forming an opening in the dielectric layer to reach the stop layer; next, forming a spacer on the sidewall surface of the opening, and implanting a first conductive type dopant by self-aligning on the surface of the substrate via the opening, thereby forming a first doped region; subsequently, etching the shielding oxide layer at the bottom of the opening to expose the substrate at the bottom of the opening; then, depositing a first silicon layer and implanting a second conductive type dopant in the first silicon layer; next, performing a thermal process to drive the dopant of the first doped region into the substrate, thereby forming a base diffusing region and make the dopant implanted in the first silicon layer diffuse to the substrate, thereby forming a emitter diffusing region; next, depositing a second silicon layer on the first silicon layer and filling up the opening, and back-etching the second silicon layer and the first silicon layer; and finally, removing the dielectric layer and forming a base contact region on the substrate surface inside the base diffusing region.

Description

492154 V. Description of the invention (1) Field of the invention The present invention provides a self-alignment (se 1 f-a 1 igned) to form a bipolar transistor (BJTH PN junction (PN j unc ti on Background Description Bipolar Junction Transistor, commonly referred to as BJT, is the most important semiconductor element in modern times ^. The dagger consists of two sets of very tight ρ η connections (juncti ο η) Three-terminal (Three Terminal) components. These three terminals are called Emitter and Base Collector, respectively. The intermediate point. Because the two carriers are connected to the transistor system and the π hole, the two carriers have high speed and provide a larger current in the space. Sub-connected transistor and complementary transistor BiCMOS structure has compensated for the operating speed of the transistor. However, the dual quantity is a major obstacle to the application of the connected transistor due to the increase in the integration of the device. At the same time, the use of "electronics" Electrns (Carr iers) are used to conduct current, and the corpse can have the advantages of a smaller space: current. Therefore, the dual-way combination of the body (CMOS) is proposed to improve the standard $ 5 carrier. When the component consumes a large amount of energy, the heat dissipation problem becomes a dual-load number. In addition, at present, double-carrier days are being produced.

Page 5 492154 5. In the description of the invention (2), the step of forming the mask is used multiple times to combine the standard bipolar transistor and CMOS transistor processes, so the complexity of the process will be greatly increased. . Please refer to Figs. 1 to 5, which are schematic diagrams of a conventional method for making a double-carrier complementary transistor. The conventional method for making a double-battery complementary transistor is to add a double-battery element to a traditional complementary transistor process by using additional masking steps, or to add a complementary transistor to a traditional double-battery transistor. Crystal process. As shown in FIG. 1, a conventional method for making a double-carrier complementary transistor is to first provide a semiconductor wafer i0 including a p-type silicon substrate 12, and the silicon substrate 12 is at least divided into a first 16. Second 17 and third base area 18. The first substrate region 16 is used to form PMOS in CMOS, the second substrate region 17 is used to form NMOS in CMOS, and the third substrate region 18 is used to form BJT. At the same time, a plurality of field oxide regions (Field Oxide Regions) 14a, 14b, 14c, 14d, 14e, 14f, 1 4g, and 14h are formed in each base region to separate the active area regions 15a, 15b. 15c, 15d, 15e. In the silicon substrates of the first 16 and third substrate regions 18, N-type wells 20, 22 are formed, so when an N-type ion implantation process is performed to form N-type wells 20, 22, A mask must be formed over the second base region 17 to avoid N-type implantation. As shown in FIG. 2, a first p-type ion implantation process is performed next to form a channel under the field oxidation region 1 4 c and 1 4 d of the second base region 17.

492154 V. Description of the invention (3) Channel stop 24, and a base 26 of the bipolar transistor is formed in the third substrate region 18. During the P-type ion manufacturing process, a mask must be formed over the active regions 15 b, 15 c, and the first base region 16 to avoid P-type ion implantation. Subsequently, as shown in FIG. 3, gate structures 28, 30 of PM0S and NMOS transistors are formed on the first 16 and second substrate regions 17 respectively. It includes a gate dielectric layer, a doped polycrystalline silicon layer, a metal petrified layer, and a capping insulating layer. Then, a second p-type ion implantation process is performed to form the lightly doped anode (l D D) 3 2 of the P M 0 S in the first substrate region. As shown in FIG. 4, a sidewall 37 is formed around each of the gate structures 28, 30 of the PM0 ^ NM0s, and then an n-type ion implantation process is performed to form the N in the first base region 17 The source and inferior poles of M 0 S 38, and the emitter 36 of the double-carrier transistor is formed in the third base region 18, and the double-carrier transistor is formed in the active region 15c. Collector contact area 40. Finally, as shown in FIG. 5, a cover layer (not shown) is formed on the second substrate region 17 and the active regions 15 c and 15 d to perform a third P-type ion implantation process on the first substrate. Region i 6 forms the source and drain 44 of the PMOS, and forms a base contact region 46 of the bipolar transistor in the third base region 18 to complete the bipolar complementary transistor. Process. As the conventional method for making a double-battery complementary transistor is to use multiple steps to form a mask, a standard double-battery transistor and a CMOS transistor are manufactured.

Page 7 492154 V. Description of the invention (4) Combining with Israel will not only increase the complexity of the process, but also may cause damage and affect the electrical performance of the component during the process of repeated formation and removal of the mask. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for self-aligning to form a PN junction in a bipolar junction transistor (BJT), in order to simplify the conventional double carrier. The complexity of the complementary transistor process. Make a masking layer on this layer, and a layer on it. Then the substrate surface is doped. Out of the second conductive base of the opening, the best real oxidation of the second stone layer invented in the second base expansion screen (screen of the dielectric layer shaped on the side wall of the opening and self-aligning implantation then Wet etching the base-type dopant at the bottom in the dopant interspersed region in the first impurity region, and planting to form an emitter on the first silicon layer and the surface of the first stone lane alley sequentially An oxide layer, a stop layer, and a dielectric form an opening pass through the stop to form a sidewall, and pass through the opening to the first conductive type dopant to form the masking oxide at the bottom of the first opening. Layer to expose, then deposit a first silicon layer and implant into a silicon layer. A thermal process is then performed to infiltrate into the substrate to form a base that diffuses the dopant that has penetrated into the first Shixi layer towel into the (enntter) diffusion region. _ Is then deposited, and the opening is filled, and then the layer is etched back. Remove the dielectric layer and remove it from the base

492154 V. Description of the invention (5) A base contact region is formed on the surface of the β-Hai substrate in the expanded area. Because the present invention is to form a base and an emitter of a bipolar transistor using a self-alignment method after the complementary transistor (CM0s) is formed. Therefore, compared with the conventional method for making a double-carrier complementary transistor, the present invention can simplify the photomask process several times, and can avoid the substrate surface from being damaged by the plasma, and reduce the B J T leakage current. For a detailed description of the invention, please refer to FIG. 6 to FIG. 11. FIG. 6 to FIG. 11 show a PN in a bipolar junction transistor (BJT) formed by self-aligning (sel f-al igned) of the present invention. Schematic diagram of the PN junction method. As shown in FIG. 6, the present invention first provides a semiconductor wafer 50 including an N-type epitaxial silicon (epita X ia 1 si 1 ic〇η) substrate 5 2, and a MOS transistor 54 is formed on the semiconductor wafer 50. Then, on the surface of the substrate 52, a screen oxide layer 56 composed of 'monoxide oxide fragments', a stop layer 58 composed of nitride stones, and a stop oxide layer composed of nitride stones and butterflies are sequentially formed on the surface of the substrate 52. Dielectric layer 60 ′ composed of borophosphosilicate glass (BPSG) or phosphosilicate glass (PSG). The stop layer 58 is between the shielding oxide layer 56 and the dielectric layer 60. 0

492154 V. Description of the invention (6) Then, as shown in Figure 7 + r · wrs ^, a (0Pening) 61 access stop layer is formed in the dielectric layer 60, and then a spacer material layer is formed (not shown by the opening) The dielectric layer composed of silicon nitride is 60. 56, with an opening of 61 angstroms, covering the opening. 61 Bottom: the sidewall and the opening is about 500 to 1500. Then the sidewall sub-material layer is dry-etched until the oxidation is masked. The side wall of Jub forms a side wall 62, as shown in Fig. 8. Next, a type dopant is formed on the surface of the substrate 52 through the opening 6 1 to form a first doping J 63 on the surface of the substrate 52: The second layer 5 is wet-etched with a solution containing II gas acid (hydrofluoric aC1d) to etch the oxide layer 56 at the bottom of the opening 61 to expose the substrate 52 at the bottom of the opening 61. Then, a second silicon layer 64 is deposited to cover the bottom of the opening 61 A dielectric layer 60 other than the sidewall member 62 and the opening 61 is implanted with an N-type dopant in the first silicon layer M, as shown in FIG. 9. Then, a thermal process is performed to make the first doped region a63. The dopant enters the substrate 52 to form a base diffusion region 66 and implants the first silicon layer 64 The dopant diffuses into the substrate 52 to form an emi tter diffusion region 68. As shown in FIG. 10, a second silicon layer composed of amorphous silicon (am〇rph〇us sUic〇n) is deposited. 70 is on the first silicon layer 64 and fills the opening β. Then, the second silicon layer 70 and the first silicon layer 64 are etched, and the dielectric layer 20 is exposed. As shown in FIG. 11, the dielectric is removed. The layer 60 and a base contact region (not shown) are formed on the surface of the base diffusion '66 & 5 2 surface.

Page 10 492154 V. Description of the invention (7) As the method for forming PN junction in a double carrier transistor according to the present invention, firstly, an opening and a sidewall are formed on the substrate surface, and then the substrate is aligned on the substrate surface through the opening. A first conductive type dopant is implanted. Next, a silicon layer is deposited, and a second conductivity type dopant is implanted in the silicon layer, and then a thermal process is performed to infiltrate the first and second conductivity types into the substrate to form respective The base and the emitter of the bipolar transistor. Compared with the conventional method for making a double-carrier complementary transistor, the present invention can simplify the photomask procedure several times. At the same time, the step of masking the oxide layer at the bottom of the opening by wet etching can prevent the substrate surface from being damaged by the plasma and reduce the leakage current of B J T. The above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the present invention.

Page 11 492154 Brief description of the diagrams Brief description of the diagrams Figures 1 to 5 are schematic diagrams of the conventional method for making a double-carrier complementary transistor. FIG. 6 to FIG. 11 are schematic diagrams of a method for self-aligning to form a PN junction in a bipolar transistor according to the present invention. Explanation of symbols in the figure 10 Semiconductor wafer 12 Silicon substrate 14a '] 4h Field oxide region 15a', 15e Active region 16 First substrate region 17 Second substrate region 18 Second substrate region 20 > 22 N-type well 24 Channel block 26 Base 28 > 30 Gate structure 32 Lightly doped drain 36 Emitter 38 > 44 Source / drain 40 Collector contact field 46 Base contact area 50 Semiconductor wafer 52 Substrate 54 MOS transistor 56 Masking oxide layer 58 Stop layer 6 0 Dielectric layer 61 Open α 62 Side wall 64 First silicon layer 66 Base diffusion 68 Emitter diffusion region 70 First silicon layer

Page 12

Claims (1)

492154 VI. Application Patent Scope 1. A method of self-aligning (sel f-al igned) to form a PN junction (PN juncti ο η) in a bipolar junction transistor (BJT). The method includes the following: Steps: sequentially forming a screen oxide layer, a stop layer and a dielectric layer on a substrate surface, wherein the stop layer is interposed between the screen oxide layer and the dielectric layer; on the dielectric An opening is formed in the layer to reach the stop layer; a spacer material layer is formed to cover the bottom of the opening, the sidewall, and the dielectric layer outside the opening; dry-etching the sidewall material layer until the shielding An oxide layer to form a sidewall on the side wall of the opening; self-aligned implantation on the substrate surface through the opening; a first conductive type dopant to form a first doped region on the substrate surface; wet etching the The shielding oxide layer at the bottom of the opening exposes the substrate at the bottom of the opening; depositing a first silicon layer covering the bottom of the opening, the sidewalls, and the media outside the opening Layer; implanting a second conductive type dopant into the first silicon layer; performing a thermal process to make the dopant in the first doped region into the substrate to form a base diffusion Region, and the dopants implanted in the first silicon layer are diffused into the substrate to form an emitter diffusion region, and a second silicon layer is deposited on the first silicon layer. And fill the opening; etch back the second silicon layer and the first silicon layer to expose the dielectric Page 13 492154 CJ'VI VI '> 5 Amendments / Correction / Supplements VI. Patent application layer; remove the dielectric layer; and _ form a base contact area on the substrate surface in the base diffusion area (base contact region); wherein the step of wet-etching the shielding oxide layer at the bottom of the opening can prevent the substrate surface from being damaged by the plasma and reduce the leakage current of β j T. 2. The method of claim 1 in which the substrate is an epitaxial silicon substrate. For example, the method of claim 2 of the patent application range, wherein the epitaxial silicon substrate is the first conductive type. ^ The method of applying for item No. 丨 in the patent application, wherein the side wall is composed of lice silicon. The method of applying for the fourth item of the patent scope, wherein the thickness of the side wall is about 500 to 1. The material layer of 500 angstroms is the method of the first application for the patent scope, which is composed of oxide stone, and the stop layer is The masking oxide layer system composed of nitriding seconds (^ The following-": Method of 2nd item 1", wherein the dielectric layer is composed of a material: silicon dioxide, borophosphosilicate glass (borophosphosi1ί + ^ ΐ G g) 〇0 (phosphos i 1 i cat e 〇 1 s, BPS G) and lithophyllum glass > PSG) 〇8, such as the masking oxide layer in the scope of the patent application It is a solution using the eighth method, in which the open bottom is wet-etched. 3 Hydrofluoric acid (9) As in the scope of the patent application, the dopant concentration is greater than that of the method, in which the dopant concentration of the base contact area in the enlarged region. 1 0. If the scope of patent application 专利 is P type, the second conductive type is: type method. In which, the second silicon layer in the first-conductivity type system is composed of 11. As described in item i of the patent application scope, the amorphous silicon (amorphous silicon): 12 ·-seeded on a substrate Method for self-aligned fabrication of a bi-carrier complementary transistor (BiCMOS) 'The substrate includes a first region, a second region disposed on one side of the first region, and a third region, which are used to form — _ A transistor (NM0S), a P-type transistor (PM0S), and a bipolar transistor (BJT). The method includes the following steps: forming a gate structure in each of the first region and the second region; Performing an N implantation in the first region to form a source and a drain of the NMOS; Page 15 492154 6. The scope of the patent application sequentially forms a ^ shielding oxide layer, a stop layer, and a dielectric layer to cover the first region, the second region, and the third region; within the third region, An opening is formed in the dielectric layer to reach the stop layer; a side wall sub-material layer is formed to cover the bottom of the opening, the side wall, and the dielectric layer outside the opening; dry the side wall sub-material layer until the shielding oxide layer A side wall is formed on the side wall of the opening; a first conductivity type doped region is implanted on the surface of the substrate through the opening; wet etching of the shielding oxide layer at the bottom of the opening exposes the substrate; A first silicon layer covering the bottom of the opening and the sidewall; implanting a second conductivity type dopant in the first silicon layer; performing a thermal process to make the dopant concentration in the first conductivity type doped region Into the substrate to form a base diffusion region, and to diffuse a second conductivity type dopant implanted in the first silicon layer into the substrate to form an emitter diffusion region in the first silicon Deposited on the layer A second silicon layer and filling the opening; etch back the second silicon layer and the first silicon layer to expose the dielectric layer; remove the dielectric layer; and perform a P implantation on the first silicon layer Forming a source and a drain of the PMOS in a region, and forming a base contact region in the base diffusion region in the third region, Page 16 492154 VI. Application for patent scope The step of wet etching the shielding oxide layer at the bottom of the opening can prevent the substrate surface from being damaged by the plasma and reduce the leakage current of the B J T. 13. The method according to item 12 of the scope of patent application, wherein the substrate is an N-type substrate, and the first conductivity type is a P-type, and the second conductivity type is an N-type. 14. The method according to item 12 of the scope of patent application, wherein the substrate includes an N-type stupid crystal layer in the third region. 15. The method of claim 12 in the scope of patent application, wherein the first region includes a P-well region. 16. The method according to item 12 of the scope of patent application, wherein the side wall sub-material layer is composed of silicon nitride having a thickness of about 500 to 1500 angstroms. 17. The method according to item 12 of the scope of patent application, wherein the shielding oxide layer is composed of silicon dioxide, and the stop layer is composed of silicon nitride. 18. The method according to item 12 of the scope of patent application, wherein the dielectric layer is composed of one of the following materials: silicon dioxide, borophosphosilicate glass (BPSG), and phosphosilicate glass (PSG). 19. The method according to item 12 of the patent application scope, wherein the open bottom is wet-etched Page 17 492154 Page 18