GB2142185A

GB2142185A - Mosfet fabrication method

Info

Publication number: GB2142185A
Application number: GB08414923A
Authority: GB
Inventors: Alfred Charles Ipri; Lubomir Leon Jastrzebski
Original assignee: RCA Corp
Current assignee: RCA Corp
Priority date: 1983-06-22
Filing date: 1984-06-12
Publication date: 1985-01-09
Also published as: SE8403302L; DE3422495A1; GB8414923D0; IT8421384A0; FR2549294A1; IT1174192B; SE8403302D0; IT8421384A1

Abstract

A method for fabricating a plurality of relatively closely spaced MOSFETs is disclosed. A field oxide (54) having a plurality of vertical-walled apertures (56) is formed on the surface (52) of a silicon substrate (50), and a monocrystalline semiconductor region (58) is grown epitaxially within each aperture. MOSFETs are then formed in these semiconductor regions. <IMAGE>

Description

SPECIFICATION MOSFET fabrication method The present invention pertains to a method for fabricating Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) on a substrate. More particularly, it relates to a method for fabricating a plurality of N-channel MOSFET (NMOS), P-channel MOSFET (PMOS) or Complementary Symmetry MOSFET (CMOS) devices in a relatively dense configuration on a substrate surface.

When fabricating a plurality of MOSFET devices on the surface of a silicon substrate, the individual devices are typically laterally spaced from each other by a field oxide which comprises thermally grown silicon dioxide. Metal or polycrystalline silicon conductor lines typically overlie the field oxide between devices. To reduce the capacitance between the silicon substrate and the conductors which overlie the field oxide, it is desirable to have a relatively thick field oxide. This would permit higher voltages in the overlying conductors, and would permit greater device operating speed.

However, there are countervailing reasons for using a relatively thin field oxide between neighboring devices. A well identified problem, known in the semi-conductor industry as "bird beak" formation, occurs during the conventional fabrication of MOSFET devices on bulk silicon substrates. Bird beaks are characterized by a reduction in the thickness of the field oxide in the vicinity of the devices. They are undesirable because, among other things, they reduce the packing density of the devices and create a non-planar silicon/field oxide surface. The thicker the oxide, the more pronounced the bird beaks, the lower the device packing density, and the less planar the silicon/field oxide surface.

A method for fabricating a plurality of relatively closely spaced MOSFETs on a substrate comprises first forming a field oxide having a plurality of vertical-walled apertures, and then selectively forming a MOSFET within each aperture.

In the drawing: Figures 1 through 7 are cross-sectional views illustrating a portion of a conventional processing sequence used in fabricating a CMOS device.

Figures 8through 11 are cross-sectional views illustrating the processing sequence of the present invention.

Figures 1 through 7 represent a portion of a typical processing sequence for a conventional CMOS device.

As shown in Figure 1,a monocrystalline N type silicon substrate 10 having a major surface 12 is initially provided. A mask layer 14 is disposed on the major surface 12 and includes an opening 16 which exposes a preselected portion of the surface 12. A P type conductivity modifier, such as boron, is then implanted into the substrate, as shown at 18 in Figure 1. This implantation 18 creates a P type well 20 extending into the substrate 10 from the surface 12, as shown in Figure 2.

First and second active-area masks, 22 and 23, are then generated on the surface 12 of the substrate 10, as shown in Figure 2. The first active-area mask 22 is disposed within the boundaries of the P type well 20, and the second active-area mask 23 is disposed on an N type portion of the surface 12. As illustrated, both active-area masks 22 and 23 have a width W and are separated by a distance D. Typical dimensions for W and for D are approximately 3 microns. Each active-area mask 22 and 23 typically comprises a buffer layer 24, of silicon dioxide having a thickness of a few hundred Angstroms, disposed on the surface 12, and a silicon nitride layer 26, having a thickness of a few thousand Angstroms, disposed on the buffer layer 24. The buffer layer 24 is used primarily to prevent defects from being introduced into the substrate 10 by the silicon nitride layer 26.

As shown in Figure 3, a photoresist mask 28 is next defined on the surface 12 and second active-area mask 23, so as to expose the first active-area mask 22 and the P type well 20. A field threshold-control implantation of P type conductivity modifiers is then provided, as indicated at 30. As illustrated in Figure 4, the threshold-control implantation 30 creates an enhanced P type region 32 in those areas of the P type well 20 which are not covered by the first active-area mask 22.

A second photoresist mask 34 is then defined on the surface 12 so as to cover the P type well 20, and an N type field threshold-control implantation 36 is provided into areas of the N type substrate which are not covered by the second active-area mask 23. As illustrated in Figure 5, this implantation 36 creates an enhanced N type region 38 in those portions of the N type substrate not covered by the second active-area mask 23. The second photoresist mask 34 is then removed.

As illustrated in Figure 6, the substrate 10 is next subjected to a thermal oxidation step so as to create a field oxide 40 on portions of the substrate 10 which are not covered by the active-area masks 22 and 23. This process is sometimes referred to as LOCOS (LOCal Oxidation of Silicon) in the semiconductor processing art.

As illustrated, the nature of thermal oxidation is that portions of the surface 12 of the silicon substrate 10 are consumed when the field oxide 40 is grown. Approximately one-half of the thickness of the field oxide 40 occurs below the plane of the original surface 12, and one-half of the thickness occurs above the plane of the original surface 12.

In the distance D between the active-area masks 22 and 23, the thickness of the field oxide 40 is substantially uniform as indicated at T. Atypical value for T is approximately 0.5 to 1.5 micrometers.

However, in the LOCOS process, a portion of the field oxide 40 also grows beneath the edges of active-area masks 22 and 23. These undergrowing portions of the field oxide 40 are commonly referred to as "bird beaks", and are identified at 42 in Figure 6. The distance that each bird beak undercuts its overlying active-area mask is labeled as B, and typically, this distance is approximately equal to the thickness of the field oxide T.

Another phenomenon which occurs during the LOCOS process is the additional diffusion of the enhanced P type and N type regions 32 and 38. The distance of this additional enhancement-region diffusion at the silicon surface 12 beneath each of the active-area masks 22 and 23 is labeled as F, and is approximately equal to one half the field oxide thickness T.

As illustrated in Figure 7, the activa-area masks 22 and 23 are next removed so as to expose P type silicon surface 122 and N type silicon surface 123. The nonplanar surface of the substrate comprising the silicon surfaces 122 and 123 and the field oxide 40 surrounding the silicon surfaces 122 and 123 is identified as 44 An NMOS device and a PMOS device are now formed at the silicon surfaces 122 and 123 by conventional processing. The maximum channel width of a PMOS or NMOS device fabricated in this conventional structure is equal to W minus 2B minus 2F. Thus, in addition to the reduction of width W due to the occurrence of bird beaks, the additional diffusion of the enhancement regions 32 and 38 further reduces the maximum possible channel width.

Following the fabrication of the NMOS and PMOS devices at the silicon surfaces 122 and 123, electrical contact must be made to the devices. However, the structure illustrated in Figure 7 restrists the location of this electrical contact to a substantially central location within each surface 122 and 123.

In accordance with the present invention, the conventional processing sequence can be significantly streamlined, and the device packing density, performance, and reliability can be significantly improved. As illustrated in Figure 8, a bulk monocrystalline silicon substrate 50 having a substantially planar major surface 52 is initially provided. An apertured field oxide 54 is provided on the major surface 52. Each aperture 56 has walls which are substantially perpendicular to the major surface 52 and which, hereinafter, will be referred to as being vertical. Such a structure can be readily fabricated by a number of conventional processing techniques. For example, a layer of silicon dioxide of appropriate thickness can be formed on the substrate surface 52 of the substrate 50, and a photoresist mask can then be generated conventionally on the surface of the silicon dioxide layer.The silicon dioxide can be thermally grown or it can be deposited by CVD, and it may have a thickness of approximately 2 to 4 micrometers. Portions of the silicon dioxide layer exposed through the photoresist mask can then be removed by an anisotropic etching technique, such as plasma or reactive ion etching.

In the present invention, the width of each aperture 56 and the distance between apertures 56 are constrained by photolithographic limitations similar to those encountered when fabricating the active-area masks 22 and 23 in the conventional process. The width of each aperture 56 is designated as W', and the distance between apertures 56 is designated as D'.

Following the formation of the apertured field oxide 54, a monocrystalline semiconductor region 58 is formed in each of the apertures 56, as shown in Figure 9. These monocrystalline regions 58, which are silicon in the preferred embodiment, are grown from the substrate surface 52 to a height substantially equal to that of the field oxide 54, so as to form a substantially coplanar silicon/field oxide surface 59. The monocrystalline silicon regions 58 can be formed by the selective epitaxial deposition process referred to as the Epitaxial Lateral Overgrowth (ELO) technique.

Basically, this selective epitaxial deposition process involves a repititous two-stage depositing/etching cycle. In the first stage, silicon is deposited from a gas mixture which includes a silicon-source gas, a carrier gas, and, optionally, a silicon-etching gas. In the second stage, a portion of the silicon deposited during the first stage is etched in a gas mixture of a silicon-etching gas and a carrier gas. This depositing/etching cycle is then repeated an appropriate number of times until the monocrystalline silicon regions 58 grow to a height substantially equal to the thickness of the field oxide 54.

The depositing/etching cycle can be performed in a conventional reactor at atmospheric or reduced pressure, and a variety of silicon-source gases, silicon-etching gases, and carrier gases can be used. Using dichlorosilane as the silicon-source gas, HCI as the etching gas (in both stages), and hydrogen as the carrier gas, exemplary depositing/etching parameters are summarized in the table below: FLOW RATE (liters/min) H2 HCI SiH2Cl2 TIME (min) DEPOSITING STAGE 24 0.15 0.20 2 ETCHING STAGE 24 0.30 1 FLOW VELOCITY: 24 cm/sec REACTOR TEMPERATURE: 1100 C (pyrometer reading) PRESSURE: 1 atm Furthermore, the monocrystalline silicon regions 58 can be doped simultaneously with their formation by admitting an appropriate dopant gas during the depositing stage.In the exemplary structure of Figure 9, each of the monocrystalline silicon regions 58 is of N type material, although alternatively, they could be of P type material. As a further alternative, N and P type monocrystalline silicon regions 58 can be sequentially grown by selectively masking one or more or the apertures 56 while growing monocrystalline regions 58 of one type conductivity, and then masking the grown monocrystalline regions 58 while growing monocrystalline regions 58 of the other type conductivity in the unfilled apertures 56.

In the preferred embodiment for fabricating a CMOS device, a photoresist mask 60 is defined over one or more N type monocrystalline silicon regions 58, as shown in Figure 10. The exposed monocrystalline silicon regions 58 are then doped with a P type conductivity modifier, for example, by ion implantation, as illustrated at 62. The doping level should be such that a P type well 64 is formed in each of the exposed monocrystalline silicon regions 58. The photoresist mask 60 is then removed, as shown in Figure 11, and the field-oxide-isolated N and P type monocrystalline regions 58 and 64 are subjected to further MOSFET device fabrication processing.To fabricate a CMOS device, this further processing typically includes the steps of: growing gate oxide; depositing, doping and defining polycrystalline silicon gates; doping source and drain regions; depositing an oxide layer; forming contact openings in the oxide layer; and depositing and defining interconnect metallization. Further reference may be made, for example, to COS/MOS Integrated Circuits Manual, RCA Corporation, 1979.

Thus, the method of the present invention provides a number of advantages over the conventional MOSFETfabrication technique. In the present invention, aperture size and the spacing between apertures determines MOSFET size and the spacing between MOSFETS. Since the present novel process does not produce bird beaks, the distance between neighboring devices can be reduced by at least 2B. Greater packing density is therefore possible on a given area of a silicon substrate.

As the illustrations show, the inventive process also requires fewer processing steps. Two photolithographic sequences are required, i.e., one to generate the apertures 56, and a second to generate the photoresist mask 60. Whereas, in the conventional process, four photolithographic sequences are required, i.e., one to generate the mask layer 14, a second to generate the active-area masks 22 and 23, a third to generate the photoresist mask 28, and a fourth to generate the second photoresist mask 34.

Also, only a single implantation step is required in the present invention compared to the three implantations required in the conventional sequence. The two threshold-control implantations 30 and 36 used in the conventional process are eliminated by the present invention. The absence of these threshold-control implantations and, hence, the enhanced N type and P type regions 32 and 38 also provides a structural improvement in the devices formed. The elimination of these enhanced regions 32 and 38 prevents what is known as the "channel-narrowing effect". More area of the P type and N type silicon surfaces is now available for channel width. The elimination of these enhanced regions 32 and 38 from beneath the field oxide between devices also permits a higher operating voltage for the devices.

Compared to the nonplanar silicon/field oxide surface 44 produced by the conventional processing sequence, the substantially planar silicon/field oxide surface 59 produced by the method of the present invention provides a more desirable foundation for subsequent processing. It is expected, for example, that subsequent photolithographic processing yields will be improved because of this planar surface.

Because the formation of unduly large bird beaks is not a consideration in the present novel process, the field oxide 54 between devices can be made thicker than it is in conventional devices. As previously indicated, a thicker field oxide 54 serves to enhance several device operating parameters. It will produce lower capacitive coupling between conductor lines, which overlie the field oxide, and the substrate 50. Since this capacitance is reduced, the operating speed of the device can be increased, and the voltages of the conductor lines can be increased.

The planar silicon/field oxide surface 59 also facilitates subsequent interconnection to each device by a metal contact. A contact to the structure of the present invention can be greater in size than the width W of the monocrystalline silicon region which it contacts, such that it overlies the adjacent field oxide 54. By comparison, in the conventionally processed structure, a contact to a device at either of the silicon surfaces 122 or 123 must be centrally located on the surfaces 122 and 123.

Furthermore, by modifying the material of the substrate 50 used in the present invention, the incidence of soft error problems in NMOS, PMOS or CMOS devices, and the incidence of latch-up in CMOS devices can be reduced. This is accomplished by providing a substrate which is relatively heavily doped with N type conductivity modifiers and/or relatively heavily doped with oxygen precipitates. This doping reduces the frequency of latch-up and soft errors because it produces a lower carrier lifetime in the substrate and, thus, impedes minority carrier flow between devices fabricated in the monocrystalline silicon regions 58. Because the present invention substantially reduces the incidence of latch-up, the NMOS and PMOS devices in a CMOS device can be located within a photolithographically-limited distance of each other, thereby substantially increasing device packing density.

Claims

1. A method for fabricating a plurality of relatively closely spaced MOSFETs on a substrate, the improvement comprising: forming on a surface of said substrate a field oxide having a plurality of vertical-walled apertures therein, and forming a MOSFETwithin each aperture.

2. A method in accordance with Claim 1, comprising: forming a layer of silicon dioxide on the surface of said substrate; and anisotropically etching portions of the silicon dioxide layer so as to form the field oxide.

3. A method in accordance with Claim 1, comprising: selectively epitaxially growing a monocrystalline semiconductor region within each aperture.

4. A method in accordance with Claim 3, wherein: said monocrystalline regions are silicon and are substantially coplanar with the field oxide.

5. A method in accordance with Claim 1, further comprising: providing a substrate which is relatively heavily doped so as to reduce charge carrier lifetime therein.

6. A method in accordance with Claim 1, further comprising: providing a substrate which includes oxygen precipitates.

7. A method in accordance with Claim 5, further comprising: providing a substrate which includes oxygen precipitates.

8. A method for fabricating a plurality of relatively closely spaced MOSFET's on a substrate as described hereinbefore with reference to Figures 8 through 11 of the accompanying drawing.