DE3422495A1 - METHOD FOR PRODUCING SEVERAL MOSFETS ON A SUBSTRATE - Google Patents

Description

The invention relates to a method for producing several relatively closely adjacent MOSFETs (metal-oxide-semiconductor field effect transistors) on a substrate, in which a field oxide with a plurality of openings having vertical walls is formed on a surface of the substrate will. In particular, the invention relates to a method for producing a plurality of N-channel MOSFETs (NMOS), P-channel MOSFETs (PMOS) or more complementary symmetric MOSFETs (CMOS) in a relatively close arrangement on a substrate surface. Finally, the invention relates to a semiconductor device with a plurality of MOSFETs surrounded by field oxide on the surface of a substrate.

When manufacturing multiple MOSFET components on the surface of a silicon substrate, the individual components typically by intervening field oxide consisting of thermally grown silicon dioxide against each other set at a distance. On the field oxide between the individual components there are usually electrically conductive ones Strips of metal or polycrystalline silicon. To reduce the capacitance between the silicon existing substrate and the conductor strips lying on the field oxide, it is desirable to relate the field oxide to train thick. That would mean that the conductor strips could be subjected to a higher voltage and the device enabled a higher switching speed.

However, there are also reasons in favor of a relatively thin field oxide between the neighboring components. In the conventional manufacture of MOSFET components on substrates made of silicon, this occurs "bird beak" problem well known in the semiconductor industry or wedge-shaped growth of the field oxide towards

the areas of the substrate reserved for the MOSFET components. This beak or wedge growth is characterized by a reduced overall thickness of the field oxide in the vicinity of the individual components. The wedge growth is undesirable because, among other things, it reduces the maximum packing density of the components and a non-flat silicon / field oxide outer surface result Has. The thicker the oxide, the stronger the wedge growth, with the consequence of an increasingly lower packing density the components and an increasingly uneven outer surface of the silicon / field oxide layer.

The invention is based on the object of a method for producing a plurality of elements isolated from one another by field oxide To create MOSFETs on a substrate where wedge growth does not occur. The task is in particular also in it, a semiconductor component with several MOSFETs separated from one another by field oxide to create the surface of a substrate that has the area available for the active components does not have constraining wedge growth and a coplanar surface of active and field oxide regions owns.

For the method of the type mentioned at the outset, in the case of a substrate with field oxide located thereon with several vertical walls having openings is assumed, the solution according to the invention is that in a MOSFET is formed in each opening.

While in the earlier process the active components in the semiconducting one that was already originally present Material of the substrate were to be formed and field oxide between the areas intended for the active components

starting from the substrate surface inwards and outwards was to grow up is the first step according to the invention made the field oxide with openings for introducing the MOSFETs. For this purpose, starting from one on one Surface with silicon dioxide coated substrate for forming the field oxide parts of the silicon dioxide layer anisotropically etched in such a way that the desired openings are created with walls vertical to the substrate surface. According to a further invention, a monocrystalline semiconductor zone can now be grown selectively epitaxially within each opening will. The growth of the monocrystalline, in particular composed of silicon, is preferred Zones continued until the surface of these zones is coplanar with the surface of the pre-existing one Field oxide is. Within the monocrystalline semiconductor zones grown in this way on the original substrate Finally, the active components can be prepared in the usual way.

In order to rule out the formation of current paths and the like in the substrate as far as possible, the substrate can according to FIG further invention in the sense of shortening the carrier life of the substrate material is relatively heavily doped will. It can also be beneficial to have an oxygen precipitate (e.g. built-in in non-bonded form Use oxygen) containing substrate. ■

For the semiconductor component mentioned at the beginning with several MOSFETs surrounded by field oxide on the surface of a substrate, the solution according to the invention consists in that the MOSFETs are located in openings of the field oxide which have walls perpendicular to the substrate surface. The outer surfaces of the MOS-FET and field oxide regions should preferably be essentially coplanar, so that the device surface containing the active components is substantially flat and there are no problems with the application of conductor strips there.

Using the schematic representation in the drawing the invention is explained in more detail. Show it:

1 to 7 show the sequence of a known method for producing a CMOS component on the basis of a sequence of cross-sections of the component; and

8 to 11 show the sequence of the method according to the invention on the basis of a sequence of cross-sections of a semiconductor component.

Referring to Figures 1-7, part of the manufacturing sequence is shown for a conventional CMOS component. According to FIG. 1, a single-crystal, N-conductive substrate 10 made of silicon with a main surface 12 assumed. A masking layer 14 with an opening 16 is applied to the main surface 12. In the Opening 16, a predetermined part of the main surface 12 is exposed. A P-type dopant, e.g. Boron, as indicated in Fig. 1 by the arrows 18, in the substrate 10 is implanted. As a result of the implantation 18, according to FIG. 2, one extends from the main surface 12 P-well 20 extending into the substrate 10 is formed.

Then, as shown in FIG. 2, a first and a second active area mask 22 and 23 are placed on the main surface 12 of the substrate 10 is generated. The first active area mask 22 is formed within the confines of the P-well 20. The second active area mask 23 is generated on an N area of the main surface 12. According to the drawing The active area masks 22 and 23 both have a diameter W, while their mutual distance is D. Typical sizes for W and D are around 3 microns. Each active area mask 22, 23 usually contains a buffer layer applied to the main surface 12

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24 made of silicon dioxide with a thickness of several tens of nanometers and a silicon nitride layer on top 26 with a thickness of a few hundred nanometers. The buffer layer 24 serves primarily to To prevent defects that could be introduced into the substrate 10 by the silicon nitride layer 26.

According to FIG. 3, a first photomask 28 is delimited on the main surface 12 and the second active area mask 23 in such a way that that the first active area mask 22 and the surface of the P-well 20 are exposed. Afterward an implantation 30 for field threshold value control is provided. The field threshold control is used to control the Threshold voltage, i.e. the voltage at which the component switches on or becomes conductive by enclosing parasitic MOS components raise the conductivity in the silicon substrate 10 below the inactive Field oxide areas is increased. According to FIG. 4, the threshold value control implantation 30 results in an enriched P-zone 32 is generated in the areas of the P-well 20 that were not covered by the first active-area mask 22.

Next, a second photomask 34 is defined on the main surface 12 so that it covers the surface of the P-well 20 covered. The component prepared in this way is used for the field threshold value control of an N-implantation 36 in the N-conductive areas of the substrate 10 that are not covered by the second active area mask 23 are exposed. According to 5, an enriched N-zone 38 in the parts of the N-conductive substrate 10 is created by the N-implantation 36 generated which were not covered by the second active area mask 23. The second photo mask 34 is then removed.

Thereupon the substrate 10 according to FIG. 6 is first thermally oxidized in order to produce a field oxide 40 on the parts of the substrate surface 12 not covered by the active area masks 22 and 23. The method suitable for this is sometimes referred to in semiconductor technology as the LOCOS method ( Loc al (Oxidation of S_ilicon). As can also be seen from the illustration, it is the nature of the thermal oxidation that parts of the silicon substrate 10 on the main surface 12 when the Field oxide 40. About half the thickness of the field oxide 40 grows from the plane of the original main surface 12 downwards (into the semiconductor body), while the other half grows upwards beyond the original main surface 12.

In the space (distance D) between the active area masks 22, 23, the thickness T of the field oxide 40 is essentially the same everywhere. A typical value for the field oxide thickness T is about 0.5 to 1.5 micrometers. In which However, with the LOCOS process, part of the field oxide 40 also grows under the edges of the active area masks 22 and 23. These parts of the field oxide 40 growing under the edges of the masks are due to the above called wedge growth formed beak-shaped or wedge-shaped undercuts 42 (see Fig. 6). The distance up to the each undercut 42 under the active area mask is sufficient, has been given the designation B in FIG. In typical cases, the depth B is approximately that same amount as the thickness T of the field oxide 40. As the field oxide thickness T increases, the depth B also increases the undercut 42 too.

Another effect occurring in the LOCOS process is the additional diffusion of the enriched P and N zones 32 and 38, respectively. The mutual spacing of the corresponding diffusion zones on the main surface 12 below the active area masks 22 and 23 are denoted by F in FIG. The magnitude of F is roughly the same half of the field oxide thickness T. As the thickness T of the field oxide increases, so does the width F of the additional diffusion zone originating from the enriched P and N zones 32 and 38.

Next, as shown in FIG. 7, the active area masks 22 and 23 are removed in such a way that P-conductive silicon surfaces 122 and N-conductive silicon surfaces 123 exposed. The (overall) uneven surface of the substrate, consisting of the silicon surfaces 122 and 123 and the surface of the field oxide 40 surrounding the silicon surfaces 122, 123 is denoted by 44.

In the manufacturing process, an NMOS component and a PMOS component are now inserted into the silicon surfaces in the usual way 122 or 123 introduced. The maximum channel width of a PMOS or NMOS component manufactured in this way is equal to W minus 2B minus 2F. The largest possible channel width is therefore based on the conventional method of the diameter W of the active area masks 22, 23 not only about the wedge growth of the undercut 42 but also reduced by the additional diffusion of the enrichment zones 32 and 38.

After manufacturing the NMOS and PMOS components in The associated electrical contacts must be formed on the silicon surfaces 122 and 123. In the in Fig. 7, electrical contacts can

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but can only be mounted substantially centrally within each of surfaces 122 and 123.

According to the invention, the conventional production process significantly streamlined and the packing density, performance and reliability of the semiconductor component produced can be improved considerably.

In this case, according to FIG. 8, a solid, single-crystal silicon substrate 50 with an essentially flat Main area 52 assumed. A field oxide 54 having openings 56 is provided on the main surface 52. Each opening 56 has substantially perpendicular to the main surface 52 standing walls, hereinafter referred to as be referred to as "vertical". Such a structure can be produced by various known production methods will. For example, a silicon dioxide layer of appropriate thickness can be provided on major surface 52 of the substrate 50 are formed and covered with a conventionally produced and limited photoresist mask. The silicon dioxide can be grown thermally or generated by chemical vapor deposition (CVD); it can be a Approximately 2 to 4 micrometers thick. The parts of the exposed within the limited photoresist mask Silicon dioxide layers can be etched using an anisotropic etching technique, e.g. by plasma etching or reactive ion etching, be removed.

In the method according to the invention, the diameter of each opening 56 and the spacing between different openings 56 in a similar manner by photolithographic Boundary inevitably formed, as in the production of the active area masks 22 and 23 in FIG

conventional technology. The width or the diameter of each opening 56 is denoted ^{by W and the distance between two openings 56 is denoted by D 1.}

After the production of the field oxide 54 having openings 56, according to FIG. 9, a monocrystalline oxide is formed in each opening 56 Semiconductor zone 58 formed. The monocrystalline semiconductor zones 58, which are preferably made of silicon exist, are grown on the substrate surface 52 up to equality with the thickness of the field oxide 54, so that a substantially coplanar silicon / field oxide surface 59 results. The single crystal silicon zones 58 can be deposited using a selective epitaxial process, e.g. using the ELO technique (ELO = Epitaxial Lateral Overgrowth), in which a lateral growth can be achieved.

An essential feature of this selective epitaxial precipitation technique is a repeated two-stage process Wax / etch cycle. In the first stage, silicon is made from a gas mixture with a silicon donating gas, a carrier gas and - optionally a silicon etching gas deposited. In each The second stage of the cycle becomes some of the silicon deposited during the first stage in a gas mixture etched from a silicon etching gas and a carrier gas. This deposition / etching cycle is repeated as long as until the monocrystalline silicon zones 58 are grown to substantially the same thickness as the field oxide 54 are.

The grow / etch cycle can be done in a conventional reactor be carried out at normal pressure or reduced pressure. A large number of silicon donors can be used

Gases, silicon etching gases and carrier gases are used. In the case of dichlorosilane as the silicon source, HCl as the etching gas (in both stages) and hydrogen as the carrier gas are exemplary growth / etching parameters in compiled in the following table:

Flow rate (liter / minute)

H _n HCl

Time (min)

Growth phase etching phase

Flow rate: reactor temperature: Pressure:

2 1

24 cm / sec

HOO ⁰ C (pyrometer reading) 0.1 MPa (1 atm)

Furthermore, the monocrystalline silicon zones 58 can be doped at the same time as they are formed by the in the A suitable doping gas is added to the gas mixture used in the growth phase.

In the exemplary structure according to FIG. 9, each monocrystalline silicon zone 58 consists of N-conductive material; instead, the zones could of course be P-conductive be. Another alternative is to have N- and P-conducting, single-crystal silicon zones 58 one after the other to grow, in which one or more openings 56 during the growth of the monocrystalline zones 58 of the selectively masking one conduction type and then masking the monocrystalline zones 58 that have already been grown, while the monocrystalline zones 58 of the other conductivity type are formed in the openings 56 which have not been filled up to that point will.

In a preferred embodiment for fabricating a CMOS device, a photoresist mask 60 is overlaid one or more of the N-conductive, single-crystal silicon zones 58 as shown in FIG. 10. The monocrystalline silicon zones 58, which are then still exposed, are then doped with a P-type dopant, e.g., by ion implantation 62. The doping level should be set in this way be that in each exposed, monocrystalline silicon zone 58 a P-well 64 is formed. After removal the configuration according to FIG. 11 then arises of the photoresist mask 60.

The N- and P-conducting, monocrystalline zones 58 and 64 can be subjected to further steps in the manufacturing process for the production of MOSFET semiconductor components. For example, the following typical process steps can be used to manufacture a CMOS component: Growing a gate oxide; Depositing, doping and confining polycrystalline silicon gates; Doping of source and drain zones; Depositing an oxide layer; Forming contact openings in the oxide layer; and depositing and delimiting a metallization that represents the electrical connections. Otherwise, for example, the publication "COS / MOS Integrated Circuits Manual", RCA Corporation, 1979, Referenced.

The method of the invention provides numerous advantages compared to conventional technology in MOSFET fabrication. According to the invention, the MOSFET size and the spacing between adjacent MOSFETs is predetermined by the size and spacing of the openings in the field oxide.

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Since in the method according to the invention, the wedge growth described does not occur, the distance between adjacent components can be reduced by at least the amount 2B will. There is therefore a closer packing density of active components on a given area of a silicon substrate possible.

As is clear from the explanation, the invention requires Process also fewer process steps. Initially, only two photolithographic steps are required namely, once to form the openings 56 and then to form the photoresist mask 60. In contrast, required the known method four photolithographic steps, namely once to form the mask 14, a second time to form the active area masks 22 and 23, a third Time to form the first photoresist mask 28 and a fourth time to form the second photoresist mask 34.

In the method according to the invention, there is only one Implantation required, while three implantations are required for the known method. The two Implantations 30 and 36 for regulating the threshold value in the known method are omitted according to the invention. The elimination the implantation for threshold control also has the further advantage that the enriched N and P zones 32 and 38 do not arise. This means that the "channel narrowing effect" corresponding to the enriched zones 32 and 38 also omitted. According to the invention, there is therefore a larger area of the P- and N-conductive silicon surfaces available for the channel width. The elimination of the enriched zones 32 and 38 below the Field oxide between components also enables a higher operating voltage of the components.

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In contrast to the uneven silicon / field oxide surface 44 of a conventionally manufactured component, according to the invention, an essentially flat silicon / field oxide surface is created 59, which is a very desirable basis for further processing. For example it is to be expected that subsequent photolithographic processing deliver much better results because of the flat surface.

Since, according to the invention, inappropriately deep, wedge-shaped undercuts As a result of the wedge growth explained at the outset, the field oxide 54 can also be between the components are made thicker than previously possible. As mentioned, a thicker field oxide 54 has an improvement several operating parameters of the component result. First of all, the capacitive coupling is between on the conductor strips lying on the field oxide and the substrate 50 reduced by greater field oxide thickness. If this capacity is reduced, the operating speed of the component are enlarged; in addition, the voltages applied to the conductor strips can be increased.

The flat silicon / field oxide surface 59 makes it easier also the subsequent making of connections to each component through a metal contact. The respective With the structure according to the invention, contact can even exceed the diameter W of the single-crystal silicon zone which it is intended to contact, so that it is also on the adjacent field oxide 54 is located. In contrast, with conventionally manufactured structures, the contact had to be Component both on the silicon surface 122 and 123 (see Fig. 7) are arranged centrally.

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By adapting the material of the substrate 54, weak-defect problems can occur in the method according to the invention (soft error) in NMOS, PMOS or CMOS components and the occurrence of latching effects (latchup) can be reduced in CMOS components. In contrast to permanent ones caused by constructive imperfections Faults are expressed by "weak faults" in MOSFET components in a temporarily faulty behavior, the in principle originates from an excessive stream of minority carriers. The "Snap Effects" are the creation of a low-resistance current path between the voltage source and earth in a circuit during of a current impulse, whereby the current path remains after the impulse, ie "locks". The weak bug and Locking problems are solved according to the invention by using a Reduced substrate, which is relatively heavily doped with N-dopants and / or with oxygen precipitates. Such doping increases the frequency of occurrence of weak defects and latching effects decreased because the carrier life in the substrate is reduced and therefore the minority carrier flow between the Individual components formed in the monocrystalline silicon zones 58 are hindered. As when applying the invention the occurrence of the locking effect essentially is decreased, the NMOS and PMOS components in a CMOS device in a photolithographically bounded one Be arranged at a distance from one another, which has a significantly increased packing density compared to known components allows.

Claims (13)

Dr.-lng. Reimarf ^{king; v} : "PphHng. Klaus Bergen Wühelm-Tell-Str. 14 4DOO Düsseldorf 1 Telephone 39 7O2B Patent Attorneys 342243 5 15.Jum i984 35 532 B RCA Corporation, 30 Rockefeiler Plaza,
New York , NY 10020 (V.St.A.) "Method of making multiple MOSFETs on one Substrate " Patent claims: Method for producing several relatively closely adjacent MOSFETs on a substrate (50), in which a field oxide (54) with several openings (56) having vertical walls is formed on a surface (52) of the substrate (50), characterized in that a MOSFET is formed in each opening (56). 2. The method according to claim 1, characterized in that a silicon dioxide layer is formed on the surface (52) of the substrate (50) and that parts of the silicon dioxide layer are anisotropically etched to form the field oxide (54). 3. The method according to claim 1 or 2, characterized in that a monocrystalline semiconductor zone (58) is grown selectively epitaxially in each opening (56). 4. The method according to claim 3, characterized in that the monocrystalline zone (58) is made of silicon. 5. The method according to claim 3 or 4, characterized in that the monocrystalline zone (58) is grown up to a surface coplanar with the field oxide surface. 6. The method according to one or more of claims 1 to 5, characterized in that the substrate (50) is relatively heavily doped to shorten the carrier life. 7. The method according to one or more of claims 1 to 6, characterized in that a substrate (50) containing oxygen precipitates is used. 8. A semiconductor component with a plurality of field oxide (54) surrounded, in each case a semiconductor zone (58) formed MOSFETs on the surface (52) of a substrate (50), characterized in that each MOSFET is in one to the surface (52) of the substrate ( 50) opening (56) of the field oxide (54) having vertical walls. 9. Semiconductor component according to claim 8, characterized in that the outer surfaces of the semiconductor zones (58) containing the MOSFETs and of the field oxide (54) are essentially coplanar. 10. Semiconductor component according to claim 8 or 9, characterized in that the field oxide (54) consists of silicon dioxide. 11. Semiconductor component according to one or more of claims 8 to 10, characterized in that the semiconductor zones (58) containing the MOSFETs consist of optionally doped, in particular monocrystalline epitaxially grown silicon. 12. Semiconductor component according to one or more of claims 8 to 11, characterized in that the substrate is relatively heavily doped to shorten the service life. 13. Semiconductor component according to one or more of claims 8 to 12, characterized in that the substrate (50) contains oxygen precipitates.