JPS5726463A - Manufacture of complementary mos integrated circuit - Google Patents

Manufacture of complementary mos integrated circuit

Info

Publication number
JPS5726463A
JPS5726463A JP10199780A JP10199780A JPS5726463A JP S5726463 A JPS5726463 A JP S5726463A JP 10199780 A JP10199780 A JP 10199780A JP 10199780 A JP10199780 A JP 10199780A JP S5726463 A JPS5726463 A JP S5726463A
Authority
JP
Japan
Prior art keywords
type
type impurity
manufacture
integrated circuit
type layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10199780A
Other languages
Japanese (ja)
Inventor
Yasuhiro Funakoshi
Keiichi Murayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP10199780A priority Critical patent/JPS5726463A/en
Publication of JPS5726463A publication Critical patent/JPS5726463A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To simplify the steps of manufacturing a complementary MOSIC by selectively doping N type impurity to exceed both the density and the diffusing depth in a P type layer as an N type layer. CONSTITUTION:A P type well 2 is formed in an N type Si substrate 1, and a P type layer 8 is diffused as source and drain for P-channel and N-channel FET. Then, an SiO2 23 is selectively covered, conditions are so determined as to exceed the density and the diffusing depth of the P type impurity to diffuse the N type impurity, and an N type layer 10 is formed. Thus, the N-channel MOSFET source and drain layers are formed of P type and N type impurity double diffusion. In this manner, the formation and the selective removal of the SiO2 mask can be performed only once, thereby simplifying the steps.
JP10199780A 1980-07-24 1980-07-24 Manufacture of complementary mos integrated circuit Pending JPS5726463A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10199780A JPS5726463A (en) 1980-07-24 1980-07-24 Manufacture of complementary mos integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10199780A JPS5726463A (en) 1980-07-24 1980-07-24 Manufacture of complementary mos integrated circuit

Publications (1)

Publication Number Publication Date
JPS5726463A true JPS5726463A (en) 1982-02-12

Family

ID=14315455

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10199780A Pending JPS5726463A (en) 1980-07-24 1980-07-24 Manufacture of complementary mos integrated circuit

Country Status (1)

Country Link
JP (1) JPS5726463A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61125165A (en) * 1984-11-22 1986-06-12 Hitachi Ltd Manufacture of semiconductor device
JPS6211259A (en) * 1985-07-09 1987-01-20 Sony Corp Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61125165A (en) * 1984-11-22 1986-06-12 Hitachi Ltd Manufacture of semiconductor device
JPS6211259A (en) * 1985-07-09 1987-01-20 Sony Corp Manufacture of semiconductor device

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