JP2006351745A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP2006351745A
JP2006351745A JP2005174556A JP2005174556A JP2006351745A JP 2006351745 A JP2006351745 A JP 2006351745A JP 2005174556 A JP2005174556 A JP 2005174556A JP 2005174556 A JP2005174556 A JP 2005174556A JP 2006351745 A JP2006351745 A JP 2006351745A
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trench
forming
insulating film
mask
semiconductor device
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JP4720307B2 (en
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Masanobu Iwatani
将伸 岩谷
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Fuji Electric Co Ltd
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Fuji Electric Holdings Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66704—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of semiconductor device which does not easily allow lowering of voltage resistance by solving the problems that electric field is easily concentrated to an oxide film at the bottom of a trench, and that shape at the surface of the trench aperture has changed to a large extent. <P>SOLUTION: The manufacturing method of semiconductor device comprises the steps of forming a first trench with a first nitride film formed on the surface of a semiconductor substrate used as a mask, forming a second trench to the bottom of the first trench with a second nitride film and the first nitride film formed at the side wall of the first trench as the masks, forming a thermal oxide film within the second trench with the first nitride film and the second nitride film used as the masks, and forming a gate electrode to the side wall of the first trench via a gate insulating film after removing the first and second nitride films. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、シリコン基板上にトレンチを形成し、そのトレンチ内部にＭＯＳゲート構造とドレイン領域を形成した横型パワーＭＯＳＦＥＴなどの半導体装置に関する。   The present invention relates to a semiconductor device such as a lateral power MOSFET in which a trench is formed on a silicon substrate and a MOS gate structure and a drain region are formed inside the trench.

従来のトレンチ横型パワーＭＯＳＦＥＴ（略号ＴＬＰＭ）の模式的断面図を図９に示す。以下、トレンチ１０３の底部がｎドレイン領域１０４となるｎチャネル型のＴＬＰＭについて述べるが、ｐチャネル型ＴＬＰＭの場合は、導電型をそれぞれ逆にすれば、同様に作ることができる。
図１０〜図１３は、図９のＴＬＰＭの製造方法について、その要部を製造工程順に示したＴＬＰＭの要部断面図である。
図１０に示すように、半導体基板１００にＴＬＰＭのチャネルが形成される領域となるｐオフセット領域１０１を形成する。
次に、図１１に示すように、酸化膜（熱酸化膜または堆積酸化膜）１０２をマスクにトレンチ１０３を形成し、トレンチ１０３形成後、マスク酸化膜１０２をそのままマスクとしてトレンチ１０３底面だけに選択的にｎドレイン領域１０４を形成する。マスク酸化膜１０２を除去した後に、図１２に示すように、ゲート酸化膜１０５を例えば１７ｎｍの厚さで形成し、次に例えば厚さ３００ｎｍのドープトポリシリコンゲート電極１０６をＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）およびそれに続くエッチバック技術によりトレンチ１０３側壁にのみ残し、他の部分を除去して形成する。 A schematic cross-sectional view of a conventional trench lateral power MOSFET (abbreviated as TLPM) is shown in FIG. Hereinafter, an n-channel type TLPM in which the bottom of the trench 103 becomes the n-drain region 104 will be described. However, in the case of the p-channel type TLPM, if the conductivity types are reversed, they can be similarly produced.
10 to 13 are cross-sectional views of the main part of the TLPM showing the main parts in the order of the manufacturing steps in the method for manufacturing the TLPM of FIG.
As shown in FIG. 10, a p-offset region 101 that is a region where a TLPM channel is formed is formed in a semiconductor substrate 100.
Next, as shown in FIG. 11, a trench 103 is formed using an oxide film (thermal oxide film or deposited oxide film) 102 as a mask, and after forming the trench 103, only the bottom surface of the trench 103 is selected using the mask oxide film 102 as a mask. Thus, the n drain region 104 is formed. After removing the mask oxide film 102, a gate oxide film 105 is formed with a thickness of 17 nm, for example, as shown in FIG. 12, and then a doped polysilicon gate electrode 106 with a thickness of, eg, 300 nm is formed by CVD (Chemical Vapor Deposition). ) And the subsequent etch-back technique, leaving only the sidewalls of the trench 103 and removing other portions.

図１３に示すように、ＴＬＰＭ部のソース領域１０７を形成した後、層間絶縁膜１０８となるトレンチ埋め込み酸化膜をＣＶＤにより形成し、化学機械研磨（ＣＭＰ）を用いて表面を平坦化する。そして、前記図９に示すように、フォトリソグラフィ工程により層間絶縁膜１０８の必要な部分にコンタクト孔１０９を形成し、このコンタクト孔１０９にバリアメタル１１１と埋め込み金属プラグ１１０を形成し、この金属プラグ１１０上にアルミニウムなどの金属電極配線１１２を形成してＴＬＰＭ２００を完成させる。
ところが、前述のように従来のＴＬＰＭ２００を作製すると、トレンチ１０３内面のゲート酸化膜１０５が薄いため、トレンチ１０３底部のｎドレイン領域１０４を高電位にした場合、トレンチ１０３底部の薄い酸化膜の部分に電界集中が起こり、素子耐圧が低下し易いという問題がある。 As shown in FIG. 13, after forming the source region 107 of the TLPM portion, a trench buried oxide film to be the interlayer insulating film 108 is formed by CVD, and the surface is flattened by chemical mechanical polishing (CMP). Then, as shown in FIG. 9, a contact hole 109 is formed in a necessary portion of the interlayer insulating film 108 by a photolithography process, a barrier metal 111 and a buried metal plug 110 are formed in the contact hole 109, and this metal plug A metal electrode wiring 112 such as aluminum is formed on 110 to complete the TLPM 200.
However, when the conventional TLPM 200 is manufactured as described above, the gate oxide film 105 on the inner surface of the trench 103 is thin. Therefore, when the n drain region 104 at the bottom of the trench 103 is set to a high potential, There is a problem that electric field concentration occurs and the device breakdown voltage tends to decrease.

一方、次に説明するように、前記ＴＬＰＭ２００を改良してトレンチ１０３底面および底面のコーナーに厚い酸化膜を形成し、前述の電界集中を緩和して耐圧低下を防ぐ方法が知られている（特許文献１）。以下、特許文献１に記載の図１７と実質的に同じ図を本明細書に図番を変えて添付した図１４を参照しながら、改良された製造方法を説明する。
図１４（ａ）〜（ｆ）は、前記図９に示すＴＬＰＭをさらに改良した製造方法の主要工程（トレンチ８２１のエッチング用マスク酸化膜８７０の形成から選択酸化膜８４１の形成まで）を工程順に並べた半導体基板の断面図である。
半導体基板８００表面にマスク酸化膜８７０を形成し、パターニングする（図１４（ａ））。マスク酸化膜８７０は、熱酸化膜でもＣＶＤ酸化膜でもどちらでも良い。
塩素ガス、窒素、酸素の混合ガスを用いた反応性イオンエッチング（ＲＩＥ）等の異方性エッチングによりトレンチ８２１を形成する（同図（ｂ））。 On the other hand, as will be described below, a method is known in which the TLPM 200 is improved to form a thick oxide film on the bottom surface of the trench 103 and the corners of the bottom surface to alleviate the electric field concentration and prevent the breakdown voltage from decreasing (Patent) Reference 1). Hereinafter, an improved manufacturing method will be described with reference to FIG. 14 in which substantially the same figure as FIG. 17 described in Patent Document 1 is attached with the figure number changed.
14A to 14F show the main steps (from the formation of the etching mask oxide film 870 of the trench 821 to the formation of the selective oxide film 841) in the order of steps in the manufacturing method further improving the TLPM shown in FIG. It is sectional drawing of the arranged semiconductor substrate.
A mask oxide film 870 is formed on the surface of the semiconductor substrate 800 and patterned (FIG. 14A). Mask oxide film 870 may be either a thermal oxide film or a CVD oxide film.
A trench 821 is formed by anisotropic etching such as reactive ion etching (RIE) using a mixed gas of chlorine gas, nitrogen, and oxygen (FIG. 5B).

トレンチ８２１の内面に、応力緩和のための薄いパッド酸化膜８７３を形成した後、例えばプラズマＣＶＤにより窒化シリコン膜（以下窒化膜と記す）８７２を堆積する（同図（ｃ））。
ＲＩＥ等の異方性エッチングにより基板表面およびトレンチ８２１底面の窒化膜８７２およびパッド酸化膜８７３をエッチング除去する（同図（ｄ））。
再びＲＩＥによりトレンチ８２１を更に掘り下げて深いトレンチ８２２とする。また基板表面に残ったマスク酸化膜８７０を除去する（同図（ｅ））。
熱酸化により基板表面およびトレンチ８２２の底部に厚い酸化膜８４１を形成する（同図（ｆ））。トレンチ８２１の側壁部には、窒化膜８７２があるため厚い酸化膜８４１が成長せず、薄いままとなる。
特開２００２−１８４９８０号公報 After forming a thin pad oxide film 873 for stress relaxation on the inner surface of the trench 821, a silicon nitride film (hereinafter referred to as a nitride film) 872 is deposited by, for example, plasma CVD (FIG. 3C).
The nitride film 872 and the pad oxide film 873 on the substrate surface and the bottom surface of the trench 821 are removed by etching by anisotropic etching such as RIE (FIG. 4D).
The trench 821 is further dug down again by RIE to form a deep trench 822. Further, the mask oxide film 870 remaining on the substrate surface is removed ((e) in the figure).
A thick oxide film 841 is formed on the surface of the substrate and the bottom of the trench 822 by thermal oxidation (FIG. 5F). Since the nitride film 872 exists on the side wall of the trench 821, the thick oxide film 841 does not grow and remains thin.
JP 2002-184980 A

しかしながら、前記特許文献１に記載のＴＬＰＭは、従来のＴＬＰＭにおける薄い酸化膜の部分に電界集中が起こり、素子耐圧が低下し易いという問題点を解決するためになされたものであり、トレンチ８２１底面およびコーナーに厚い酸化膜８４１を形成することにより電界集中を緩和する機能を有するものの、その方法として、トレンチ８２１形成のためのエッチング後に、シリコン窒化膜８７２をエッチバック法によりトレンチ８２１の側壁のみに選択的に残し、その側壁のシリコン窒化膜８７２をマスクとして、２段目のトレンチ８２２を形成し、その後、選択酸化を行う方法である。この場合、シリコン基板の表面側シリコンも酸化されてしまい、トレンチ開口部形状が酸化により大きく変形するという問題が新たに発生する。さらに、シリコン基板上部の厚い選択酸化膜を除去する工程が別途必要になるという問題も新たに発生する。   However, the TLPM described in Patent Document 1 has been made to solve the problem that electric field concentration occurs in a thin oxide film portion in the conventional TLPM and the device breakdown voltage tends to decrease, and the bottom surface of the trench 821 In addition, although the thick oxide film 841 is formed at the corners to reduce the electric field concentration, the silicon nitride film 872 is etched only on the side wall of the trench 821 by the etch back method after the etching for forming the trench 821. In this method, the second-stage trench 822 is formed using the silicon nitride film 872 on the side wall as a mask, and then selectively oxidized. In this case, the surface side silicon of the silicon substrate is also oxidized, and a new problem arises that the shape of the trench opening is greatly deformed by oxidation. Furthermore, there is a new problem that a separate process for removing the thick selective oxide film on the silicon substrate is required.

本発明は、前記問題点に鑑みてなされたものであり、その目的とするところは、トレンチ底部の酸化膜に電界集中が起こり易いという問題およびトレンチ開口部の表面形状が大きく変形するという問題を解消して、耐圧が低下しにくい半導体装置の製造方法を提供することである。   The present invention has been made in view of the above problems, and the object of the present invention is to solve the problem that electric field concentration easily occurs in the oxide film at the bottom of the trench and the problem that the surface shape of the trench opening is greatly deformed. The object is to provide a method for manufacturing a semiconductor device which is free from a decrease in breakdown voltage.

特許請求の範囲の請求項１記載の本発明によれば、前記目的は、半導体基板の表面に形成した第一窒化膜をマスクとして第一トレンチを形成する工程と、前記第一トレンチの側壁に形成した第二窒化膜と前記第一窒化膜とをマスクとして前記第一トレンチの底部に第二トレンチを形成する工程と、前記第一窒化膜と前記第二窒化膜をマスクとして前記第二トレンチ内面に熱酸化膜を形成する工程と、前記第一窒化膜と第二窒化膜とを除去した後、第一トレンチ側壁にゲート絶縁膜を介してゲート電極を形成する工程とを含む半導体装置の製造方法とすることにより、達成される。
特許請求の範囲の請求項２記載の本発明によれば、前記目的は、半導体基板の表面に露出する一導電型領域の表面に窒化膜を含む絶縁膜を所定パターンに形成する第一マスク絶縁膜を形成し、第一マスク絶縁膜をマスクとしてトレンチを形成する第一トレンチ形成工程と、該第一トレンチ側壁に窒化膜を含む第二マスク絶縁膜を形成し、第二マスク絶縁膜および前記第一マスク絶縁膜をマスクとして前記第一トレンチ底部に連続する追加トレンチを形成する第二トレンチ形成工程と、前記第二トレンチの内面に接合端が前記第一トレンチ側壁に至る他導電型ドレイン領域を形成するドレイン形成工程と、熱酸化により前記第二トレンチ内面に選択的に酸化膜を形成する選択酸化膜形成工程と、前記第一絶縁膜および第二絶縁膜を除去し、第一トレンチの側壁にゲート絶縁膜と該ゲート絶縁膜を介してポリシリコンゲート電極を形成するＭＯＳゲート構造の形成工程と、前記一導電型領域表面に形成され、一端が第一トレンチ側壁に露出する他導電型ソース領域を形成するソース形成工程とを含む半導体装置の製造方法とすることにより、達成される。 According to the first aspect of the present invention, the object is to form a first trench using a first nitride film formed on the surface of a semiconductor substrate as a mask, and on the side wall of the first trench. Forming a second trench at the bottom of the first trench using the formed second nitride film and the first nitride film as a mask; and the second trench using the first nitride film and the second nitride film as a mask. A step of forming a thermal oxide film on an inner surface; and a step of forming a gate electrode on a side wall of the first trench through a gate insulating film after removing the first nitride film and the second nitride film. This is achieved by using a manufacturing method.
According to the present invention as set forth in claim 2, the object is to form a first mask insulation that forms an insulating film including a nitride film in a predetermined pattern on the surface of one conductivity type region exposed on the surface of the semiconductor substrate. Forming a film and forming a trench using the first mask insulating film as a mask; forming a second mask insulating film including a nitride film on the side wall of the first trench; A second trench forming step of forming an additional trench continuous with the bottom of the first trench using the first mask insulating film as a mask, and another conductivity type drain region having a junction end on the inner surface of the second trench reaching the side wall of the first trench Forming a drain, forming a selective oxide film selectively on the inner surface of the second trench by thermal oxidation, removing the first insulating film and the second insulating film, Forming a gate insulating film on the side wall of the wrench and forming a polysilicon gate electrode through the gate insulating film; and forming a MOS gate structure on the surface of the one conductivity type region, one end of which is exposed to the first trench side wall This is achieved by providing a method for manufacturing a semiconductor device including a source formation step for forming a conductive type source region.

特許請求の範囲の請求項３記載の本発明によれば、前記ポリシリコンゲート電極は、ポリシリコンを少なくとも前記第一トレンチを埋めないように前記半導体基板表面および前記第二トレンチの底部に堆積された前記ポリシリコンを除去することにより形成し、前記ソース形成工程の後に、前記半導体基板全面に層間絶縁膜を堆積する工程と、該層間絶縁膜の表面から前記ソース領域およびドレイン領域に達する開口部を形成する工程とを有する特許請求の範囲の請求項２記載の半導体装置の製造方法とすることが好ましい。
特許請求の範囲の請求項４記載の本発明によれば、半導体装置がトレンチＭＯＳゲート構造を有する横型ＭＯＳＦＥＴである特許請求の範囲の請求項１乃至３のいずれか一項に記載の半導体装置の製造方法とすることが好適である。
特許請求の範囲の請求項５記載の本発明によれば、半導体装置が双方向のＭＯＳＦＥＴである特許請求の範囲請求項1または２記載の半導体装置の製造方法とすることが望ましい。 According to the third aspect of the present invention, the polysilicon gate electrode is deposited on the surface of the semiconductor substrate and the bottom of the second trench so as not to fill at least the first trench. Forming an interlayer insulating film on the entire surface of the semiconductor substrate after the source forming step, and an opening reaching the source region and the drain region from the surface of the interlayer insulating film. Preferably, the method of manufacturing a semiconductor device according to claim 2 includes the step of forming the semiconductor device.
According to the present invention, the semiconductor device is a lateral MOSFET having a trench MOS gate structure. 4. The semiconductor device according to claim 1, wherein the semiconductor device is a lateral MOSFET having a trench MOS gate structure. A manufacturing method is preferred.
According to the present invention as set forth in claim 5, it is preferable that the semiconductor device is a bidirectional MOSFET manufacturing method according to claim 1 or 2, wherein the semiconductor device is a bidirectional MOSFET.

本発明によれば、トレンチ開口部形状を酸化により大きく変形させることなく、トレンチの底面にのみ厚い酸化膜を形成することができ、素子耐圧の低下を防ぐことができる半導体装置の製造方法を提供することができる。   According to the present invention, there is provided a method of manufacturing a semiconductor device in which a thick oxide film can be formed only on the bottom surface of a trench without greatly changing the shape of the trench opening by oxidation, and a reduction in device breakdown voltage can be prevented. can do.

以下、本発明の実施の形態を説明する。以下の説明では半導体基板に示される導電型であるｐ型、ｎ型は逆でも構わない。また、以下、実施例１ではＴＬＰＭ（トレンチ横型パワーＭＯＳＦＥＴ）を例に挙げて、実施例２では、トレンチ底面のドレイン領域へのコンタクト電極を持たず、等価的には２つのＭＯＳＦＥＴが直列に接続された、双方向ＴＬＰＭの場合について、それぞれ本発明にかかる半導体装置の製造方法を詳細に説明する。ただし、本発明は、本発明の要旨を超えない限り、以下の実施例の記載に限定されるものではない。   Embodiments of the present invention will be described below. In the following description, the p-type and n-type which are the conductivity types shown in the semiconductor substrate may be reversed. Further, in the following, in Example 1, TLPM (trench lateral power MOSFET) is taken as an example, and in Example 2, there is no contact electrode to the drain region at the bottom of the trench, and equivalently, two MOSFETs are connected in series. In the case of the bidirectional TLPM, the method for manufacturing a semiconductor device according to the present invention will be described in detail. However, the present invention is not limited to the description of the following examples unless it exceeds the gist of the present invention.

図１は、この発明にかかる半導体装置の要部を示す断面図であり、図２〜図８は、この発明の半導体装置の製造方法を工程順に示した半導体基板の要部断面図である。
図２に示すように、ｐ型シリコン基板１のＴＬＰＭ形成領域にＴＬＰＭのチャネルとなるｐオフセット領域２を拡散形成する。次に、図３に示すように、第一マスク絶縁膜となる酸化膜３を例えば３０ｎｍとシリコン窒化膜４を例えば３００ｎｍ成長させ、フォトリソグラフィ工程により、トレンチ形成用パターン形成を行った後、それらの第一マスク絶縁膜３、４をマスクに第一トレンチ５を例えば１μｍの深さで形成する。前記酸化膜３はシリコン基板１とシリコン窒化膜４との密着性向上と、後でシリコン窒化膜を除去する際、シリコン窒化膜とのエッチング選択比を高くするために形成される。その後、図４に示すように、第一トレンチ５の内面に酸化膜６を例えば３０ｎｍの厚さに形成した後、新たにシリコン窒化膜７を例えば１５０ｎｍ成長させ、エッチバックすることにより、基板表面とトレンチ５の底部のシリコン窒化膜７を除去し、トレンチ側壁８には第二マスク絶縁膜となるシリコン窒化膜７を、基板表面上にはシリコン窒化膜４を残す。その後、図５に示すように、基板表面およびトレンチ側壁シリコン窒化膜４、７からなる第一および第二マスク絶縁膜をマスクとして再度トレンチエッチングを行い、２段目の第二トレンチ９を例えば０．５μｍの追加深さで形成する。そして、図６−１に示すように、酸化膜３および窒化膜４、７からなる第一および第二マスク絶縁膜をマスクをそのままマスクとしてトレンチ９内面だけに選択的にｎドレイン領域１０を形成する。ｎドレイン領域１０は最終的には熱拡散により、接合端が第一トレンチ５の側壁に達するようになる。さらにこの状態で、図６−２の示すように、熱酸化を例えば３００ｎｍの厚さで行うと、第一トレンチ５の側壁８と基板表面はそれぞれシリコン窒化膜４、７で覆われているため、第二トレンチ９の内面のみに選択的に酸化膜１１が形成される。続いてシリコン窒化膜４、７を除去し、さらに酸化膜３を除去した後に、図７に示すように、新たにゲート酸化膜１２を例えば１７ｎｍの厚みで形成し、さらに例えば厚さ３００ｎｍのドープトポリシリコンをＣＶＤにより堆積させ、エッチバックによりシリコン基板１表面と第二トレンチ９の底部のポリシリコンを除去してポリシリコンゲート電極１３をトレンチ５の側壁に形成する。そして、図８に示すように、ＴＬＰＭ部のソース領域１４となる領域を基板表面に拡散形成した後、層間絶縁膜１５となるトレンチ埋め込み酸化膜をＣＶＤにより形成し、化学機械研磨（ＣＭＰ）を用いて表面を平坦化する。そして、フォトリソグラフィ工程により必要な部分にコンタクト孔１６−１、１６−２を形成し、バリアメタル１７−１、１７−２、埋め込みプラグ１８−１、１８−２、金属電極配線１９−１、１９−２を形成すると図１に示す本発明の半導体装置ができる。 FIG. 1 is a cross-sectional view showing a main part of a semiconductor device according to the present invention, and FIGS.
As shown in FIG. 2, a p offset region 2 serving as a TLPM channel is diffused and formed in the TLPM formation region of the p-type silicon substrate 1. Next, as shown in FIG. 3, an oxide film 3 to be a first mask insulating film is grown to 30 nm and a silicon nitride film 4 are grown to 300 nm, for example, and a trench forming pattern is formed by a photolithography process. The first trench 5 is formed to a depth of 1 μm, for example, using the first mask insulating films 3 and 4 as a mask. The oxide film 3 is formed to improve the adhesion between the silicon substrate 1 and the silicon nitride film 4 and to increase the etching selectivity with the silicon nitride film when the silicon nitride film is removed later. Thereafter, as shown in FIG. 4, after an oxide film 6 is formed on the inner surface of the first trench 5 to a thickness of, for example, 30 nm, a silicon nitride film 7 is newly grown, for example, 150 nm and etched back, thereby Then, the silicon nitride film 7 at the bottom of the trench 5 is removed, the silicon nitride film 7 serving as the second mask insulating film is left on the trench sidewall 8, and the silicon nitride film 4 is left on the substrate surface. Thereafter, as shown in FIG. 5, trench etching is performed again using the first and second mask insulating films made of the substrate surface and the trench sidewall silicon nitride films 4 and 7 as a mask, and the second trench 9 in the second stage is set to 0, for example. Formed with an additional depth of 5 μm. Then, as shown in FIG. 6A, the n drain region 10 is selectively formed only on the inner surface of the trench 9 using the first and second mask insulating films made of the oxide film 3 and the nitride films 4 and 7 as masks. To do. The n drain region 10 finally reaches the side wall of the first trench 5 by thermal diffusion. Further, in this state, as shown in FIG. 6B, when the thermal oxidation is performed with a thickness of, for example, 300 nm, the sidewall 8 and the substrate surface of the first trench 5 are covered with the silicon nitride films 4 and 7, respectively. The oxide film 11 is selectively formed only on the inner surface of the second trench 9. Subsequently, after the silicon nitride films 4 and 7 are removed and the oxide film 3 is further removed, a gate oxide film 12 is newly formed with a thickness of 17 nm, for example, as shown in FIG. The polysilicon is deposited by CVD, and the polysilicon on the surface of the silicon substrate 1 and the bottom of the second trench 9 is removed by etch back to form a polysilicon gate electrode 13 on the sidewall of the trench 5. Then, as shown in FIG. 8, after a region that becomes the source region 14 of the TLPM portion is diffused and formed on the substrate surface, a trench buried oxide film that becomes the interlayer insulating film 15 is formed by CVD, and chemical mechanical polishing (CMP) is performed. Use to flatten the surface. Then, contact holes 16-1 and 16-2 are formed in necessary portions by a photolithography process, barrier metals 17-1 and 17-2, embedded plugs 18-1 and 18-2, metal electrode wiring 19-1, When 19-2 is formed, the semiconductor device of the present invention shown in FIG. 1 is obtained.

以上の実施例では、図１に示すように、トレンチ９の下部に選択的にｎドレイン領域１０を形成する場合であったが、シリコン基板がｎ型の場合、または、シリコン基板１とｐオフセット領域２の間にｎ型の領域を形成する場合は、ｎドレイン領域１０を形成しなくてもよい。この場合、酸化膜１１がｎ型の半導体基板１またはｎ型の領域の中に形成されることが望ましい。
さらに、シリコン基板１をｎ型とし、トレンチ９の幅を狭くして、トレンチ９をポリシリコンゲート電極１３で充填される構成とし、シリコン基板１の裏面にドレイン電極を形成した縦型トレンチＭＯＳＦＥＴに適用できる。
要するに、第一トレンチの側壁にＭＩＳゲート構造が形成され、ゲート電極へのゲート電圧のオン、オフにより、チャネルを通じて電流のオン、オフが可能になるように構成であれば、上述以外にも、いろいろな実施形態をとることができる。 In the above embodiment, as shown in FIG. 1, the n drain region 10 is selectively formed below the trench 9. However, when the silicon substrate is n-type, or the p offset with respect to the silicon substrate 1. When an n-type region is formed between the regions 2, the n drain region 10 does not have to be formed. In this case, the oxide film 11 is preferably formed in the n-type semiconductor substrate 1 or the n-type region.
Further, the vertical trench MOSFET in which the silicon substrate 1 is n-type, the width of the trench 9 is narrowed, the trench 9 is filled with the polysilicon gate electrode 13, and the drain electrode is formed on the back surface of the silicon substrate 1. Applicable.
In short, as long as the MIS gate structure is formed on the sidewall of the first trench and the gate voltage to the gate electrode can be turned on and off, the current can be turned on and off through the channel. Various embodiments can be taken.

以上の説明では、ＴＬＰＭ（トレンチ横型パワーＭＯＳＦＥＴ）は、トレンチの底部にｎドレイン領域を形成したｎチャネル型のＴＬＰＭについて説明したが、図１５に示すようなトレンチ５３底面に形成したドレイン領域５４にドレインコンタクトを有さず、二つのＭＯＳＦＥＴが直列に接続された双方向のＴＬＰＭとすることもできる。図１６に、その双方向ＴＬＰＭの等価回路図を示す。以下、本発明にかかる双方向ＴＬＰＭについて説明する。
図１５は本発明にかかる、異なる実施例としての半導体装置の構成図であり、同図（ａ）は要部平面図、同図（ｂ）は（ａ）で一点鎖線枠内を示すＡ部の拡大図、同図（ｃ）は同図（ｂ）のＸ−Ｘ線で切断した要部断面図である。
図１５の（ｃ）に示すように、ｐ半導体基板５１にｎウェル領域５２を拡散形成し、このｎウェル領域５２表面層にｐオフセット領域５５を形成する。ｐオフセット領域５５表面からトレンチ５３を形成し、このトレンチ５３底面下にｎドレイン領域５４を形成する。 In the above description, the TLPM (trench lateral power MOSFET) has been described for the n-channel type TLPM in which the n drain region is formed at the bottom of the trench, but the drain region 54 formed on the bottom surface of the trench 53 as shown in FIG. A bidirectional TLPM in which two MOSFETs are connected in series without having a drain contact can also be used. FIG. 16 shows an equivalent circuit diagram of the bidirectional TLPM. The bidirectional TLPM according to the present invention will be described below.
15A and 15B are configuration diagrams of a semiconductor device according to another embodiment of the present invention, in which FIG. 15A is a plan view of a main part, and FIG. 15B is a portion A showing the inside of a one-dot chain line in FIG. FIG. 4C is an enlarged cross-sectional view taken along line XX in FIG.
As shown in FIG. 15C, an n well region 52 is formed by diffusion in a p semiconductor substrate 51, and a p offset region 55 is formed in the surface layer of the n well region 52. A trench 53 is formed from the surface of the p offset region 55, and an n drain region 54 is formed below the bottom surface of the trench 53.

トレンチ５３内壁にゲート絶縁膜５６を形成し、トレンチ側壁５３ｂにゲート絶縁膜５６を介してゲート電極５７を形成する。この際、前述の実施例１と同様の方法により、トレンチ５３の底部に選択酸化膜５６ａを形成する。トレンチ５３に囲まれたｐオフセット領域５５の表面に、第１ｎソース領域５９と第２ｎソース領域６０を、それぞれ一端がトレンチ５３の側壁に露出するように選択的に形成する。この第１ｎソース領域５９と第２ｎソース領域６０は、図１５の（ａ）および（ｂ）に示すように、トレンチ５３を挟んで交互に形成される。層間絶縁膜５８を基板表面上に堆積し、トレンチ５３内部を充填する際に表面に形成される凹凸を平坦化する。その後、図１５（ｃ）に示すように、この層間絶縁膜５８にコンタクトホール５８ａをそれぞれ開孔して、第１ｎソース領域５９上と第２ｎソース領域６０上に第１ソース電極６１と第２ソース電極６２をそれぞれ形成する。図１５（ｂ）の鎖線で示すように、第１ソース電極６１同士、第２ソース電極６２同士は第１ソース配線６３、第２ソース配線６４でそれぞれ接続する。またゲート電極５７は層間絶縁膜５８によりソース電極６１、６２と短絡しないように延長されて図示しないゲートパッドに接続される。   A gate insulating film 56 is formed on the inner wall of the trench 53, and a gate electrode 57 is formed on the trench side wall 53 b via the gate insulating film 56. At this time, the selective oxide film 56a is formed on the bottom of the trench 53 by the same method as in the first embodiment. A first n source region 59 and a second n source region 60 are selectively formed on the surface of the p offset region 55 surrounded by the trench 53 so that one end thereof is exposed on the side wall of the trench 53. As shown in FIGS. 15A and 15B, the first n source region 59 and the second n source region 60 are alternately formed with the trench 53 interposed therebetween. An interlayer insulating film 58 is deposited on the substrate surface, and the unevenness formed on the surface when filling the trench 53 is flattened. Thereafter, as shown in FIG. 15C, contact holes 58a are formed in the interlayer insulating film 58, and the first source electrode 61 and the second source electrode 61 are formed on the first n source region 59 and the second n source region 60, respectively. Source electrodes 62 are formed respectively. As shown by the chain line in FIG. 15B, the first source electrodes 61 and the second source electrodes 62 are connected to each other by a first source wiring 63 and a second source wiring 64, respectively. The gate electrode 57 is extended by the interlayer insulating film 58 so as not to be short-circuited with the source electrodes 61 and 62 and is connected to a gate pad (not shown).

前記したように、ｎドレイン領域５４がトレンチ底部に形成されていることと、さらに、ドレイン領域５４とゲート電極の間にはゲート絶縁膜よりかなり厚い選択酸化膜５６ａが介在しているので、電界が緩和され高耐圧を確保することができる。
また、前述のように、ゲート電極５７とｎドレイン領域５４をトレンチ５３底部に形成することで、耐圧がトレンチ５３に沿って維持されるようになり、そのため、第１ｎソース領域５９と第２ｎソース領域６０の表面での間隔を狭くでき、セルの微細化ができる。その結果、オン電圧を低下させることができる。
なお、前述のようにｐ半導体基板５１を用いることで、この基板５１をグランド電位にすることができて、図示しないＣＭＯＳ回路などをこの基板５１に形成することが容易になる。また、前記の各トレンチ底部に形成される各ｎドレイン領域５４は、それぞれ離れて形成されているが、それぞれのｎドレイン領域５４が接するように形成しても構わない。 As described above, the n drain region 54 is formed at the bottom of the trench, and the selective oxide film 56a that is considerably thicker than the gate insulating film is interposed between the drain region 54 and the gate electrode. Is relaxed and a high breakdown voltage can be secured.
Also, as described above, the breakdown voltage is maintained along the trench 53 by forming the gate electrode 57 and the n drain region 54 at the bottom of the trench 53. Therefore, the first n source region 59 and the second n source The interval on the surface of the region 60 can be narrowed, and the cells can be miniaturized. As a result, the on-voltage can be reduced.
In addition, by using the p semiconductor substrate 51 as described above, the substrate 51 can be set to the ground potential, and a CMOS circuit or the like (not shown) can be easily formed on the substrate 51. The n drain regions 54 formed at the bottoms of the trenches are formed apart from each other. However, the n drain regions 54 may be formed in contact with each other.

前記図１６の等価回路図を用いて、前記双方向ＴＬＰＭ５０の動作について説明する。第１ソース端子Ｓ１に対して第２ソース端子Ｓ２に高電圧を印加し、第２ソース端子Ｓ２より高い電圧をゲート端子Ｇに印加することで、図１５の第１、第２ｎソース領域５９、６０とｎドレイン領域５４に挟まれたｐオフセット領域５５側面にチャネルが形成されて第２ソース端子Ｓ２から第１ソース端子Ｓ１に電流が流れる。第２ソース端子Ｓ２に対して第１ソース端子Ｓ１に高電圧を印加し、第１ソース端子Ｓ１より高い電圧をゲート端子Ｇに印加することで、第１、第２ｎソース領域５９、６０とｎドレイン領域５４に挟まれたｐオフセット領域５側面にチャネルが形成されて第１ソース端子Ｓ１から第２ソース端子Ｓ２に電流が流れる。このように、双方向に電流を流すことができる双方向ＴＬＰＭとなる。一方、ゲート端子Ｇを第１、第２ソース端子Ｓ１、Ｓ２の内の低電位側の端子の電位にするか、グランド電位にすることで、ｐオフセット領域５に形成されたチャネルを消滅させて双方向ＴＬＰＭを阻止状態とすることができる。   The operation of the bidirectional TLPM 50 will be described with reference to the equivalent circuit diagram of FIG. By applying a high voltage to the second source terminal S2 with respect to the first source terminal S1 and applying a voltage higher than the second source terminal S2 to the gate terminal G, the first and second n source regions 59 of FIG. A channel is formed on the side surface of the p offset region 55 sandwiched between 60 and the n drain region 54, and a current flows from the second source terminal S2 to the first source terminal S1. By applying a high voltage to the first source terminal S1 with respect to the second source terminal S2 and applying a voltage higher than that of the first source terminal S1 to the gate terminal G, the first and second n source regions 59, 60 and n A channel is formed on the side surface of the p offset region 5 sandwiched between the drain regions 54, and a current flows from the first source terminal S1 to the second source terminal S2. In this way, the bidirectional TLPM can flow current in both directions. On the other hand, the channel formed in the p offset region 5 is extinguished by setting the gate terminal G to the potential of the low potential side of the first and second source terminals S1 and S2 or to the ground potential. Bidirectional TLPM can be blocked.

以上説明した実施例では、ゲート端子Ｇ一つの場合について説明したが、二つのＭＯＳＦＥＴに、それぞれゲート端子を設け、それぞれ別々に制御する構成とすることもできる。また、ｎドレイン領域５４を形成したが、ｎドレイン領域５４を形成しなくてもよい。この場合、ｐオフセット領域５５を酸化膜５６ａと接しない深さとすることが望ましい。
さらに、ｐオフセット２、５５はトレンチ５、５３を形成する前に拡散形成したが、トレンチ５、５３を形成する後に形成しても構わない。
さらにまた、以上の実施例において、ｐオフセット２、５５は、シリコン基板１、５１の表面から拡散形成した場合について説明したが、エピタキシャル成長により形成した場合であっても構わない。また、このとき、ｎソース領域１４、５９、６０をエピタキシャル成長により形成してもよい。 In the embodiment described above, the case of one gate terminal G has been described. However, it is also possible to provide a configuration in which each of the two MOSFETs is provided with a gate terminal and is controlled separately. Further, although the n drain region 54 is formed, the n drain region 54 may not be formed. In this case, it is desirable that the p offset region 55 has a depth that does not contact the oxide film 56a.
Further, the p offsets 2 and 55 are diffused before the trenches 5 and 53 are formed, but may be formed after the trenches 5 and 53 are formed.
Furthermore, in the above embodiment, the p offsets 2 and 55 have been described as being formed by diffusion from the surface of the silicon substrates 1 and 51, but they may be formed by epitaxial growth. At this time, the n source regions 14, 59, 60 may be formed by epitaxial growth.

本発明の半導体装置にかかる半導体基板の要部断面図である。It is principal part sectional drawing of the semiconductor substrate concerning the semiconductor device of this invention. 本発明の半導体装置の製造方法を製造工程順に示す半導体基板の要部断面図（その１）である。It is principal part sectional drawing (the 1) which shows the manufacturing method of the semiconductor device of this invention in order of a manufacturing process. 本発明の半導体装置の製造方法を製造工程順に示す半導体基板の要部断面図（その２）である。It is principal part sectional drawing (the 2) of the semiconductor substrate which shows the manufacturing method of the semiconductor device of this invention in order of a manufacturing process. 本発明の半導体装置の製造方法を製造工程順に示す半導体基板の要部断面図（その３）である。It is principal part sectional drawing (the 3) which shows the manufacturing method of the semiconductor device of this invention in order of a manufacturing process. 本発明の半導体装置の製造方法を製造工程順に示す半導体基板の要部断面図（その４）である。It is principal part sectional drawing (the 4) which shows the manufacturing method of the semiconductor device of this invention in order of a manufacturing process. 本発明の半導体装置の製造方法を製造工程順に示す半導体基板の要部断面図（その５）である。It is principal part sectional drawing (the 5) of the semiconductor substrate which shows the manufacturing method of the semiconductor device of this invention in order of a manufacturing process. 本発明の半導体装置の製造方法を製造工程順に示す半導体基板の要部断面図（その６）である。It is principal part sectional drawing (the 6) of the semiconductor substrate which shows the manufacturing method of the semiconductor device of this invention in order of a manufacturing process. 本発明の半導体装置の製造方法を製造工程順に示す半導体基板の要部断面図（その７）である。It is principal part sectional drawing (the 7) which shows the manufacturing method of the semiconductor device of this invention in order of a manufacturing process. 本発明の半導体装置の製造方法を製造工程順に示す半導体基板の要部断面図（その８）である。It is principal part sectional drawing (the 8) which shows the manufacturing method of the semiconductor device of this invention in order of a manufacturing process. 従来の半導体装置にかかる半導体基板の要部断面図である。It is principal part sectional drawing of the semiconductor substrate concerning the conventional semiconductor device. 従来の半導体装置の製造方法を製造工程順に示す半導体基板の要部断面図（その１）である。It is principal part sectional drawing (the 1) of the semiconductor substrate which shows the manufacturing method of the conventional semiconductor device in order of a manufacturing process. 従来の半導体装置の製造方法を製造工程順に示す半導体基板の要部断面図（その２）である。It is principal part sectional drawing (the 2) of the semiconductor substrate which shows the manufacturing method of the conventional semiconductor device in order of a manufacturing process. 従来の半導体装置の製造方法を製造工程順に示す半導体基板の要部断面図（その３）である。It is principal part sectional drawing (the 3) of the semiconductor substrate which shows the manufacturing method of the conventional semiconductor device in order of a manufacturing process. 従来の半導体装置の製造方法を製造工程順に示す半導体基板の要部断面図（その４）である。It is principal part sectional drawing (the 4) of the semiconductor substrate which shows the manufacturing method of the conventional semiconductor device in order of a manufacturing process. 特許文献１にかかる半導体装置の製造方法を製造工程順に示す半導体基板の要部断面図である。FIG. 10 is a cross-sectional view of a principal part of a semiconductor substrate showing a method of manufacturing a semiconductor device according to Patent Document 1 in order of manufacturing steps. 本発明にかかる、異なる半導体装置の半導体基板の要部断面図である。It is principal part sectional drawing of the semiconductor substrate of a different semiconductor device concerning this invention. 本発明にかかる、図１５の半導体装置の等価回路図である。FIG. 16 is an equivalent circuit diagram of the semiconductor device of FIG. 15 according to the present invention.

符号の説明Explanation of symbols

１… シリコン基板、
２… ｐオフセット領域
３… シリコン酸化膜、マスク酸化膜
４、７… シリコン窒化膜
５… トレンチ
６、１２… ゲート酸化膜
８… トレンチ側壁
９… 追加（２段目）トレンチ
１０… ｎドレイン領域
１１… 選択酸化膜
１３… ドープトポリシリコンゲート電極
１４… ｎソース領域
１５… 層間絶縁膜
１６−１、１６−２ 開口部
１７−１、１７−２ バリアメタル
１８−１、１８−２ 埋め込みプラグ
１９−１、１９−２ 金属電極配線。

1 ... Silicon substrate,
2 ... p offset region 3 ... silicon oxide film, mask oxide film 4, 7 ... silicon nitride film 5 ... trench 6, 12 ... gate oxide film 8 ... trench sidewall 9 ... additional (second stage) trench 10 ... n drain region 11 ... selective oxide film 13 ... doped polysilicon gate electrode 14 ... n source region 15 ... interlayer insulating film 16-1, 16-2 opening 17-1, 17-2 barrier metal 18-1, 18-2 buried plug 19 -1, 19-2 Metal electrode wiring.

Claims (5)

半導体基板の表面に形成した第一窒化膜をマスクとして第一トレンチを形成する工程と、前記第一トレンチの側壁に形成した第二窒化膜と前記第一窒化膜とをマスクとして前記第一トレンチの底部に第二トレンチを形成する工程と、前記第一窒化膜と前記第二窒化膜をマスクとして前記第二トレンチ内面に熱酸化膜を形成する工程と、前記第一窒化膜と第二窒化膜とを除去した後、第一トレンチ側壁にゲート絶縁膜を介してゲート電極を形成する工程とを含むことを特徴とする半導体装置の製造方法。 Forming a first trench using the first nitride film formed on the surface of the semiconductor substrate as a mask; and forming the first trench using the second nitride film and the first nitride film formed on a sidewall of the first trench as a mask. Forming a second trench at the bottom of the substrate, forming a thermal oxide film on the inner surface of the second trench using the first nitride film and the second nitride film as a mask, and the first nitride film and the second nitride. And a step of forming a gate electrode on the side wall of the first trench through a gate insulating film after removing the film. 半導体基板の表面に露出する一導電型領域の表面に窒化膜を含む絶縁膜を所定パターンに形成する第一マスク絶縁膜を形成し、第一マスク絶縁膜をマスクとしてトレンチを形成する第一トレンチ形成工程と、該第一トレンチ側壁に窒化膜を含む第二マスク絶縁膜を形成し、第二マスク絶縁膜および前記第一マスク絶縁膜をマスクとして前記第一トレンチ底部に連続する追加トレンチを形成する第二トレンチ形成工程と、前記第二トレンチの内面に接合端が前記第一トレンチ側壁に至る他導電型ドレイン領域を形成するドレイン形成工程と、熱酸化により前記第二トレンチ内面に選択的に酸化膜を形成する選択酸化膜形成工程と、前記第一絶縁膜および第二絶縁膜を除去し、第一トレンチの側壁にゲート絶縁膜と該ゲート絶縁膜を介してポリシリコンゲート電極を形成するＭＯＳゲート構造の形成工程と、前記一導電型領域表面に形成され、一端が第一トレンチ側壁に露出する他導電型ソース領域を形成するソース形成工程とを含むことを特徴とする半導体装置の製造方法。 Forming a first mask insulating film that forms an insulating film including a nitride film in a predetermined pattern on the surface of one conductivity type region exposed on the surface of the semiconductor substrate, and forming a trench using the first mask insulating film as a mask; Forming a second mask insulating film including a nitride film on the sidewall of the first trench, and forming an additional trench continuous to the bottom of the first trench using the second mask insulating film and the first mask insulating film as a mask A second trench forming step, a drain forming step of forming a drain region of another conductivity type whose junction end reaches the side wall of the first trench on the inner surface of the second trench, and selectively forming the inner surface of the second trench by thermal oxidation. A selective oxide film forming step for forming an oxide film, the first insulating film and the second insulating film are removed, and a gate insulating film is formed on the side wall of the first trench via the gate insulating film; A step of forming a MOS gate structure for forming a congate electrode; and a source forming step of forming another conductivity type source region formed on the surface of the one conductivity type region and having one end exposed at the side wall of the first trench. A method for manufacturing a semiconductor device. 前記ポリシリコンゲート電極は、ポリシリコンを少なくとも前記第一トレンチを埋めないように前記半導体基板表面および前記第二トレンチの底部に堆積された前記ポリシリコンを除去することにより形成し、前記ソース形成工程の後に、前記半導体基板全面に層間絶縁膜を堆積する工程と、該層間絶縁膜の表面から前記ソース領域およびドレイン領域に達する開口部を形成する工程とを有することを特徴とする請求項２記載の半導体装置の製造方法。 The polysilicon gate electrode is formed by removing the polysilicon deposited on the surface of the semiconductor substrate and the bottom of the second trench so as not to fill at least the first trench, and the source forming step 3. The method of claim 2, further comprising: depositing an interlayer insulating film over the entire surface of the semiconductor substrate; and forming openings reaching the source region and the drain region from the surface of the interlayer insulating film. Semiconductor device manufacturing method. 半導体装置がトレンチＭＯＳゲート構造を有する横型ＭＯＳＦＥＴであることを特徴とする請求項１乃至３のいずれか一項に記載の半導体装置の製造方法。 4. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a lateral MOSFET having a trench MOS gate structure. 半導体装置が双方向のＭＯＳＦＥＴであることを特徴とする請求項1または２記載の半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a bidirectional MOSFET.
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