JP2003008008A - Insulated gate semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that the reductions of the on-resistances of the planar transistors of an insulated gate semiconductor device largely relies upon the device or lithography in such a way that the cell densities of the transistors must be improved by scale-down etc., and, when the scale-down is advanced further, the gate lengths of the transistors become shorter due to a scaling rule, and the withstand voltages of the transistors are deteriorated depending upon impressed gate voltages. SOLUTION: The insulated gate semiconductor device is constituted in a multilayered structure by alternately laminating the gate electrode layers and channel layers of planar transistors upon another. Consequently, a structure in which the planar transistors are arranged in parallel can be realized and the gate width of the device also increases in proportion to the number of laminated layers. Therefore, the total on-resistance of the semiconductor device can be reduced without reducing the size of the device nor relying upon lithography technology.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate semiconductor device and a method of manufacturing the same, and more particularly to an insulated gate semiconductor device and a method of manufacturing the same that can reduce ON resistance by increasing a channel width.

[0002]

2. Description of the Related Art With the popularization of portable terminals, small-sized and large-capacity lithium-ion batteries have been required. The protection circuit for battery management of charge and discharge of the lithium ion battery must be smaller and sufficiently resistant to load short circuit due to the need for weight reduction of the mobile terminal. Such a protection circuit is required to be miniaturized because it is built in the container of the lithium-ion battery, and a COB (Chip on Boar) that uses a lot of chip parts is required.
d) Technology has been used to meet the demand for miniaturization. However, on the other hand, the power MOS is connected in series with the lithium ion battery.
Since FETs are connected, there is a need to make the on-resistance of this power MOSFET extremely small, and this is an essential element in a mobile phone in order to lengthen the call time and standby time.

Therefore, development of increasing cell density by microfabrication has been advanced in manufacturing chips. Specifically, by reducing the cell size, the cell density is significantly increased from the conventional 7.5 million cells / inch ² to 25 million cells / inch ² , and the conventional planar MOSFET
On the other hand, in the trench type power MOSFET, about 33%
It has become possible to reduce the on resistance of.

Referring to FIG. 17, a conventional trench type power M
The structure of the OSFET is shown by taking the N-channel type as an example. FIG. 17
17A is a top view and FIG. 17B is a cross-sectional view.

According to FIG. 17A, a trench type MOS is provided.
The FET includes a lattice-shaped trench 27, a gate electrode 33 embedded in the trench 27, a source region 35 provided along the trench 27, and a body contact region 34 provided in a region surrounded by the source region 35. Composed of. The interlayer insulating film and the source electrode are omitted.

Also, the portion shown by the broken line is a trench type MO.
It becomes one cell 38 of the SFET.

The trench 27 has a width of about 1 μm and is formed in a lattice pattern with an interval of about 5 μm on the actual operating region, and its inner wall is covered with a gate oxide film (not shown). In the trench 27,
A gate electrode 33 is provided by burying polysilicon and introducing impurities to reduce the resistance.

The body contact region 34 has a square shape or a shape similar thereto and is formed in an island shape surrounded by the source region 35 in order to stabilize the potential of the substrate.

The source region 35 is provided along the trench 27 and has a square shape or a shape similar thereto. The channel is formed in the depth direction of the trench 27 from the source region 35 and adjacent to the gate electrode 33 via a gate oxide film (not shown). The gate width W is the width of the channel serving as the current path, and in this case, the gate width of one basic cell is 4
× W2.

FIG. 17B shows a trench type MOSFE.
A sectional structure of T is shown.

On the N ⁺ type silicon semiconductor substrate 21, N ⁻
A drain region 22 made of a positive type epitaxial layer is provided, and a P type channel layer 24 is provided on the surface thereof. A trench 27 penetrating the channel layer 24 and reaching the drain region 22 is provided, and the inner wall of the trench 27 is covered with the gate oxide film 3
A gate electrode 33 made of polysilicon, which is coated with 1 and is filled in the trench 27, is provided. An N ⁺ type source region 35 is formed on the surface of the channel layer 24 adjacent to the trench 27, and a P ⁺ type body contact region 34 is provided on the surface of the channel layer 24 between two adjacent source regions 35. Further, when the gate electrode 33 is applied, a channel serving as a current path is formed from the source region 35 along the trench 27 as shown by a broken line. The gate electrode 33 is covered with an interlayer insulating film 36, and a source electrode 37 that contacts the source region 35 and the body contact region 34 is provided.

Referring to FIGS. 18 to 21, the manufacturing process of a conventional power MOSFET having a trench structure will be described.

In FIG. 18, an N ⁺ type silicon semiconductor substrate 2 is shown.
A drain region 22 is formed by laminating an N ⁻ type epitaxial layer on the substrate 1. After the oxide film 23 is formed on the surface, the oxide film 23 in the portion of the planned channel layer 24 is etched. A dose amount of 1.
After implanting boron at 0 × 10 ^13, it is diffused to form a P-type channel layer 24.

NSG (Non-d
a CVD oxide film 25 of an open silicate glass) with a thickness of 3000 Å, and a mask made of a resist film is applied to remove a portion to be a trench opening, and C
The VD oxide film 25 is partially removed by dry etching to form a trench opening where the channel layer 24 is exposed to a frontage of about 1.0 μm.

Next, using the CVD oxide film 25 as a mask, the silicon semiconductor substrate in the trench opening is CF-based and HB-based.
Dry etching is performed using an r-based gas to form a trench 27 that penetrates the channel layer 24 and reaches the drain region 22 and has a depth of about 2.0 μm.

Further, dummy oxidation is performed to form a dummy oxide film of about 3000 Å on the inner wall of the trench 27 and the surface of the channel layer 24 to remove etching damage during dry etching. By removing the dummy oxide film formed by this dummy oxidation and the CVD oxide film 25 simultaneously with an oxide film etchant such as hydrofluoric acid, a stable gate oxide film can be formed. Further, the opening of the trench 27 is rounded by thermal oxidation at a high temperature, and the trench 2
There is also an effect of avoiding the electric field concentration at the opening of No. 7.

In FIG. 19, the entire surface is thermally oxidized to form a gate oxide film 31 with a thickness of, for example, about 700 Å according to a threshold value.
Then, the gate electrode 33 embedded in the trench 27 is formed. That is, a non-doped polysilicon layer 32 is deposited on the entire surface, phosphorus is injected and diffused at a high concentration to increase the conductivity, and the gate electrode 33 is formed. After that, the polysilicon layer 32 deposited on the entire surface is dry-etched without a mask to leave the gate electrode 33 buried in the trench 27.

In FIG. 20, boron is selectively ion-implanted with a mask of the resist film PR at a dose amount of 5.0 × 10 ¹⁴ to form a P ⁺ type body contact region 34, and then the resist film PR is removed. Thereafter, a new resist film PR is used for the planned source region 35 and gate electrode 33.
Mask to expose the arsenic and dose arsenic 5.0 × 1
After ion implantation at 0 ¹⁵ to form the N ⁺ type source region 35 on the surface of the channel layer 24 adjacent to the trench 27, the resist film PR is removed.

In FIG. 21, BPSG (Boron) is formed on the entire surface.
Phosphorus Silicate Glass
The s) layer is deposited by the CVD method to form the interlayer insulating film 36. After that, the interlayer insulating film 36 is left at least on the gate electrode 33 using the resist film as a mask. After that, aluminum is deposited on the entire surface by a sputtering apparatus to form a source electrode 37 that contacts the source region 35 and the body contact region 34.

[0020]

Generally, a power MOSF is used.
The ET on-resistance r _m is expressed by the following equation.

R_m= L / (WC_OX(V_GS-V_th)) In the above formula, L: gate length W: gate width C_OX: Ge
Capacity of oxide film V _GS: Gate applied voltage V_th: Shiki
Value.

According to this r _m , various parameters can be improved in order to reduce the on-resistance, but the on-resistance can be reduced by increasing the gate width W (width of the current path), for example.

In the trench type power MOSFET described above, the gate width W is the sum of the widths W2 of the source regions formed around the trench as shown in FIG. In the trench type power MOSFET, since the vertical channel is formed in the direction perpendicular to the substrate surface, the unit cell can be downsized and the number of unit cells per unit area can be increased as long as the processing accuracy allows.

However, the processing accuracy of the trench depends largely on the lithography technique and the exposure apparatus, and there is a limit to miniaturization of the trench type power MOSFET.
If the number of cells does not increase, the gate width W naturally does not increase any more, and there is a problem that the on-resistance cannot be reduced due to the increase in the gate width W.

Further, as miniaturization progresses, the current path of the trench type power MOSFET is changed to the epitaxial layer and the N
It bends outward at the interface of the mold substrate and merges with the current paths of adjacent cells, resulting in an excessive current density. It is considered that the current is saturated in the portion where the current density is excessive and a resistance component is generated in that portion. In this respect as well, there is a limit to the increase in the number of unit cells per unit area.

[0026]

The present invention has been made in view of the above problems, and one channel layer on the surface of a semiconductor substrate of one conductivity type, and one of the opposite conductivity type provided separately on the surface of the channel layer. One source region and a drain region, and a plurality of gate electrode layers and other channel layers that are alternately laminated on the channel layer adjacent to the source region and the drain region. The parallel connection of the transistors is realized by forming the gate electrode and the channel layer of the existing planar transistor into two or more layers. This makes it possible to increase the gate width W regardless of the miniaturization technique, and can significantly reduce the on-resistance as compared with the conventional structure.

Further, a step of forming an insulating film on a semiconductor substrate of one conductivity type to be one channel layer and forming a gate electrode layer made of a semiconductor material on the insulating film, and forming the insulating film on the entire surface. A step of covering the gate electrode layer with an insulating film,
Forming a semiconductor layer of one conductivity type to be another channel layer on the gate electrode layer, alternately stacking a plurality of the gate electrode layers and other channel layers, and inverting the surface of the one channel layer. Forming one source region and drain region of conductivity type and simultaneously forming another source region and drain region at both ends of another channel layer, without introducing new equipment.
It is possible to provide a method of manufacturing an insulated gate semiconductor device that can reduce the on-resistance by increasing the gate width W.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail with reference to FIGS.

FIG. 1 shows a stack type MOSFE of the present invention.
The structure of T is shown by taking an N channel type as an example.

The cell of the stack type MOSFET includes a first channel layer 1, a gate electrode layer 5, a first source region 8 and a drain region 9, another channel layer 6, another source region 10 and a drain. The stack type MOSFET includes a region 11, a source electrode 12 and a drain electrode 13, and a gate electrode 14, and a large number of these cells are arranged in the stacked MOSFET.

The first channel layer 1 is a P-type silicon semiconductor substrate.

The gate electrode layer 5 is made of silicon single crystal or polysilicon into which impurities are introduced to enhance conductivity, and on the first channel layer 1 adjacent to the first source region 8 and the drain region 9, A plurality of layers are alternately stacked with the other channel layers 6. Further, a gate oxide film 2 is provided so as to cover the four side surfaces around it.

First source region 8 and drain region 9
Are N ⁺ -type regions that are provided on the surface of the first channel layer 1 with a gate length L and are separated from each other, and are adjacent to the first-layer gate electrode layer 5.

The other channel layer 6 is a P-type semiconductor layer made of silicon single crystal or polysilicon which is alternately laminated on the gate electrode layer 5 in plural, and has another source region at both ends thereof. 10 and an N ⁺ type region serving as the drain region 11. The sum of the lengths (W1) of the contact between the channel layer and the gate electrode layer is the gate width W, and a channel is formed along the gate electrode layer 5 in the other channel layer 6. That is, channels are formed vertically in the channel layer 6 sandwiched between the gate electrode layers 5,
Also, the gate width W increases in proportion to the number of stacked other channel layers 6.

Another source region 10 and drain region 1
Reference numeral 1 denotes N ⁺ type regions formed at both ends of the other channel layer 6, all the other source regions 10 are in contact with the source electrode 12, and all the other drain regions 11 are in contact with the drain electrode 13.

The gate electrode 14 is made of a conductive material such as polysilicon having impurities introduced therein, or a metal, extends the gate electrode layer 5 and is laminated, and is brought into contact with all of them.

The source electrode 12 is in contact with all of the first source region 8 and the other source region 10, and the drain electrode 13 is in contact with the first drain region 9 and the other drain region 1.
Contact all 1s. Each of them is formed of a semiconductor material such as polysilicon or a metal into which impurities are introduced.

A region sandwiched between the source electrode 12 and the drain electrode 13 is one cell of a stack type MOSFET, and adjacent cells commonly use the source electrode or the drain electrode as shown in FIG. Many cells are arranged. In the adjacent cell, the other source region 10 and drain region 11 are connected to the source electrode 12
Alternatively, the drain electrodes 13 are symmetrically formed.

FIG. 2 shows an example of the wiring layer. A large number of stack type MOSFET cells 18 shown by the alternate long and short dash line are continuously arranged. The source electrode 12 is the source wiring layer 1
5, and the drain electrode 13 is connected between the cells by
The drain wiring layer 16 connects the cells. The gate electrode 14 extends and is connected between adjacent cells.
For example, the gate electrode 14 serves as the first wiring layer, and the source wiring layer 15 and the drain wiring layer 16 serving as the second layer are formed via an insulating film or the like.

The wiring pattern shown in FIG. 2 is an example, and the source electrode 12 and the drain electrode 13 are provided between the cells.
If the gate electrode 14 and the gate electrode 14 are connected to each other, the number is not limited to this.

FIG. 3 shows a stack type MOSFET of the present invention.
2 shows a top view and a cross-sectional view of one cell of FIG. Figure 3 (A)
Is a top view, and FIG. 3B is a sectional view taken along the line AA.

Source electrode 12 and drain electrode 13
Are provided adjacent to the gate electrode layer 5 and the other channel layer 6 on the semiconductor substrate.

The gate electrode 14 is the entire gate electrode layer 5
It is provided in contact with. The gate electrode layer 5 is laminated without interposing another channel layer at the contact portion with the gate electrode 14, and the gate electrode layer 5 is formed by etching.
A conductive material such as polysilicon or metal into which impurities have been introduced is buried by providing a contact hole penetrating therethrough.

The feature of the present invention resides in the alternately laminated gate electrode layers 5 and other channel layers 6. With this structure, a channel is formed in the other channel layer 6 on the surface in contact with the gate electrode layer 5 through the gate oxide film 2.
As shown in FIGS. 1 and 3B, the sum of the length W1 of contact between the channel layer and the gate electrode layer 5 is the gate width W, which is proportional to the number of stacked gate electrode layers 5 and other channel layers 6. As a result, the gate width W also increases. In other words, it has a structure in which a plurality of transistors are connected in parallel with the size of the conventional planar type MOSFET, and the ON resistance is one fourth and three layers when the gate electrode layer 5 has two layers as compared with the one layer planar type transistor. In this case, the on-resistance becomes 1/6. In addition, the gate width W also increases in proportion to the number of stacked layers,
Since the channel is formed above and below the channel layer 6 sandwiched by the gate electrode layers 5, the gate width W becomes four times in the case of two layers, and the gate width W becomes six times in the case of three layers. The values of the on-resistance and the gate width W are as shown in FIG. 1 when the gate electrode layers 5 and the channel layers 6 are alternately stacked and the uppermost layer is the channel layer 6.

FIG. 4 shows a concrete conventional planar type M.
The comparison of OSFET and trench type MOSFET and the stack type MOSFET of this invention is shown. FIG. 4A is a comparison of ON resistance, and FIG. 4B is a comparison of gate width W. In this calculation, the chip size is 2.3 x 2.8 mm
Then, this is an example of the case where the respective elements are arranged in the same chip size with reference to the trench type MOSFET having the ON resistance of 8 mmΩ. The gate length L of the planar MOSFET and the stack MOSFET of the present invention are both 5 μm.
m, and the stack type MOSFET is as shown in FIG.
This is the case where the uppermost layer is the channel layer 6.

According to FIG. 4 (A), the stack type MOSFET of the present invention has 27.8 mmΩ in one layer, but has two gate electrode layers and an ON resistance of 6.95 mmΩ. It is less than 8 mmΩ and 10 when compared with the conventional planar MOSFET.
About 30% reduction with respect to mmΩ. Furthermore, if the stack type MOSFET of the present invention has three layers, 4.6.
It becomes mmΩ.

According to FIG. 4B, the conventional planar MOSFET has a gate width W of about 1.3 million μm under the conditions of the present calculation, and the trench MOSFET has about 5 μm.
It is 400,000 μm. In the stack type MOSFET of the present invention, the thickness of one layer is 900,000 μm, but since it increases in proportion to the gate electrode layer, the trench type MOSFET has three or more layers.
It turns out that it exceeds.

That is, in comparison of the on-resistance, the number of gate electrode layers is two or more, which is smaller than that in the conventional technique. In comparison of the gate width W, the number of gate electrode layers is three or more, which is higher than that of the conventional technique and the on-resistance is reduced. It is possible. Here, the calculations are for comparison of the on-resistances, but the reason why the effect is different is due to the difference in structure.
In OSFET, this includes the resistance of the epitaxial layer and the resistance of the N ⁺ type substrate. However, the stack type MO of the present invention
In the SFET structure, the resistance component is only the channel layer resistance. In the comparison of the on-resistances, better results are obtained than in the case of simply comparing the gate widths W.

However, in any case, the gate width W can be increased as much as possible in proportion to the number of the gate electrode layers 5 and the other channel layers 6 to be laminated. Without depending on
The conventional design rule and chip size can significantly reduce the on-resistance.

In the structure of the present invention, the gate electrode layers 5 and the channel layers 6 may be laminated alternately, and the uppermost layer may be the gate electrode layer 5.

Next, with reference to FIGS. 5 to 16, the method of manufacturing the stack type power MOSFET of the present invention will be described by taking the N channel type as an example. In the following description of the manufacturing method, only one cell is shown.

A method of manufacturing a trench type power MOSFET comprises a step of forming an insulating film on a semiconductor substrate of one conductivity type to be one channel layer, and forming a gate electrode layer made of a semiconductor material on the insulating film. Forming an insulating film on the entire surface and covering the gate electrode layer with an insulating film; forming a one-conductivity-type semiconductor layer to be another channel layer on the gate electrode layer; Alternately laminating a plurality of channel layers, and forming one source region and drain region of opposite conductivity type on the surface of the one channel layer, and simultaneously forming another source region and drain region at both ends of another channel layer. And a process of forming.

In the first step of the present invention, as shown in FIGS. 5 and 6, an insulating film is formed on a semiconductor substrate of one conductivity type which will be the first channel layer, and a semiconductor material is formed on the insulating film. Forming a gate electrode layer.

In FIG. 5, the P-type silicon semiconductor substrate to be the first channel layer 1 is oxidized at about 800 ° C., and a gate oxide film 2 of about several hundred Å is formed by a driving voltage.

FIG. 6 shows the formation of a gate electrode layer made of a semiconductor material on the insulating film. As a first embodiment of the formation of a silicon semiconductor layer to be the gate electrode layer, SPE (So
lid-phase epitaxy).

In FIG. 6 (A), for SPE, an opening 3 having a width of about 1 μm is formed in the gate oxide film 2 in a region adjacent to the intended gate electrode layer to expose the first channel layer, Amorphous silicon is deposited on the entire surface at about 560 ° C. The opening 3 is also utilized when forming one source and drain region later, and the source and drain electrodes are in contact with each other. afterwards,
By annealing at about 500 ° C., amorphous silicon is sputtered from the opening 3 of the gate oxide film 2 as a starting point.
A single crystal is formed by E (solid phase epitaxial growth).
As a result, the silicon semiconductor layer 4 to be the gate electrode layer is formed.

Here, as a second embodiment of forming the silicon semiconductor layer 4, MBE (Molecular beam Epitaxy) is used.
y: a molecular beam epitaxy) is used to deposit silicon molecules to form a silicon single crystal layer, or a known method is used to deposit polysilicon, the details of which will be described later.

After that, as shown in FIG. 6B, phosphorus or the like is injected / diffused at a high concentration over the entire surface of the silicon semiconductor layer 4 to reduce the resistance. For example, the gate width W = 20 μm and the gate length L = 5 μm. Then, the gate electrode layer 5 is formed on the first channel layer 1 with the gate oxide film 2 interposed therebetween.

The second step of the present invention is to form an insulating film on the entire surface and cover the gate electrode layer with the insulating film, as shown in FIG.

On the gate electrode layer 5, in order to form another channel layer, it is oxidized at about 800 ° C., and the gate oxide film 2 of about several hundred Å is formed again by the driving voltage. As a result, the four side surfaces around the gate electrode layer 5 are covered with the gate oxide film 2.

The third step of the present invention is to form, on the gate electrode layer, a semiconductor layer of one conductivity type which becomes another channel layer, as shown in FIG.

First, in FIG. 8A, since the opening 3 for the SPE is covered with the gate oxide film 2, it is opened again by etching to expose the first channel layer 1. Similar to the formation of the gate electrode layer 5, amorphous silicon is deposited on the entire surface at about 560 ° C., and then 5
Anneal at about 00.degree. Amorphous silicon is monocrystallized by this SPE, and a silicon semiconductor layer 4 similar to the gate electrode layer 5 is formed. After that, as shown in FIG. 8B, another channel layer 6 is formed by introducing a P-type impurity and etching into a desired shape. The channel layer is shown in FIG.
As shown in (B), it is etched to have a desired width W1.

As shown in FIG. 9, the fourth step of the present invention is to alternately stack a plurality of the gate electrode layers and the other channel layers.

This step is the step which is the first characteristic of the present invention, and by repeating the above first to fourth steps a plurality of times, as shown in FIGS. 9 (A) to 9 (C). A plurality of electrode layers 5 and other channel layers 6 are alternately laminated. As a result, a plurality of gate electrode layers 5 whose side surfaces are covered with the gate oxide film 2 and a plurality of channel layers 6 are alternately laminated.

By forming a source region and a drain region at both ends of another channel layer in a later step, a plurality of transistors can be connected in parallel, and if the gate electrode layer 5 has two layers, the on-resistance is 4 If it is one-third or three layers, it will be one-sixth. In addition, since the gate width W increases in proportion to the number of stacked layers, the gate width W becomes four times the gate electrode layer 5 when the number of the gate electrode layers 5 is two, and the gate width W becomes six times when the number of the three layers is three. It should be noted that this value is obtained when the gate electrode layers 5 and the channel layers 6 are alternately laminated and the uppermost layer is the channel layer 6. Therefore, the cell density is not improved by miniaturization, but the on-resistance of the basic transistor element itself can be reduced.

Further, since it can be realized by the conventional design rule without depending on the lithography technique or the apparatus, the power M for reducing the on-resistance without introducing new equipment.
OSFETs can be manufactured.

The fifth step of the present invention is as shown in FIG.
The first source and drain regions of opposite conductivity type are formed on the surface of the first channel layer, and at the same time, other source and drain regions are formed at both ends of the other channel layer.

This step is the second characteristic step of the present invention. The first source region 8 and the drain region 9 and other source regions are formed by ion implantation or by diffusion from the source and drain electrodes in contact. 10 and the drain region 11 are formed to form a stack type power MOSFET in which a plurality of layers are stacked. As described above, since the basic elements are connected in parallel in multiples, the on resistance can be significantly reduced. The gate width W is also the sum of the width W1 at which the gate electrode layer 5 and the channel layer are in contact with each other, and channels are formed vertically in the other channel layers 6 sandwiched by the gate electrode layers 5, so that It grows in proportion to the number.
That is, the gate width W can be increased with the conventional chip size and design rule.

FIG. 10A shows a method of forming by ion implantation. The interlayer insulating film 7 is formed on the entire surface, and the opening 3 is formed.
Expose again. The opening 3 becomes a planned first source region and drain region adjacent to the first-layer gate electrode layer 5. At the same time, as shown in FIG. 3B, a groove for forming a gate electrode that contacts all of the extended gate electrode layer 5 is formed by etching.

N ⁺ -type impurities such as phosphorus are ion-implanted obliquely to form the first source region 8 and the drain region 9, and at the same time, the other source region 1 is formed on both ends of the other channel layer 6.
0 and drain region 11 are formed.

Thereafter, as shown in FIG. 10B, polysilicon is deposited on the entire surface, and the trench is filled with polysilicon.
Impurities of about × 10 ¹⁸ to 1 × 10 ²⁰ cm ^-3 are introduced to form the source electrode 12 in contact with all the source regions and the drain electrode 13 in contact with all the drain regions. Further, the gate electrode 14 that contacts all the gate electrode layers is formed (FIGS. 3A and 3B).
reference).

Here, the source electrode 12 and the drain electrode 1
3, the gate electrode 14 may be a metal such as aluminum or tungsten. Moreover, without ion implantation, as shown in FIG.
As shown in (B), the source electrode 12 and the drain electrode 13 are formed of polysilicon into which the impurities are introduced, and the impurities of the source electrode 12 and the drain electrode 13 are thermally diffused to form all the source regions and the drain regions. In that case, the gate electrode 14 may be made of metal such as aluminum or tungsten.

It should be noted that although it is omitted in FIG. 10 because one cell is described, in reality, the other channel layers 6 on both sides adjacent to the first source region 8 are closer to the first source region side. Another source region 10 is formed on the side wall of the. The same applies to the other drain regions 11.

On the other hand, FIGS. 11 to 15 show a second embodiment of forming the silicon semiconductor layer 4. As described above, the gate electrode layer 5 and the other channel layer 6 may be the silicon semiconductor layer 4, and the formation method thereof is MBE (Mole).
There is a method of depositing silicon molecules to form a silicon single crystal layer by cular beam epitaxy, or a method of depositing polysilicon by a known method.

FIG. 11 shows the gate oxide film 2 formed on the silicon semiconductor substrate which is the first channel layer 1 by the above-described method.
Then, silicon atoms are deposited on the entire surface by MBE, or polysilicon is deposited by a known method such as a CVD method to form the silicon semiconductor layer 4
Are formed (FIG. 11A). Furthermore, after introducing impurities,
The gate electrode layer 5 is formed by etching into a desired shape (FIG. 11B).

FIG. 12 shows the formation of the gate oxide film. The gate oxide film 2 of about several hundred liters is formed on the entire surface by the above-mentioned method according to the driving voltage, and the four side surfaces around the gate electrode layer 5 are covered.

FIG. 13 shows the formation of another channel layer.
Silicon semiconductor layer 4 with MBE or polysilicon on the entire surface
After the formation of impurities and the introduction of impurities, as shown in FIG. 3B, etching is performed to a desired width W1. After that, the gate oxide film 2 is formed on the entire surface.

Thereafter, as shown in FIGS. 14A and 14B, a plurality of gate electrode layers 5 and other channel layers 6 are alternately laminated.

Further, in FIG. 15, the planned source electrode and drain electrode portions are etched to form grooves, respectively, and the first channel layer 1 adjacent to the gate electrode layer 5 is exposed. At the same time, a groove is also formed by etching in a planned gate electrode portion.

The subsequent steps are the same as those in the fifth embodiment.
The process is the same as the process (FIG. 10) and thereafter.

Here, as shown in FIGS. 16A and 16B, in both cases, the first source region 8 and the drain region 9 are the first layer in the first and second embodiments. covers the gate electrode layer 5 in the form after the insulating film, the entire surface N ⁺
The type impurities may be diffused and formed on the surface of one channel layer 1.

In the manufacturing method of the present invention, the gate electrode layers 5 and the channel layers 6 may be alternately laminated, and the uppermost layer may be the gate electrode layer 5.

[0083]

According to the present invention, by stacking a plurality of gate electrode layers and a plurality of channel layers, a structure in which a plurality of transistors are connected in parallel can be realized. Can be reduced to In addition, the gate width W also increases in proportion to the number of stacked layers as long as stacking is possible. That is, in the present invention,
It is possible to reduce the ON resistance of the basic element itself.
In the conventional MOSFET, it is mainstream to increase the cell density and reduce the total on-resistance by miniaturization, and there are many points depending on the device and the lithography technique. However, in the present invention, by forming the transistors in a multi-layer structure, parallel connection of the transistors can be realized according to the conventional design rule or size. Focusing on the gate width W, the gate width W can be increased as much as possible in proportion to the number of stacked gate electrode layers and other channel layers. That is,
Instead of reducing the total on-resistance of the device by miniaturization,
This has the advantage that the on-resistance of each basic element of the transistor itself can be reduced.

Specifically, when the structure of the present invention is applied to a current trench type MOSFET chip effective for reducing the on-resistance, a trial calculation is made, and when the uppermost layer is a channel layer, two gate electrode layers are provided. Since four channel layers can be formed, the on-resistance is lower than that of the existing trench type MOSFET, and three gate electrode layers can form six channel layers, which reduces the on-resistance by about 40% compared to the existing trench type MOSFET. be able to.

Further, according to the manufacturing method of the present invention, the on-resistance of the basic element itself of the transistor can be reduced without depending on the manufacturing apparatus and the lithography technique. Since the design rule may be the same as the conventional one, there is an advantage that a power MOSFET with reduced on-resistance can be manufactured without introducing new equipment.

[Brief description of drawings]

FIG. 1 is a structural diagram illustrating an insulated gate semiconductor device of the present invention.

FIG. 2 is a top view illustrating an insulated gate semiconductor device of the present invention.

3A is a top view and FIG. 3B is a cross-sectional view illustrating an insulated gate semiconductor device of the present invention.

FIG. 4 is a characteristic diagram illustrating an insulated gate semiconductor device of the present invention.

FIG. 5 is a cross-sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

FIG. 6 is a cross-sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

FIG. 7 is a cross-sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

FIG. 8 is a cross-sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

FIG. 9 is a cross-sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

FIG. 10 is a cross-sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

FIG. 11 is a cross-sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

FIG. 12 is a cross-sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

FIG. 13 is a cross-sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

FIG. 14 is a cross-sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

FIG. 15 is a cross-sectional view illustrating the method for manufacturing the insulated gate semiconductor device of the present invention.

FIG. 16 is a cross-sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

17 (A) is a top view and FIG. 17 (B) is a cross-sectional view illustrating a conventional insulated gate semiconductor device.

FIG. 18 is a cross-sectional view illustrating the method of manufacturing a conventional insulated gate semiconductor device.

FIG. 19 is a cross-sectional view illustrating the method for manufacturing the conventional insulated gate semiconductor device.

FIG. 20 is a cross-sectional view illustrating the method of manufacturing the conventional insulated gate semiconductor device.

FIG. 21 is a cross-sectional view illustrating the method for manufacturing the conventional insulated gate semiconductor device.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/78 613Z (72) Inventor Eiichiro Kuwako 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Machinery Co., Ltd.F-term (reference) 4M104 AA01 BB01 BB02 BB18 BB40 CC01 CC05 DD06 DD15 DD35 DD43 DD55 DD78 DD92 FF01 FF06 FF26 GG09 GG10 GG14 GG18 HH20 5F048 AA01 AC06 BA01 BB02 BB19A05B09A05A08 BB09BD08 5B07A08B09A08A08 BB08BD05 BB08BD05 BB08A08 BB09BD08 BB08A08 BB08BD08 BB08BD08 BB08A08 EE30 EE33 EE36 EE41 FF02 FF22 GG02 GG12 GG13 GG22 GG41 HJ14 HL03 HL05 HM02 HM13 HM17 5F140 AA30 AB04 AB05 BA01 BB01 BB06 BC06 B11 B26 B25 B38B25 BG45B30 BG45B30 BG45 BG45 BG45 BG45 BG45 BG45 BG45 BG45 BG45 BG45 BG45 BG45 BG45 BK14

Claims (14)

[Claims] 1. A channel layer on the surface of a semiconductor substrate of one conductivity type, a source region and a drain region of the opposite conductivity type provided separately on the surface of the channel layer, and the source region and the drain region. And a plurality of gate electrode layers and other channel layers which are alternately stacked on the channel layer adjacent to the other gate layer and another channel layer. 2. The insulated gate semiconductor device according to claim 1, wherein the one source region and the drain region are in contact with the other channel layer by a conductive material, respectively. 3. A channel layer on the surface of a semiconductor substrate of one conductivity type, a source region and a drain region of the opposite conductivity type which are provided on the surface of the channel layer so as to be separated from each other, and the source region and the drain region. A plurality of gate electrode layers and other channel layers alternately stacked on the channel layer adjacent to the gate layer, a gate electrode that contacts all of the plurality of gate electrode layers, the one source region and the other channel layer An insulated gate semiconductor device comprising: a source electrode that contacts one end of the drain electrode and a drain electrode that contacts the other end of the one drain region and the other channel layer. 4. The plurality of cells of the insulated gate semiconductor device are arranged in succession, and the source electrode, the drain electrode, and the gate electrode between the cells are connected to each other. Insulated gate semiconductor device. 5. The insulated gate semiconductor device according to claim 1, wherein each of the gate electrode layers is covered with an insulating film around the periphery thereof. 6. The one-conductivity-type semiconductor layer in which the other channel layer is provided with another source and drain regions of opposite conductivity type at both ends thereof. Insulated gate type semiconductor device according to. 7. The insulated gate semiconductor device according to claim 1, wherein each of the gate electrode layers and the other channel layer are made of single crystal silicon or polysilicon. 8. A step of forming an insulating film on a semiconductor substrate of one conductivity type to be one channel layer and forming a gate electrode layer made of a semiconductor material on the insulating film, and forming an insulating film on the entire surface. A step of covering the gate electrode layer with an insulating film, a step of forming a one-conductivity-type semiconductor layer to be another channel layer on the gate electrode layer, and a plurality of the gate electrode layers and the other channel layers alternately. Laminating, and forming one source region and drain region of opposite conductivity type on the surface of the one channel layer and simultaneously forming another source region and drain region at both ends of the other channel layer. A method for manufacturing an insulated gate semiconductor device, comprising: 9. After laminating a plurality of the gate electrode layers and other channel layers, an impurity of opposite conductivity type is introduced into the entire surface to form one impurity in a region exposed adjacent to the gate electrode layer on the surface of the one channel layer. Forming a source region and a drain region and simultaneously forming another source region and a drain region at both ends of the other channel layer; and forming a source electrode that contacts the one source region and the other source region. Forming a drain electrode in contact with the one drain region and the other drain region, and forming a gate electrode in contact with all of the respective gate electrode layers. A method of manufacturing an insulated gate semiconductor device according to claim 1. 10. A reverse conductivity contacting a region exposed adjacent to the gate electrode layer on the surface of the one channel layer and both ends of the other channel layer after stacking a plurality of the gate electrode layers and the other channel layers. Forming a source electrode and a drain electrode made of polysilicon into which a type impurity is introduced, and forming a gate electrode in contact with all of the gate electrode layers, and removing impurities in the source electrode and the drain electrode Diffusing into all the channel layers to form the one source region and the drain region on the one channel surface, and forming the other source region and the drain region at both ends of the other channel layer. 9. The method for manufacturing an insulated gate semiconductor device according to claim 8. 11. A method of forming the one source region and the drain region on the surface of the one channel layer by covering the entire surface of the first gate electrode layer with an insulating film and then introducing an impurity of the opposite conductivity type. 9. The method for manufacturing an insulated gate semiconductor device according to claim 8. 12. The method for manufacturing an insulated gate semiconductor device according to claim 8, wherein each of the gate electrode layers and each of the semiconductor layers are formed into a silicon single crystal by solid phase epitaxial growth of amorphous silicon. 13. The method of manufacturing an insulated gate semiconductor device according to claim 8, wherein each of the gate electrode layers and each of the semiconductor layers is formed into a silicon single crystal by molecular beam epitaxy of silicon atoms. 14. The method of manufacturing an insulated gate semiconductor device according to claim 8, wherein each of the gate electrode layers and each of the semiconductor layers are formed of polysilicon.