JP2002343805A - Method of manufacturing insulating gate-type semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that about 44% of silicon is carved in the growing amount of the oxidized film of dummy oxidation, that a trench cannot be finished in a design value, and that a capacity value and on-resistance cannot be reduced although a process for performing dummy oxidation at a high temperature and removing the oxidized film is performed for removing the damage of dry etching, after the trench is formed in trench-type power MOSFET. SOLUTION: The trench is annealed in very high vacuum or hydrogen atmosphere after the trench is formed. Thus, the migration of silicon is generated, and the surface of silicon is made smooth without performing dummy oxidation. Thus, a dimension conversion difference can be reduced and the trench can be finished in the design value. Consequently, a manufacturing method for realizing highly reliable power MOSFET with low capacity, low on-resistance and high performance can be supplied.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an insulated gate semiconductor device, and more particularly to a method of manufacturing an insulated gate semiconductor device which improves the cell density and reduces the capacity by obtaining a fine trench as designed. It relates to a manufacturing method.

[0002]

2. Description of the Related Art With the spread of portable terminals, a small-sized and large-capacity lithium-ion battery has been required. The protection circuit for performing the battery management of the charging and discharging of the lithium ion battery must be smaller and capable of sufficiently withstanding a load short due to the need for reducing the weight of the portable terminal. Such a protection circuit is required to be miniaturized because it is built in a container of a lithium ion battery, and a COB (Chip on Boar) using a lot of chip components is required.
d) Technology has been used to meet the demand for miniaturization. However, on the other hand, a power MOS in series with a lithium ion battery
Since the FET is connected, there is a need to make the on-resistance of the power MOSFET extremely small, which is an indispensable factor for the mobile phone to increase the talk time and the standby time.

[0003] For this reason, in the production of chips, developments have been made to increase the cell density by fine processing. Specifically, in the planar structure in which the channel is formed on the surface of the semiconductor substrate, the cell density is 7.4 million cells / square inch, but in the first generation of the trench structure in which the channel is formed on the side surface of the trench, the cell density is 2500. Significantly improved to 10,000 pieces per square inch. Furthermore, in the second generation of the trench structure,
The cell density could be increased to 72 million cells / square inch by miniaturization.

The operating frequency of the CPU of a personal computer has also exceeded 500 MHz, and the current consumption of the CPU has also increased significantly. Therefore, built-in D
It is desired that the C / DC converter also performs high-speed switching correspondingly, and the power MOSFET used is also required to have high-speed switching characteristics.

When a power MOSFET is used in a switching operation, input capacitance, output capacitance, and feedback capacitance are important items for improving the switching speed. For example, a feedback capacitance is a capacitance between a gate and a drain in a power MOSFET. If the feedback capacitance is increased, a cutoff frequency is deteriorated, and a charging current required for switching on is increased and a rise is delayed. Is generated.

For this reason, the cell density has been improved by forming the cell into a trench structure, and a low on-resistance has been realized to some extent.

Referring to FIGS. 11 to 20, a process of manufacturing a conventional power MOSFET having a trench structure will be described.

In FIG. 11, an N ⁺ type silicon semiconductor substrate 2
A drain region 22 is formed by laminating an N ⁻ -type epitaxial layer on 1. After the oxide film 23 is formed on the surface, the oxide film 23 in the predetermined channel layer 24 is etched. Using this oxide film 23 as a mask, a dose of 1.
After implanting boron at 0 × 10 ¹³ , diffusion is performed to form a P-type channel layer 24.

FIGS. 12 to 15 show steps of forming a trench.

In FIG. 12, NSG is formed on the entire surface by CVD.
(Non-doped Silicate Glass
s) The CVD oxide film 25 is formed to a thickness of 3000 °.

In FIG. 13, a mask made of a resist film is applied except for a portion to be the trench opening 26, and the CVD oxide film 25 is partially removed by dry etching to remove the trench opening 26 where the channel region 24 is exposed. Frontage Approx.
It is formed to 0 μm.

In FIG. 14, the silicon semiconductor substrate in the trench opening 26 is dry-etched with a CF-based gas and an HBr-based gas using the CVD oxide film 25 as a mask.
A trench 27 having a depth of 0 μm is formed.

In FIG. 15, dummy oxidation is performed to form trench 27.
A dummy oxide film 28 of about 3000 ° is formed on the inner wall and the surface of the channel layer 24 to remove etching damage during dry etching. By removing the dummy oxide film 28 and the CVD oxide film 25 formed by the dummy oxidation simultaneously with an oxide film etchant such as hydrofluoric acid, a stable gate oxide film can be formed. Also, the opening of the trench 27 is rounded by thermal oxidation at a high temperature,
There is also an effect of avoiding electric field concentration at the opening of the trench 27.

In FIG. 16, a gate oxide film 31 is formed. That is, the entire surface is thermally oxidized to form a gate oxide film 31 having a thickness of, for example, about 700 ° according to the threshold value.

In FIG. 17, a gate electrode 33 buried in the trench 27 is formed. That is, a non-doped polysilicon layer 32 is deposited on the entire surface, and phosphorus is implanted at a high concentration.
The gate electrode 33 is formed by diffusion to achieve high conductivity. Thereafter, the polysilicon layer 32 deposited on the entire surface is dry-etched without using a mask to leave the gate electrode 33 buried in the trench 27.

In FIG. 18, boron is ion-implanted selectively with a mask of the resist film PR at a dose of 5.0 × 10 ¹⁴ to form a P ⁺ -type body region 34, and then the resist film PR is removed.

In FIG. 19, a new resist film PR is used to mask the intended source region 35 and gate electrode 33 so as to be exposed, and arsenic is ion-implanted at a dose of 5.0 × 10 ¹⁵ to form an N ⁺ type. After forming the source region 35 on the surface of the channel layer 24 adjacent to the trench 27, the resist film PR is removed.

In FIG. 20, BPSG (Boron)
Phosphorus Silicate Glas
s) A layer is deposited by a CVD method to form an interlayer insulating film 36. Thereafter, the interlayer insulating film 36 is left at least on the gate electrode 33 using the resist film as a mask. Thereafter, aluminum is adhered to the entire surface by a sputtering device to form a source electrode 37 that contacts the source region 35 and the body region 34.

Referring to FIG. 20, the structure of a conventional power MOSFET having a trench structure is shown taking an N-channel type as an example.

[0020] on top of the N ⁺ type silicon semiconductor substrate 21 N ^-
A drain region 22 made of a p-type epitaxial layer is provided, and a p-type channel layer 24 is provided on the surface thereof. A trench 27 penetrating through the channel layer 24 and reaching the drain region 22 is provided.
1 and a gate electrode 33 made of polysilicon filled in the trench 27 is provided. An N ⁺ type source region 35 is formed on the surface of the channel layer 24 adjacent to the trench 27, and a P ⁺ type body region 34 is provided on the surface of the channel layer 24 between the source regions 35 of two adjacent cells.
Further, when the gate electrode 33 is applied, a channel region (not shown) is formed from the source region 35 along the trench 27. The gate electrode 33 is covered with an interlayer insulating film 36, and a source electrode 37 that contacts the source region 35 and the body region 34 is provided.

[0021]

SUMMARY OF THE INVENTION Such a conventional MOSF
In the ET, after the trench is formed, dummy oxidation is performed to form a dummy oxide film 28 on the inner wall of the trench 27 and the surface of the channel layer 24.

Since the trench 27 is formed by dry etching, the silicon surface and the inner wall of the trench 27 are rough due to etching damage. The roughness of the silicon surface is removed, and the gate oxide
Dummy oxidation is performed to form 1 stably, and the formed dummy oxide film 28 and CVD oxide film 25 are simultaneously removed by hydrofluoric acid or the like. The thermal oxidation at a high temperature also rounds the opening of the trench 27, and has an effect of avoiding electric field concentration at the opening of the trench 27.

Since this dummy oxidation is thermal oxidation, the silicon surface corresponding to about 44% of the growth amount of the oxide film is shaved to form the dummy oxide film 28. In other words, if the dummy oxide film 28 is subsequently removed by etching, the opening width becomes wider than that at the time of forming the trench, and there is a problem that a desired capacitance value cannot be obtained because the dimensional conversion difference does not result in a finished product as designed. Further, when the trench is widened, a sufficient extension cannot be obtained between the gate electrode 33 in the trench and the adjacent source electrode 37, and there is a problem that a short circuit easily occurs between the gate and the source.

However, the gate oxide film 31 formed in a later step is one of the important factors which determine the characteristics of the MOSFET. To stably form the gate oxide film 31, dummy oxidation is an essential step. It is. In other words, even if the miniaturization of the trench is advanced, there is a problem that a dimensional conversion difference occurs due to the dummy oxidation, and a reduction in capacitance value is not realized as designed.

[0025]

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has been made in view of the above-mentioned circumstances, and includes a step of forming a channel layer of a reverse conductivity type on a surface of a semiconductor substrate of one conductivity type, and a step of penetrating the channel layer and reaching the semiconductor substrate. Forming a trench to be formed;
Annealing the semiconductor substrate in an ultra-high vacuum atmosphere or a hydrogen atmosphere following the formation of the trench; forming a gate insulating film on the inner wall of the trench and the surface of the channel layer; and burying the trench in the trench Forming a gate electrode made of a semiconductor material, and forming a source region of one conductivity type adjacent to the trench on the surface of the channel layer, without performing dummy oxidation. In addition, the surface of the silicon and the inner wall of the trench can be smoothed. Further, by forming a thin dummy oxide film after annealing, the inner wall of the trench can be made smooth without greatly increasing the trench dimension. As a result, the dimensional conversion difference of the trench can be reduced, so that the MOSFET can be finished as designed.
Since a sufficient extension between the gate electrode and the adjacent source electrode can be obtained, a low capacity and highly reliable MOSFE
It is intended to provide a manufacturing method for realizing T.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail with reference to FIGS.

Next, a method of manufacturing a trench type power MOSFET according to the present invention will be described with reference to FIGS.

The trench type power MOSFET of the present invention
The step of forming a channel layer of the opposite conductivity type on the surface of the semiconductor substrate of one conductivity type, the step of forming a trench penetrating the channel layer and reaching the semiconductor substrate; Annealing in a vacuum atmosphere or hydrogen atmosphere, forming a gate insulating film on the inner wall of the trench and the surface of the channel layer, forming a gate electrode made of a semiconductor material embedded in the trench, Forming a source region of one conductivity type adjacent to the trench.

In the first step of the present invention, as shown in FIG.
To form a channel layer of the opposite conductivity type on the surface of a semiconductor substrate of one conductivity type.

A drain region 2 is provided by laminating an N ⁻ type epitaxial layer on an N ⁺ type silicon semiconductor substrate 1. An oxide film 3 is formed on the surface of the epitaxial layer, and the oxide film 3 in a portion of the intended channel layer 4 is removed by etching. Using this oxide film 3 as a mask, boron is implanted into the entire surface at a dose of, for example, 1.0 × 10 ¹³ and then diffused to form a P-type channel layer 4.

The second step of the present invention is to form a trench penetrating the channel layer and reaching the semiconductor substrate as shown in FIGS.

In FIG. 2, NSG is formed on the entire surface by CVD.
(Non-doped Silicate Glass
s) The CVD oxide film 5 is formed to a thickness of 3000 °.

In FIG. 3, the CVD oxide film 5 is partially removed by dry etching using a mask of a resist film to form a trench opening 6 exposing the channel layer 4 with a frontage of about 1.0 μm.

In FIG. 4, the silicon semiconductor substrate is dry-etched from the trench opening 6 with the CVD oxide film 5 as a mask using a CF-based gas and an HBr-based gas to penetrate the channel layer 4 and reach the drain region 2 to about 2.0 μm. Is formed. Thereafter, the CVD oxide film 5 is entirely removed with hydrofluoric acid.

In the third step of the present invention, as shown in FIG.
This is to anneal the semiconductor substrate in an ultra-high vacuum atmosphere or a hydrogen atmosphere following the trench formation.

This step is a characteristic step of the present invention.
FIG. 5A shows a first embodiment of this step. 90
Anneal for about 60 seconds in an ultra-high vacuum atmosphere of 0 to 1100 ° C. and about 80 Torr or in a hydrogen atmosphere. Thereby, silicon atoms are diffused on the surface, and the silicon surface is smoothed at the atomic level.

At the silicon surface (the opening and the inner wall of the trench 7), the connection between silicon atoms is broken by etching, but the annealing under the above conditions causes the silicon surface (the opening and the bottom of the trench 7). The vacant hands of adjacent silicon atoms are connected to each other at the corners, and inside the silicon atoms, the silicon atoms move to fill the gap. In addition, since the broken atoms are recombined with each other, the silicon surface is in a stable state.

That is, due to this surface migration, the silicon surface becomes smooth and the inner wall of the trench 7 has no irregularities at the atomic level. Further, since the curvature at the opening of the trench 7 and the bottom of the trench 7 can be reduced, the breakdown of the gate oxide film due to the electric field concentration can be suppressed, and the reliability of the device is improved.

Further, since the silicon surface becomes high quality silicon without defects, a high quality gate oxide film can be formed in the next step. Therefore, the step of forming a dummy oxide film, which is conventionally required, is not required, and the silicon surface is not shaved by the dummy oxide film, so that the trench 7 can be formed as designed. In addition, if the trench 7 does not expand, the cell density can be improved, which can contribute to a reduction in on-resistance.

FIG. 5B shows a second embodiment of the present invention. In the present invention, after the annealing,
A thin dummy oxide film 8 of about 000 ° may be formed.
For example, even if the above-mentioned effects cannot be sufficiently obtained due to the annealing conditions, the formation of the dummy oxide film 8 makes the silicon surface free from defects and high-quality silicon, and the curvature at the opening and the bottom of the trench 7 is reduced. Also, 1000Å
If it is on the order, the amount of the silicon surface shaved is small, so that the spread of the trench 7 can be suppressed as compared with the conventional case.

In the fourth step of the present invention, as shown in FIG.
Forming a gate insulating film on the inner wall of the trench and on the surface of the channel layer.

The entire surface is thermally oxidized at 1000 ° C. or more, and for example, a gate oxide film 1 having a thickness of about 700 °
1 is formed on the inner wall of the trench 7. By the above-mentioned annealing,
Since the inner wall of the trench 7 has a defect-free and high-quality silicon surface, a high-quality gate oxide film 11 can be formed.
Since the film quality of the gate oxide film 11 is an important factor that determines the characteristics of the MOSFET, if the film quality of the gate oxide film 11 is good, the breakdown voltage between the gate and the source is improved,
The characteristics and reliability of the MOSFET can be improved.

In the fifth step of the present invention, as shown in FIG.
This is to form a gate electrode made of a semiconductor material to be buried in the trench.

Non-doped polysilicon 12 is deposited by CVD at a thickness of, for example, about 5000 ° (half the trench opening dimension) or more, doped with phosphorus at a high concentration, and then diffused to increase the conductivity. Then, the polysilicon 12 is etched back to form the gate electrode 13 buried in the trench 7. The polysilicon 12 may be formed by depositing polysilicon containing impurities.

Here, as described above, since the trench is not expanded due to the dummy oxidation, the gate electrode 13 in the trench is not formed.
And a sufficient extension can be secured between the source electrode 17 adjacent to the gate electrode 13 and formed in a later step.
Short circuit between the gate and the source can be suppressed. In addition, since the cell density can be improved as much as the trench is not expanded, it can also contribute to a reduction in on-resistance.

The sixth step of the present invention is to form a source region of one conductivity type adjacent to the trench on the surface of the channel layer, as shown in FIGS.

FIG. 8 shows a step of forming the body region 14. By masking with the resist film PR except for the channel layer 4 between the trenches 7, boron is more selectively ion-implanted at a dose of 5.0 × 10 ¹⁴ or more to form a P ⁺ -type body region 14. Then, the resist film PR is removed. The body region 14 is formed for stabilizing the potential of the substrate formed by the drain region 2 and the channel layer 4.

FIG. 9 shows a step of forming the source region 15. Arsenic is selectively implanted with a resist film PR except for the trench 7 and the adjacent channel layer 4 at a dose of 5.0 × 10 ¹⁵ , and an N ⁺ -type source region adjacent to the trench 7 is selectively implanted. Then, the resist film PR is removed. Thereby, the side surface of the trench 7 between the drain region 2 and the source region 15 becomes a channel region (not shown) when the gate electrode is applied.

FIG. 10 shows a step of forming the source electrode 17. BPSG (Boron Phosphorus)
(Silicate Glass) is deposited on the entire surface by the CVD method, an interlayer insulating film 16 is formed, and a resist film is used as a mask to partially etch at least the gate electrode 13. Subsequently, aluminum is adhered to the entire surface by a sputtering device to form the body region 14 and the source region 1.
5 is formed.

FIG. 10 shows the structure of a trench type power MOSFET of the present invention, taking an N-channel type as an example.

On the N ⁺ type silicon semiconductor substrate 1, a drain region 2 composed of an N ⁻ type epitaxial layer, a P type channel layer 4 provided on the surface thereof, and a drain region 2 penetrating through the channel layer 4. , A gate oxide film 11 covering the other inner wall of the trench 7, and a gate electrode 13 made of polysilicon buried in the trench 7.
An N ⁺ type source region 15 on the surface of the channel layer 4 adjacent to the trench 7; a P ⁺ type body region 14 provided on the surface of the channel layer 4 between the source regions 15 of two adjacent cells; A channel region (not shown) extending along the trench 7 from the source region 15 of the channel layer 4 when the electrode 13 is applied, and an interlayer insulating film 16 on the trench 7
And a source electrode 17 that contacts source region 15 and body region 14.

[0052]

According to the manufacturing method of the present invention, by annealing in an ultra-high vacuum atmosphere or a hydrogen atmosphere, the silicon surface and the trench inner wall can be made smooth without performing dummy oxidation. First, the dimensional conversion difference of the trench can be reduced.
An object of the present invention is to provide a manufacturing method capable of finishing an SFET and realizing a MOSFET with low capacitance and high reliability. In addition, since the trench is not spread due to the dummy oxidation, the cell density can be improved and the on-resistance can be reduced.

Second, the curvature of the trench opening and the trench bottom can be reduced. Since the breakdown of the gate oxide film due to the electric field concentration can be suppressed, there is an advantage that the reliability of the device is improved.

Third, since the inner wall of the trench has a high quality surface free from defects due to migration, a high quality gate oxide film can be formed. Since the quality of the gate oxide film is an important factor that determines the characteristics of the MOSFET, if the quality of the gate oxide film is good, the characteristics and reliability of the MOSFET can be improved.

Fourth, since the trench does not spread, there is an advantage that the extension between the gate electrode and the adjacent source electrode can be sufficiently obtained, a short circuit between the gate and the source can be suppressed, and the reliability is improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a method for manufacturing an insulated gate semiconductor device of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing an insulated gate semiconductor device of the present invention.

FIG. 3 is a cross-sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

FIG. 4 is a cross-sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

FIG. 5 is a cross-sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

FIG. 6 is a sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

FIG. 7 is a sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

FIG. 8 is a cross-sectional view for explaining the method for manufacturing the insulated gate semiconductor device of the present invention.

FIG. 9 is a cross-sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

FIG. 10 is a cross-sectional view illustrating the insulated gate semiconductor device of the present invention and a method for manufacturing the same.

FIG. 11 is a cross-sectional view illustrating a method of manufacturing a conventional insulated gate semiconductor device.

FIG. 12 is a cross-sectional view illustrating a method for manufacturing a conventional insulated gate semiconductor device.

FIG. 13 is a cross-sectional view illustrating a method for manufacturing a conventional insulated gate semiconductor device.

FIG. 14 is a cross-sectional view illustrating a method for manufacturing a conventional insulated gate semiconductor device.

FIG. 15 is a sectional view illustrating a method for manufacturing a conventional insulated gate semiconductor device.

FIG. 16 is a cross-sectional view illustrating a method of manufacturing a conventional insulated gate semiconductor device.

FIG. 17 is a sectional view illustrating a method for manufacturing a conventional insulated gate semiconductor device.

FIG. 18 is a sectional view illustrating a method for manufacturing a conventional insulated gate semiconductor device.

FIG. 19 is a cross-sectional view illustrating a method for manufacturing a conventional insulated gate semiconductor device.

FIG. 20 is a cross-sectional view illustrating a conventional insulated gate semiconductor device and a method for manufacturing the same.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 658Z

Claims (4)

[Claims] A step of forming a channel layer of the opposite conductivity type on the surface of the semiconductor substrate of one conductivity type; a step of forming a trench penetrating the channel layer and reaching the semiconductor substrate; Annealing the semiconductor substrate in an ultra-high vacuum atmosphere or a hydrogen atmosphere, forming a gate insulating film on the inner wall of the trench and the surface of the channel layer, and a gate electrode made of a semiconductor material embedded in the trench. Forming a source region of one conductivity type adjacent to the trench on the surface of the channel layer. A method of manufacturing an insulated gate semiconductor device, comprising: 2. The method of manufacturing an insulated gate semiconductor device according to claim 1, wherein said annealing diffuses the surface of silicon atoms and smoothes the silicon surface at an atomic level. 3. The method of manufacturing an insulated gate semiconductor device according to claim 1, wherein the annealing reduces the curvature of the trench opening and the trench bottom. 4. The method according to claim 1, wherein a thin dummy oxide film is formed subsequent to the annealing step.