WO2008023776A1

WO2008023776A1 - Semiconductor device and method for manufacturing the same

Info

Publication number: WO2008023776A1
Application number: PCT/JP2007/066397
Authority: WO
Inventors: Kiyoshi Takeuchi
Original assignee: Nec Corporation
Priority date: 2006-08-23
Filing date: 2007-08-23
Publication date: 2008-02-28
Also published as: JPWO2008023776A1; JP5544715B2

Abstract

Semiconductor layers (2a, 2b) for forming a channel are stacked above a substrate (1) by being separated one from the other. The semiconductor layer (2a) has its upper surface in contact with a gate electrode (5a) through a gate insulating film (4), and a lower surface in contact with a gate electrode (5b) through the gate insulating film (4). The semiconductor layer (2b) has its upper surface in contact with the gate electrode (5b) through the gate insulating film (4), and a lower surface in contact with a gate electrode (5c) through the gate insulating film (4). The gate electrodes (5a, 5c) are short-circuited to each other through a gate contact conductor (7a), and are connected to a wiring not shown in the figure. The gate electrode (5b) is connected to a wiring not shown in the figure through other gate contact conductor (7b).

Description

Specification

Semiconductor device and manufacturing method thereof

Technical field

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular, a MIS (Metal Insulator Semiconductor) type in which characteristics can be adjusted by a control terminal and high integration and driving capability can be realized. Field effect transistor and method of manufacturing the same

Background art

[0002] MIS field effect transistors (MISFETs) have simultaneously improved driving ability and integration by miniaturizing dimensions. However, recently, the thickness of the gate insulating thin film has reached the level of 2 nm or less and the gate length is 50 nm or less, and it is becoming difficult to simply reduce the size due to an increase in leakage current. For this reason, it is difficult to further improve the driving force and the degree of integration in the conventional planar MISFET formed on the semiconductor substrate plane.

As a means for solving this problem, a multilayer channel type MISFET in which a plurality of thin film semiconductors forming a channel are arranged in a vertical direction with respect to a substrate and these are connected in parallel to form one transistor is disclosed in Patent Document 1 and It is described in 2. FIG. 9 is a conceptual diagram showing the structure of the conventional MISFET disclosed in Patent Documents 1 and 2, (c) is a plan view thereof, (a) is a cross-sectional view taken along line AA shown in (c), (b) ) Is a cross-sectional view taken along the line B-B shown in (c). In the following description, it is assumed that the MISFET is an N-channel MISFET. In the case of a P-channel MISFET, the polarity of the potential is reversed, and N and P, which are impurity conductivity types, can be exchanged for reading. In the following description, when referring to the vertical direction, the substrate side is the lower side and the opposite side is the upper side.

As shown in FIG. 9, above the substrate 100, a thin semiconductor layer that becomes a channel of the MISFET

102b and 102a are sequentially stacked apart from each other. The upper and lower surfaces and two side surfaces of the semiconductor layers 102a and 102b are surrounded by the gate electrode 105 with the gate insulating film 104 interposed therebetween. That is, as shown in FIG. 9A, gates are formed on the upper and lower surfaces of the semiconductor layer 102b. Gate electrodes 105b and 105c are provided via the insulating film 104, respectively, and gate electrodes 105a and 105b are provided on the upper and lower surfaces of the semiconductor layer 102a via the gate insulating film 104, respectively. ing. Further, as shown in FIG. 9B, the cross sections of the semiconductor layers 102 a and 102 b formed by the BB cross section are surrounded by the gate electrode 105. In other words, the gate electrode 105 is penetrated by the semiconductor layers 102a and 102b through the gate insulating film 104 in the horizontal direction. The other two sides of the semiconductor layers 102a and 102b are one source / drain region 103a, one side of which is common to both semiconductor layers, and the other source / drain of the other side common to both semiconductor layers. Connected to region 103b. Source and drain contact conductors 106a and 106b are provided above the source 'drain regions 103a and 103b, respectively, and a gate contact conductor 106c is provided above the gate electrode 105. The source / drain regions 103a and 103b are doped N-type. Thus, a single MISFET is configured.

[0005] When the potential of the gate electrode 105 is sufficiently higher than the threshold value, a channel is formed in the semiconductor layers 102a and 102b, and the source and drain 103a and 103b are electrically connected. On the other hand, when the potential of the gate electrode 105 is sufficiently lower than the threshold value, a channel is not formed, and the source-drain 103a and 103b are electrically disconnected.

In the above-described conventional MISFET structure, the channel is formed in the thin semiconductor layers 102a and 102b, and the gate electrode 105 sandwiches the semiconductor layers 102a and 102b from both sides, so-called double gate SOI (Silicon On Insulator) structure. When a channel is formed in such a thin semiconductor layer, it is possible to suppress the short channel effect and reduce the distance between the source and drain regions (channel length) by thinning the semiconductor layer. The channel length can be reduced approximately in proportion to the thickness of the semiconductor layer. In addition, when the gate electrode is sandwiched between both sides (double gate), the channel length can be reduced to approximately half compared to when the gate electrode is only on one side (single gate). Therefore, the conventional MIS FET of FIG. 9 is suitable for miniaturization and can meet the demand for high integration.

[0007] In the conventional MISFET structure described above, two semiconductor layers forming a channel are formed in parallel in the vertical direction. For this reason, it is almost twice as large as a normal double-gate MISFET in which only one semiconductor layer is formed without increasing the projected area occupied by the MISFET. Driving ability can be obtained. In addition, the drive capability is almost four times that of a normal single-gate MISFET (a channel is formed only on one side of the semiconductor layer) in which only one semiconductor layer is formed. In this way, the driving ability can be greatly improved without hindering high integration.

[0008] Further, in the conventional SOI structure semiconductor device described in Patent Document 3, a MOS transistor is formed on a silicon substrate via an insulating film, and a gate on a thin film semiconductor layer in this MOS transistor is formed. A buried gate insulating film and a buried gate electrode are sequentially formed on the side opposite to the side on which the oxide film is formed. Then, by controlling the voltage applied to the buried gate electrode, it is possible to control the threshold voltage of the MOS transistor with the force S.

Patent Document 1: Japanese Patent Application Laid-Open No. 2003-324200

Patent Document 2: Japanese Patent Application Laid-Open No. 2004-128508

Patent Document 3: Japanese Patent Application Laid-Open No. 05-167073

Disclosure of the invention

Problems to be solved by the invention

However, the above-described conventional techniques have the following problems.

[0011] In a MISFET using a Balta semiconductor substrate, the threshold voltage of the MISFET can be changed by controlling the potential of the semiconductor substrate. Also, in the MISFET using the SOI substrate, the threshold voltage of the MISFET can be changed by controlling the potential of the semiconductor substrate under the buried insulating film embedded in the SOI substrate. In the above, the substrate functions as the fourth terminal. If the threshold voltage of the MISFET can be controlled by the fourth terminal, the threshold voltage is increased when the circuit is in standby state to reduce leakage current, and the threshold voltage is decreased when the circuit is in operation to drive the MISFET. By increasing the capability, variable threshold operation becomes possible. Or, if the threshold value of the MISFET deviates from the target value due to manufacturing variations, it is possible to adjust the threshold voltage to a desired value by the substrate potential. However, in the semiconductor devices disclosed in Patent Documents 1 and 2, since the semiconductor layer in which the channel is formed is surrounded on all sides by a single gate electrode 105, the influence of the substrate potential does not reach the channel. The threshold voltage can be adjusted. I can't.

[0012] In the prior art disclosed in Patent Document 3, the threshold voltage can be controlled by controlling the voltage applied to the embedded gate electrode, but the semiconductor layer of the MOS transistor is one layer. These are arranged in a plane and are different from a structure in which a plurality of semiconductor layers are formed in parallel in the vertical direction. For this reason, it is difficult to improve the degree of integration and driving force.

[0013] The present invention has been made in view of the above-mentioned problems, and a semiconductor device capable of realizing a high integration degree and a high driving capability and capable of controlling a threshold voltage by an externally applied voltage, and its manufacture It aims to provide a method.

Means for solving the problem

[0014] A semiconductor device according to the present invention is stacked with a substrate, a source region and a drain region formed on the substrate, and a space between the source region and the drain region on the substrate. Between a plurality of channel formation regions, a plurality of gate electrodes formed so as to sandwich each of the channel formation regions, and each of the channel formation regions and at least one of the pair of gate electrodes adjacent thereto Each channel forming region is separated from each other by the displacement of the gate electrode, and the gate electrodes adjacent to each channel forming region are separated from each other. It is characterized by not being short-circuited to each other.

[0015] Preferably, the gate insulating film is formed between each of the channel formation regions and the pair of gate electrodes adjacent thereto.

[0016] Further, the source region, the drain region, and the force can be configured to be continuous semiconductor regions over the plurality of channel formation regions.

[0017] The gate electrode disposed between a pair of channel forming regions adjacent to each other can be a common gate electrode for both of the pair of channel forming regions.

[0018] The odd-numbered gate electrodes from the substrate side are short-circuited to a first conductor connected to a first common wiring, and the even-numbered gate electrodes from the substrate side are short-circuited to a second common electrode. It can be configured to be short-circuited to the second conductor connected to the wiring. [0019] Further, the first conductor that short-circuits the odd-numbered gate electrodes from the substrate side is insulated from the even-numbered gate electrodes by the first insulator sidewalls standing on the substrate. The second conductor for short-circuiting the even-numbered gate electrodes from the substrate side is insulated from the odd-numbered gate electrodes by a second insulator sidewall standing on the substrate. It can be constituted as follows.

[0020] The channel formation region is preferably formed of a single crystal semiconductor layer.

[0021] A method for manufacturing a semiconductor device according to the present invention includes a step of alternately stacking a first semiconductor layer made of a first material and a second semiconductor layer made of a second material on a substrate, Embedding the first and second semiconductor layers in an insulator, selectively removing the first semiconductor layer to form a cavity in the insulator, and embedding a gate electrode in the cavity. Forming a first conductor connected to the odd-numbered gate electrodes from the substrate side, and forming a second conductor connected to the even-numbered gate electrodes from the substrate side; It is characterized by having.

[0022] In this case, the step of alternately laminating the first semiconductor layer and the second semiconductor layer on the substrate is performed on the single-crystal first semiconductor layer formed on the substrate. In addition, the second semiconductor layer and the first semiconductor layer are alternately and sequentially grown by the force S.

The invention's effect

[0023] According to the present invention, in the multilayer channel MISFET, gate electrodes that are not short-circuited with each other are provided above and below each semiconductor layer in which the channel is formed, and the voltage applied to these gate electrodes is set. By independently controlling the semiconductor device, it is possible to provide a semiconductor device having a high degree of integration and a high driving capability, as well as a variable threshold voltage.

Brief Description of Drawings

FIG. 1 is a conceptual diagram showing the structure of a multilayer channel MISFET according to an embodiment of the present invention, in which (c) is a plan view thereof, (a) is an AA sectional view shown in (c), (b) is a BB cross-sectional view shown in (c).

FIG. 2 is a conceptual diagram showing a case where there are three semiconductor layers in this embodiment, (a) is a cross-sectional view corresponding to FIG. 1 (a), and (b) is equivalent to FIG. 1 (b). It is sectional drawing. FIG. 3 is a conceptual diagram showing the manufacturing method of the present embodiment.

FIG. 4 is a conceptual diagram showing the manufacturing method of the present embodiment following FIG. 3.

FIG. 5 is a conceptual diagram showing the manufacturing method of the present embodiment following FIG. 4.

FIG. 6 is a conceptual diagram showing the manufacturing method of this embodiment following FIG. 5.

FIG. 7 is a conceptual diagram showing the manufacturing method of the present embodiment following FIG. 6.

FIG. 8 is a conceptual diagram showing a method for forming a gate electrode contact conductor in the present embodiment.

FIG. 9 is a conceptual diagram showing the structure of a conventional MISFET disclosed in Patent Documents 1 and 2, (c) is a plan view thereof, (a) is a cross-sectional view taken along line AA in (c), (b) ) Is a cross-sectional view taken along the line B-B shown in (c).

Explanation of symbols

[0025] 1; substrate

2a, 2b, 2c: Semiconductor layer

3a, 3b: source and drain regions

4; Gate insulation film

5a, 5b, 5c, 5d; gate electrode

7a, 7b; conductor

11, 12; Semiconductor layer

13, 14; insulator

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings.

FIG. 1 is a conceptual diagram showing the structure of a multilayer channel MIS FET according to an embodiment of the present invention, where (c) is a plan view, (a) is an AA cross-sectional view shown in (c), (b) ) Is a cross-sectional view along the line B-B shown in (c).

As shown in FIG. 1 (a), in the present embodiment, a gate electrode 5c is formed on a substrate 1, and a semiconductor layer 2b is formed on the gate electrode 5c via a gate insulating film 4. Is formed. A gate electrode 5b is formed on the semiconductor layer 2b via a gate insulating film 4, and a semiconductor layer 2b is formed on the gate electrode 5b via a gate insulating film 4. Furthermore, semiconductor A gate electrode 5a is formed on the body layer 2b with a gate insulating film 4 interposed therebetween. The semiconductor layers 2a and 2b are thin semiconductor layers in which MISFET channels are formed.In this way, the semiconductor layers 2b and 2a are sequentially formed above the substrate 1 while being spaced apart from each other. They are stacked.

As shown in FIG. 1 (b), odd-numbered gate electrodes 5a and 5c from the substrate side are short-circuited to each other through a conductor 7a and connected to a wiring (not shown). The even-numbered gate electrode 5b from the substrate side is connected to a wiring (not shown) via another conductor 7b. In other words, the odd-numbered gate electrodes from the substrate side are short-circuited to form the first gate electrode, and the even-numbered gate electrodes from the substrate side are short-circuited to form the second gate electrode. The odd-numbered gate electrode and the even-numbered gate electrode are not short-circuited with each other so that the first gate electrode and the second gate electrode are independent gate electrodes. However, in this embodiment, since there is only one even-numbered gate electrode, a plurality of gate electrodes are not short-circuited to each other. The conductor 7a is insulated from the even-numbered gate electrode 5b by an insulator side wall (not shown). Similarly, the conductor 7b is insulated from the odd-numbered gate electrode 5a by an insulator side wall (not shown). The insulator side wall will be described in detail in the manufacturing method of the present embodiment described later.

[0029] As shown in FIG. 1 (a), two side surfaces of semiconductor layers 2a and 2b facing each other (two side surfaces provided facing the left and right sides in the illustrated example) are arranged on both semiconductor layers. On the other hand, one side of the common source'drain region 3a is connected to the other side of the source'drain region 3b common to both semiconductor layers. The source / drain regions 3a and 3b are doped N-type, respectively. Further, as shown in FIG. 1B, source and drain contact conductors 6a and 6b are provided on the source and drain regions 3a and 3b, respectively. As described above, a single MISFET having the fourth terminal is configured.

[0030] It is preferable that at least the surface of the substrate 1 is made of an insulating material. However, if the source / drain regions 3a and 3b are not short-circuited with each other! / So that the surface of the substrate 1 has a polarity opposite to that of the source / drain regions (P-type in the N-channel MISFET), the substrate 1 The surface or the whole may be a semiconductor. The source / drain region is preferably made entirely of semiconductor. 1S At least a part of the source / drain region may be made of metal. Especially in contact with the channel region A metal source / drain type transistor may be formed by using a metal for the region to be formed.

Next, the operation of this embodiment will be described. A channel is formed in the semiconductor layers 2a and 2b when the potentials of the first and second gate electrodes are sufficiently high, and the source / drain regions 3a and 3b are electrically connected. When the potentials of the first and second gate electrodes are sufficiently low, no channel is formed, and the source / drain regions 3a and 3b are electrically disconnected. In this way, the on-current of the MISFET can be obtained as the sum of the current flowing through each channel. The first gate electrode can be a main gate electrode, and the second gate electrode can be an auxiliary gate electrode for threshold voltage control, that is, a fourth electrode. Increasing the auxiliary gate potential decreases the threshold for the main gate, and decreasing the auxiliary gate potential increases the threshold for the main gate. The roles of the first gate and the second gate may be interchanged. In addition, the MISFET in FIG. 1 is considered to be a parallel connection of a first MISFET having a first gate electrode as a gate electrode and a second MISFET having a second gate electrode as a gate electrode. Can also be used.

According to the present embodiment, a plurality of semiconductor layers each having a channel formed thereon are stacked so as to be separated from each other, and the first gate electrode and the first gate electrode independent from each other above and below each semiconductor layer are stacked. By arranging the second gate electrode, it is possible to realize a semiconductor device that can variably control the threshold voltage in addition to high integration and high driving force.

[0033] Further, when N double gate MISFETs (having gate electrodes above and below each semiconductor layer) are stacked, the number of gate electrodes becomes 2N. However, in this embodiment, one layer of the gate electrode is shared by the upper and lower semiconductor layers. For this reason, when N semiconductor layers are used, the number of gate electrode layers required is N + 1, which reduces the manufacturing process and reduces the total thickness of the stacked layers.

In the present embodiment, the gate insulating film 4 is provided between the semiconductor layer 2a and the gate electrodes 5a and 5b disposed above and below the semiconductor layer 2a. Similarly, the semiconductor layer 2b A gate insulating film 4 is also provided between the gate electrodes 5b and 5c disposed above and below the gate electrodes. However, the gate insulating film 4 does not necessarily have to be interposed between the gate electrode corresponding to the back gate (substrate potential side of the planar FET) and the semiconductor layer. That is, a gate insulating film is not necessarily interposed between the gate electrode corresponding to the substrate side and the semiconductor layer. A configuration in which an insulating film is not provided between the second gate electrode as the auxiliary gate electrode and the semiconductor layer is also possible.

In this embodiment, the odd-numbered gate electrodes from the substrate side are configured as first gate electrodes that are short-circuited with each other, and the even-numbered gate electrodes from the substrate side are short-circuited with each other. However, it is also possible to connect the gate electrodes to mutually independent wirings and control the applied voltage independently.

[0036] FIG. 1 shows the force S when there are two semiconductor layers, and FIG. 2 shows the case where there are three semiconductor layers. FIG. 2 is a conceptual diagram showing a case where there are three semiconductor layers in this embodiment. (A) is a cross-sectional view corresponding to FIG. 1 (a), and (b) is equivalent to FIG. 1 (b). It is sectional drawing. As shown in FIGS. 2 (a) and 2 (b), the odd-numbered gate electrodes 5b and 5d from the substrate side are short-circuited to each other via the conductor 7a to form the first gate electrode in the same manner. The even-numbered gate electrodes 5a and 5c are short-circuited to each other via the conductor 7b to form a second gate electrode, and the odd-numbered gate electrode and the even-numbered gate electrode are not short-circuited to each other. The one gate electrode and the second gate electrode can be independent gate electrodes. In FIG. 2, the same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. The same can be achieved when there are four or more semiconductor layers. With such a configuration, the degree of integration and driving force can be further improved.

Next, the manufacturing method of the present embodiment will be described with reference to FIGS. 3 to 7. Fig. 3 to Fig. 7 are conceptual diagrams showing the manufacturing method of this embodiment in the order of steps. (C) is a plan view thereof, (a) is a cross-sectional view taken along line AA in (c), and (b). FIG. 4B is a sectional view taken along line BB in (c). In order to form a structure as shown in FIGS. 3 and 4, first, a gate electrode is formed on a substrate, then a gate insulating film is formed thereon, and then a semiconductor layer is formed thereon. Thus, it is conceivable to form the constituent layers of the MISFET sequentially from the bottom. However, with such a method, the semiconductor layers 2a and 2b shown in FIG. 1 cannot be formed into a single crystal. This is because the base layer on which the semiconductor layer is deposited is a gate insulating film, but the gate insulating film (silicon oxide film or the like) is usually amorphous, and when a semiconductor is deposited thereon, the semiconductor is amorphous or polycrystalline. It becomes. Amorphous or polycrystalline can be used for the channel part of the MISFET, but the driving capability and uniformity of characteristics are significantly degraded compared to single crystals. [0038] Therefore, since the semiconductor layer forming the channel is a single crystal, the MISFET of this embodiment can be manufactured as follows. First, the structure of FIG. 3 is formed. That is, as shown in FIG. 3, a semiconductor layer 11 made of a first material (for example, SiGe (silicon germanium)) and a semiconductor layer 12 made of a second material (for example, Si (silicon)) are formed on a substrate 1. And are alternately deposited. The semiconductor layers 11 and 12 are both single crystals. The semiconductor layer 12 is retracted laterally from the semiconductor layer 1 1. The semiconductor layer 12 becomes the semiconductor layers 2a and 2b in which channels are formed later. The semiconductor layer 11 functions as a saddle shape.

In order to form the structure of FIG. 3, first, a single-crystal semiconductor layer 11 is formed on the entire surface of the substrate 1, and a silicon_on_insulator (≥iOI) tomb, or a silicon germanium on insulator (SGOI) substrate, etc. Departs from. Manufacturing methods of SOI substrates or SGOI substrates are well known. For example, when starting from an SGOI substrate, the SiGe layer originally on the SGOI substrate becomes the lowermost semiconductor layer 11. On this, the semiconductor layer 12 and the semiconductor layer 11 are sequentially epitaxially grown. In the example of FIG. 3, the semiconductor layer 12 and the semiconductor layer 11 are deposited twice each. In the epitaxial growth, since the periodicity of the underlying semiconductor crystal is inherited by the upper layer, the semiconductor layer 12 and the semiconductor layer 11 can all be single crystals. Next, the deposited multilayer semiconductor is processed into a desired planar shape by using lithography and etching. In Fig. 3, it is processed into a horizontally long rectangle. Next, the semiconductor layer 12 is selectively retracted laterally. Further, an insulator 13 is deposited so as to bury all of the semiconductor layers 11 and 12, and the structure shown in FIG. 3 is obtained. In FIG. 3C, the uppermost insulator 13 is seen through to show the state of the lower layer.

Next, the semiconductor layers 11 and 12 and the insulator 13 are shaped so as to leave the range shown in FIG. 4 (c). Next, only the semiconductor layer 11 is selectively retracted in the lateral direction to obtain the structure of FIG. In FIG. 4C, the uppermost insulator 13 is seen through to show the state of the lower layer.

Next, the semiconductor layers 11 and 12 are again embedded in the insulator 14. Insulator 14 includes the remaining portion of insulator 13. Next, holes are formed in the insulator 14 for forming the source / drain regions 3a and 3b, and a semiconductor is buried in the holes to form the source / drain regions 3a and 3b (FIG. 5). The source and drain regions 3a and 3b can be formed by epitaxial growth using the semiconductor layer 12 as a seed. In this case, at least a part of the source and drain regions 3a and 3b is used. Can be a single crystal. The source and drain regions 3a and 3b are appropriately doped with impurities by ion implantation or impurity mixing during deposition, and the source and drain regions 3a and 3b are made to be N-type. As a result, the structure of FIG. 5 is obtained. In FIG. 5 (c), the uppermost insulator 14 is seen through to show the state of the lower layer.

Next, the semiconductor layers 11 and 12 and the source / drain regions 3a and 3b are buried again in the insulator 15 (FIG. 6). Next, holes are formed in the insulator 15 from above so that a part of the semiconductor layer 11 is exposed in all the layers inside the holes. For example, a hole reaching the substrate 1 is made in the circular two-dot chain line portion in FIG. Next, the semiconductor layer 11 is completely removed from the hole by isotropic etching. Next, the gate insulating film 4 is formed on the surface of the semiconductor layer 12 in the cavity after the semiconductor layer 11 is removed. The gate insulating film 4 is formed by oxidizing the semiconductor layer 12 or chemical vapor deposition of an insulator. Next, the inside of the cavity is filled with the gate electrode material 5. Next, the gate electrode material 5 formed in the hole provided in the insulator 15 is removed, and the hole is backfilled to obtain the structure of FIG.

Next, a conductor 7a for connecting the odd-numbered gate electrode layer from the substrate side to the wiring and a conductor 7b for connecting the even-numbered gate electrode layer from the substrate side to the wiring are formed. First, a hole reaching the lowermost gate electrode layer to be connected is provided at a position where the conductor 7a of the insulator 15 is to be formed. Next, an insulator covering the inside of the hole is deposited and anisotropically etched to provide an insulator side wall 8a at the bottom of the hole. Next, a conductor is embedded in the hole to form a conductor 7a. Thus, the conductor 7a is connected only to the odd-numbered gate electrode, and is insulated from the even-numbered gate electrode by the insulator side wall 8a. Next, a hole reaching the lowermost gate electrode layer to be connected is provided at a position where the conductor 7b of the insulator 15 is to be formed. Next, an insulator covering the inside of the hole is deposited and anisotropically etched to provide an insulator side wall 8b at the bottom of the hole. Next, a conductor is embedded in the hole to form a conductor 7b. Thus, the conductor 7b is connected only to the even-numbered gate electrode, and is insulated from the odd-numbered gate electrode by the insulator side wall 8b. Further, the source and drain contact conductors 6a and 6b that connect the source and drain regions 3a and 3b to the wiring are also formed by making holes in the insulator 15 and embedding the conductors therein. Thus, the structure of FIG. 7 is obtained. The structure in FIG. 7 is equivalent to the structure in FIG. 1. The semiconductor layer 12 corresponds to the semiconductor layers 2a and 2b, and the gate electrode material 5 comprises the gate electrodes 5a, 5b, and 5c. To do.

Note that when SiGe is used as the semiconductor layer 11 and Si is used as the semiconductor layer 12, the semiconductor layer

In the process of selectively retracting 12 laterally to obtain the structure of FIG. 3, SF, H, and

6 2

Dry etching using a mixed gas of CF can be used. In addition, the semiconductor layer 11 is

Four

In the step of selectively retracting in the lateral direction to obtain the structure of FIG. 4, wet etching using a mixed aqueous solution of peracetic acid and hydrogen fluoride can be used. Further, wet etching using a mixed aqueous solution of peracetic acid and hydrogen fluoride can also be used in the step of selectively removing the semiconductor layer 11 to form a cavity in which the gate electrode is embedded.

[0045] According to the manufacturing method of the present embodiment, a multilayer channel MISFET can be manufactured such that a semiconductor layer in which a channel is formed is a single crystal.

The manufacturing method in the case where there are two semiconductor layers has been described above, but the same manufacturing method can be applied even in the case where there are three or more semiconductor layers. However, a method of forming a conductor that selectively connects only odd-numbered or even-numbered gate electrode layers may be performed as described below. As shown in Fig. 8, first, contact holes are made up to the lowest gate electrode layer to be connected. Next, the insulator sidewall 8 is formed on the side surface from the lowermost layer to the second layer upward. Next, the conductor 7 is filled in the contact hole. However, at this time, the conductor 7 is filled up to the depth that is not connected to the fourth layer above the force that is connected to the third layer upward from the bottom layer! As a result, the structure shown in FIG. Thereafter, when a step of further forming a sidewall insulator and filling the conductor is performed, the structure of FIG. 8B can be obtained. If the formation of the insulator side wall and the filling of the conductor are repeated as appropriate, it is possible to form a conductor that selectively connects only the odd-numbered or even-numbered gate electrode layers with respect to the arbitrary number of layers.

[0047] This application (until 23 August 2006, filed with Japanese Patent Application No. 2006-226821, filed on August 23, 2006), and the disclosure of which is incorporated herein in its entirety.

Industrial applicability

The semiconductor device according to the present invention can be suitably mounted on various integrated circuits.

Claims

The scope of the claims

[1] A substrate, a source region and a drain region formed on the substrate, a plurality of channel forming regions stacked on the substrate so as to be spaced apart from each other, and each of the channel forming regions A plurality of gate electrodes formed so as to sandwich the channel formation region, and a gate insulating film formed between each channel formation region and at least one of the pair of gate electrodes adjacent thereto. The channel forming regions are separated from each other by the displacement or misalignment of the gate electrode, and the gate electrodes adjacent to the channel forming regions are not short-circuited to each other. Semiconductor device.

[2] The semiconductor device according to [1], wherein the gate insulating film is formed between each of the channel forming regions and a pair of the gate electrodes adjacent thereto.

[3] The semiconductor device according to [1], wherein each of the source region, the drain region, and the force is a semiconductor region continuous over the plurality of channel formation regions.

[4] The gate electrode disposed between the pair of channel forming regions adjacent to each other is a common gate electrode for both of the pair of channel forming regions. Item 2. The semiconductor device according to Item 1.

[5] The odd-numbered gate electrode from the substrate side is short-circuited to the first conductor connected to the first common wiring, and the even-numbered gate electrode from the substrate side is connected to the second common wiring. 2. The semiconductor device according to claim 1, wherein the semiconductor device is short-circuited to the connected second conductor.

[6] The first conductor that short-circuits the odd-numbered gate electrodes from the substrate side is isolated from the even-numbered gate electrodes by a first insulator side wall erected on the substrate, The second conductor for short-circuiting the even-numbered gate electrodes from the substrate side is insulated from the odd-numbered gate electrode force by a second insulator sidewall standing on the substrate. 6. The semiconductor device according to claim 5, wherein:

7. The semiconductor device according to claim 1, wherein the channel formation region is made of a single crystal semiconductor layer.

[8] A step of alternately laminating a first semiconductor layer made of a first material and a second semiconductor layer made of a second material on a substrate, and the first and second semiconductor layers in an insulator Embedding process And selectively removing the first semiconductor layer to form a cavity in the insulator;

A step of embedding a gate electrode in the cavity, a step of forming a first conductor connected to the odd-numbered gate electrode from the substrate side, and a connection to the even-numbered gate electrode from the substrate side. Forming a second conductor to be manufactured. A method for manufacturing a semiconductor device, comprising:

The step of alternately stacking the first semiconductor layer and the second semiconductor layer on the substrate includes the step of stacking the second semiconductor on the single-crystal first semiconductor layer formed on the substrate. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the layers and the first semiconductor layer are alternately and epitaxially grown sequentially.