JP5098178B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and is particularly suitable when applied to a method of mounting an SOI structure and a bulk structure on the same substrate.

  Field effect transistors formed on an SOI substrate are attracting attention because of their ease of element isolation, latch-up freeness, and low source / drain junction capacitance. In particular, since a fully depleted SOI transistor can operate at low power consumption and at high speed and can be easily driven at a low voltage, research for operating the SOI transistor in a fully depleted mode has been actively conducted. Here, as the SOI substrate, for example, a SIMOX (Separation by Implanted Oxygen) substrate or a bonded substrate is used.

On the other hand, a field effect transistor having a large current driving capability and a high breakdown voltage is difficult to form on an SOI substrate in which the thickness of the silicon layer is limited, and it is desirable to form it on a bulk substrate.
Further, for example, in Patent Document 1, in order to allow the SOI transistor and the high breakdown voltage transistor to be mixedly mounted on the same substrate, a part of the silicon layer and the BOX layer in the SOI substrate are selectively removed. A method of providing a bulk region on an SOI substrate by forming an epitaxial silicon layer in the region is disclosed.
Japanese Patent Laid-Open No. 2004-47844

  However, in order to manufacture a SIMOX substrate, it is necessary to implant ions of oxygen at a high concentration into a silicon wafer. In order to manufacture a bonded substrate, it is necessary to polish the surface of the silicon wafer after bonding two silicon wafers. For this reason, the method of providing a non-SOI region on an SOI substrate has a problem that the cost is increased as compared with a field effect transistor formed in a bulk semiconductor.

In the method disclosed in Patent Document 1, the silicon layer is directly polished by CMP (Chemical Mechanical Polishing) in order to ensure the flatness of the SOI substrate provided with the bulk region. There was a problem that the damage remained.
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device and a semiconductor device manufacturing method capable of forming an SOI structure and a bulk structure on the same substrate while ensuring flatness between the SOI structure and the bulk structure. That is.

According to the method for manufacturing a semiconductor device of one embodiment of the present invention, the first step of forming the first semiconductor layer on the first region and the second region of the semiconductor substrate , and the second semiconductor layer and a second step of forming on the first on the first semiconductor layer over the region and the first semiconductor layer over the second region, the first pre-SL on the first region 1 so that the semiconductor layer and surrounding said second semiconductor layer on said first region, said third step of forming a support to reach the semiconductor substrate, the second semiconductor layer surrounded by said support Etching a part of the support in contact therewith to form an opening exposing a part of the first semiconductor layer; and a region surrounded by the support through the opening . A fifth step of selectively etching one semiconductor layer to form a cavity; and A sixth step of forming an insulating layer on the mouth, characterized in that it and a seventh step of forming a transistor on the second semiconductor layer surrounded by said support.
According to the method for manufacturing a semiconductor device of one embodiment of the present invention, the third step includes an eighth step of forming an antioxidant film over the second semiconductor layer over the first region. And a ninth step of forming the support by thermally oxidizing the first semiconductor layer and the second semiconductor layer using the antioxidant film as a mask .

As a result, the first semiconductor layer can be removed while leaving the second semiconductor layer, a cavity can be formed under the second semiconductor layer, and a support that supports the second semiconductor layer By providing the second semiconductor layer, the second semiconductor layer can be supported on the semiconductor substrate by the support even when the cavity is formed under the second semiconductor layer. Further, by providing an opening exposing a portion of the first semiconductor layer under the first region, even when the second semiconductor layer stacked on the first semiconductor layer, an etching gas or an etching solution first it becomes possible to contact the first semiconductor layer under the first region, along with it becomes possible to remove the first semiconductor layer under the first region while leaving the second semiconductor layer, the second region The first semiconductor layer can be left as it is under the second semiconductor layer. Therefore, while reducing the occurrence of defects of the second semiconductor layer, a second semiconductor layer of the first region can be disposed on the insulating layer, without damaging the quality of the second semiconductor layer, the first Insulation between the second semiconductor layer and the semiconductor substrate in the region can be achieved, and flatness between the SOI structure and the bulk structure can be ensured without polishing the surface of the second semiconductor layer. it can. As a result, even when the SOI structure and the bulk structure are formed on the same substrate, it is possible to realize miniaturization of the SOI structure and the bulk structure while suppressing the damage of the second semiconductor layer, and the cost. Increase can be suppressed.
As a result, when the second semiconductor layer in the SOI formation region is removed, the second semiconductor layer in the bulk region can be protected with the selective oxide film, and a cavity is formed under the second semiconductor layer. Even in this case, the second semiconductor layer can be supported on the semiconductor substrate by the selective oxide film. Therefore, the second semiconductor layer in the SOI formation region can be removed while leaving the second semiconductor layer in the bulk region as it is, and the buried insulating layer can be buried in the SOI formation region. The flatness between the SOI structure and the bulk structure can be ensured while suppressing the damage.

Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.
1A to 8A are plan views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 1B to 8B are FIGS. Sectional views cut along lines A1-A1 ′ to A8-A8 ′ in FIG. 8A, respectively, and FIGS. 1C to 8C are B1- in FIGS. 1A to 8A. It is sectional drawing cut | disconnected by the B1'-B8-B8 'line | wire, respectively.

  In FIG. 1, a semiconductor substrate 1 is provided with a bulk region R1 and an SOI formation region R2. Then, the first semiconductor layer 2 and the second semiconductor layer 3 are sequentially formed on the semiconductor substrate 1 by epitaxial growth. The first semiconductor layer 2 can be made of a material having an etching rate larger than that of the semiconductor substrate 1 and the second semiconductor layer 3, and the material of the semiconductor substrate 1, the first semiconductor layer 2 and the second semiconductor layer 3 can be used. For example, a combination selected from Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, and the like can be used. In particular, when the semiconductor substrate 1 is Si, it is preferable to use SiGe as the first semiconductor layer 2 and Si as the second semiconductor layer 3.

  Accordingly, it is possible to secure a selection ratio between the first semiconductor layer 2 and the second semiconductor layer 3 while enabling lattice matching between the first semiconductor layer 2 and the second semiconductor layer 3. it can. As the first semiconductor layer 2, a polycrystalline semiconductor layer, an amorphous semiconductor layer, or a porous semiconductor layer may be used in addition to the single crystal semiconductor layer. Instead of the first semiconductor layer 2, a metal oxide film such as γ-aluminum oxide capable of forming a single crystal semiconductor layer by epitaxial growth may be used. Moreover, the film thickness of the 1st semiconductor layer 2 and the 2nd semiconductor layer 3 can be about 1-200 nm, for example.

  Next, as shown in FIG. 2, a base oxide film 4 is formed on the surface of the second semiconductor layer 3 by thermal oxidation of the second semiconductor layer 3. Then, an antioxidant film 5 is formed on the entire surface of the base oxide film 4 by a method such as CVD. For example, a silicon nitride film can be used as the antioxidant film 5. Then, by patterning the antioxidant film 5 using a photolithography technique and an etching technique, the bulk region R1 and the SOI formation region R2 are covered with the antioxidant film 5 and the periphery of the bulk region R1 and the SOI formation region R2 is covered. The antioxidant film 5 is removed.

  Next, as shown in FIG. 3, the first semiconductor layer 2 and the second semiconductor layer using the antioxidant film 5 as a mask until they penetrate the first semiconductor layer 2 and the second semiconductor layer 3 and reach the semiconductor substrate 1. 3, the bulk region R1 and the SOI formation region R2 are separated from each other, and the selective oxide film 6 that supports the second semiconductor layer 3 on the semiconductor substrate 1 is formed in the bulk region R1 and the SOI formation region R2. Form around.

  Next, as shown in FIG. 4, by using a photolithography technique, the second semiconductor layer 3 in the SOI formation region R2 is exposed and a part of the selective oxide film 6 in contact with the second semiconductor layer 3 is exposed. The resist pattern R provided with the opening Ra to be formed is formed. Then, using the resist pattern R as a mask, the base oxide film 4 and a part of the selective oxide film 6 in contact with the second semiconductor layer 3 are etched to form a groove 7 exposing a part of the side wall of the first semiconductor layer 2. To do. Here, the arrangement position of the groove 7 can correspond to a part of the element isolation region of the second semiconductor layer 3.

  When a part of the side wall of the first semiconductor layer 2 is exposed, the etching may be stopped at the surface of the first semiconductor layer 2, or the first semiconductor layer 2 is over-etched and the first semiconductor layer 2 is overetched. You may make it form a recessed part in this. Alternatively, the surface of the semiconductor substrate 1 may be exposed through the first semiconductor layer 2 in the groove 7. Here, it is possible to prevent the surface of the semiconductor substrate 1 in the groove 7 from being exposed by stopping the etching of the first semiconductor layer 2 halfway. For this reason, when the first semiconductor layer 2 is removed by etching, the time during which the semiconductor substrate 1 in the groove 7 is exposed to the etching solution or the etching gas can be reduced, and the over-etching of the semiconductor substrate 1 in the groove 7 can be reduced. Can be suppressed.

Next, as shown in FIG. 5, the first semiconductor layer 2 is removed by etching by bringing an etching gas or an etchant into contact with the first semiconductor layer 2 through the groove 7, and the semiconductor substrate 1 and the second semiconductor layer are removed. The cavity 8 is formed between the two.
Here, a selective oxide film 6 configured to penetrate the first semiconductor layer 2 and the second semiconductor layer 3 to reach the semiconductor substrate 1 is provided around the second semiconductor layer 3, whereby the first semiconductor layer 2. Even when the second semiconductor layer 3 is removed, the second semiconductor layer 3 can be supported on the semiconductor substrate 1, and the second semiconductor layer is provided by providing the groove 7 exposing the end of the first semiconductor layer 2. 3, the etching gas or the etchant can be brought into contact with the first semiconductor layer 2 below. For this reason, it is possible to form the cavity 8 between the second semiconductor layer 3 and the semiconductor substrate 1 without impairing the quality of the second semiconductor layer 3.

  When the semiconductor substrate 1 and the second semiconductor layer 3 are Si and the first semiconductor layer 2 is SiGe, hydrofluoric acid (a mixed solution of hydrofluoric acid, nitric acid, and water) is used as the etchant for the first semiconductor layer 2. preferable. Thereby, it is possible to remove the first semiconductor layer 2 while suppressing overetching of the semiconductor substrate 1 and the second semiconductor layer 3. Further, as an etchant for the first semiconductor layer 2, hydrofluoric acid / hydrogen peroxide, ammonia / hydrogen peroxide, or hydrofluoric acid / hydrogen peroxide may be used.

  Further, before the first semiconductor layer 2 is removed by etching, the first semiconductor layer 2 may be made porous by a method such as anodic oxidation, or by ion implantation in the first semiconductor layer 2, The first semiconductor layer 2 may be made amorphous, or a P-type semiconductor substrate may be used as the semiconductor substrate 1. Thereby, the etching rate of the first semiconductor layer 2 can be increased, and the etching area of the first semiconductor layer 2 can be increased.

Next, as shown in FIG. 6, by performing thermal oxidation of the semiconductor substrate 1 and the second semiconductor layer 3, a buried insulating layer 9 is formed in the cavity 8 between the semiconductor substrate 1 and the second semiconductor layer 3. Form. At that time, the side walls and the surface of the second semiconductor layer 3 are also oxidized, and an oxide film is formed on the side walls and the surface of the second semiconductor layer 4.
In the case where the buried insulating layer 9 is formed by thermal oxidation of the semiconductor substrate 1 and the second semiconductor layer 3, it is preferable to use low-temperature wet oxidation that is reaction-controlled in order to improve the embeddability. Further, the buried insulating layer 9 may be formed so as to fill the entire cavity 8 or may be formed so that a part of the cavity 8 remains.

  In the method of FIG. 6, the buried insulating layer 9 is formed in the cavity 8 between the semiconductor substrate 1 and the second semiconductor layer 3 by performing thermal oxidation of the semiconductor substrate 1 and the second semiconductor layer 3. As described above, by forming an insulating film in the cavity 8 between the semiconductor substrate 1 and the second semiconductor layer 3 by the CVD method, the cavity between the semiconductor substrate 1 and the second semiconductor layer 3 is formed. 8 may be embedded in the embedded insulating layer 9.

  Thereby, it is possible to fill the cavity 8 between the semiconductor substrate 1 and the second semiconductor layer 3 with a material other than the oxide film while preventing the second semiconductor layer 3 from being reduced. Therefore, it is possible to increase the thickness of the buried insulating layer 9 disposed on the back surface side of the second semiconductor layer 3, and to reduce the dielectric constant, so that the back surface side of the second semiconductor layer 3 can be reduced. Parasitic capacitance can be reduced.

  As the buried insulating layer 9, for example, an FSG (fluorinated silicate glass) film or the like may be used in addition to the silicon oxide film. As the material of the buried insulating layer 9, in addition to a SOG (Spin On Glass) film, a PSG film, a BPSG film, a PAE (poly arylene ether) -based film, an HSQ (hydrogen silsesquioxane) -based film, an MSQ (methyl silsesquioxane) film. Alternatively, an organic lowk film such as a PCB film, a CF film, a SiOC film, or a SiOF film, or a porous film thereof may be used.

  Further, by making the arrangement position of the groove 7 correspond to the element isolation region of the second semiconductor layer 3, it is possible to perform the element isolation of the second semiconductor layer 3 and to selectively oxidize around the second semiconductor layer 3. By providing the film 6, it is not necessary to secure a support for supporting the second semiconductor layer 3 on the semiconductor substrate 1 in the active region. Therefore, an SOI transistor can be formed while suppressing an increase in the number of processes, and an increase in chip size can be suppressed, so that the cost of the SOI transistor can be reduced.

  Next, as shown in FIG. 7, the buried insulating layer 9 and the selective oxide film 6 are thinned by a method such as CMP or etchback, thereby planarizing the bulk region R <b> 1 and the SOI formation region R <b> 2. The surface of the semiconductor layer 3 is exposed. In the case where the bulk region R1 and the SOI formation region R2 are planarized, an oxide film may be deposited on the bulk region R1 and the SOI formation region R2, and then CMP may be performed. A nitride film may be formed as a stopper film by CMP.

  Next, as shown in FIG. 8, the gate insulating film 11 a is formed on the surface of the second semiconductor layer 3 by performing thermal oxidation of the surface of the second semiconductor layer 3 in the bulk region R <b> 1. Then, a polycrystalline silicon layer is formed on the second semiconductor layer 3 on which the gate insulating film 11a is formed by a method such as CVD. Then, the gate electrode 12a is formed on the second semiconductor layer 3 by patterning the polycrystalline silicon layer using a photolithography technique and an etching technique.

  Next, by using the gate electrode 12a as a mask, impurities such as As, P, and B are ion-implanted into the second semiconductor layer 3, thereby forming LDDs composed of low-concentration impurity introduction layers disposed on both sides of the gate electrode 12a. A layer is formed on the second semiconductor layer 3. Then, an insulating layer is formed on the second semiconductor layer 3 on which the LDD layer is formed by a method such as CVD, and the insulating layer is etched back using anisotropic etching such as RIE, whereby the gate electrode 12a. Sidewalls 13a are formed on the side walls. Then, by using the gate electrode 12a and the sidewall 13a as a mask, impurities such as As, P, and B are ion-implanted into the second semiconductor layer 3, the first semiconductor layer 2, and the semiconductor substrate 1, thereby the side of the sidewall 13a. A source / drain layer 14 a made of a high concentration impurity introduction layer disposed on each side is formed on the second semiconductor layer 3, the first semiconductor layer 2, and the semiconductor substrate 1.

  In addition, in the SOI formation region R2, the surface of the second semiconductor layer 3 is thermally oxidized to form the gate insulating film 11b on the surface of the second semiconductor layer 3. Then, a polycrystalline silicon layer is formed on the second semiconductor layer 3 on which the gate insulating film 11b is formed by a method such as CVD. Then, the gate electrode 12b is formed on the second semiconductor layer 3 by patterning the polycrystalline silicon layer using a photolithography technique and an etching technique.

  Next, by using the gate electrode 12b as a mask, impurities such as As, P, and B are ion-implanted into the second semiconductor layer 3 to thereby form LDDs composed of low-concentration impurity introduction layers disposed on both sides of the gate electrode 12b. A layer is formed on the second semiconductor layer 3. Then, an insulating layer is formed on the second semiconductor layer 3 on which the LDD layer is formed by a method such as CVD, and the insulating layer is etched back using anisotropic etching such as RIE, whereby the gate electrode 12b. Sidewalls 13b are formed on the side walls. Then, by using the gate electrode 12b and the sidewall 13b as a mask, impurities such as As, P, and B are ion-implanted into the second semiconductor layer 3, thereby introducing high-concentration impurities respectively disposed on the side of the sidewall 13b. A source / drain layer 14 b composed of layers is formed on the second semiconductor layer 3.

  In the above embodiment, each step of forming a transistor in the bulk region R1 and each step of forming the SOI formation region R2 have been described separately. However, the present invention is not limited to this, and the steps are appropriately performed in the same manner. It may be simplified. Since the required characteristics are often different between the transistor in the bulk region R1 and the transistor in the SOI formation region R2, for example, the gate insulating films 11a and 11b are preferably formed in separate steps, but the gate electrode 12a The gate electrode 12b and the side walls 13a and 13b are preferably formed in the same process. The source / drain layers 14a14b may also be formed in the same process depending on required characteristics.

  Thus, it is possible to form the SOI structure and the bulk structure on the same semiconductor substrate 1 without using the SOI substrate, and to bury the buried insulating layer 9 in the SOI formation region R2, the SOI formation region R2 Even when the first semiconductor layer 2 is removed, the first semiconductor layer 2 can be left as it is in the bulk region R1. Therefore, the flatness between the SOI structure and the bulk structure can be ensured without polishing the surface of the second semiconductor layer 3, and even when the SOI structure and the bulk structure are formed on the same semiconductor substrate 1. While minimizing the SOI structure and the bulk structure can be realized while suppressing damage to the second semiconductor layer 3, an increase in cost can be suppressed.

The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention.

Explanation of symbols

  R1 bulk region, R2 SOI formation region, 1 semiconductor substrate, 2 first semiconductor layer, 3rd semiconductor layer, 4 base oxide film, 5 antioxidant film, 6 selective oxide film, 7 groove, 8 cavity, 9 buried insulation Layer, 11a, 11b gate insulating film, 12a, 12b gate electrode, 13a, 13b sidewall, 14a, 14b source / drain layer, R resist pattern, Ra opening

Claims (2)

Forming a first semiconductor layer on the first region and the second region of the semiconductor substrate;
The second semiconductor layer, a second step of forming on the first on the first semiconductor layer over the region and the first semiconductor layer over the second region,
As before Symbol said first semiconductor layer on the first region and surrounding the second semiconductor layer on said first region, a third step of forming a support to reach the semiconductor substrate,
A fourth step of etching a part of the support in contact with the second semiconductor layer surrounded by the support to form an opening exposing a part of the first semiconductor layer;
A fifth step of selectively etching the first semiconductor layer in a region surrounded by the support through the opening to form a cavity;
A sixth step of forming an insulating layer in the cavity and the opening;
A seventh step of forming a transistor in the second semiconductor layer surrounded by the support;
A method for manufacturing a semiconductor device, comprising: The third step includes
A step of eighth forming the first anti-oxidation film on said second semiconductor layer on a region,
A ninth step of forming the support by thermally oxidizing the first semiconductor layer and the second semiconductor layer using the antioxidant film as a mask;
The method of manufacturing a semiconductor device according to claim 1, comprising a.

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