JP2004221530A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a high-performance semiconductor element whose strain Si channel is formed into a thin film and which can prevent Ge from being diffused from its base and sufficient strain is applied to the Si channel. <P>SOLUTION: The MOS semiconductor device has a strain relief SiGe layer 12 formed on an Si substrate 10 across an insulating layer 11, a strain Si layer 13 formed on the SiGe layer 12, a gate electrode 15 selectively formed on the strain Si layer 13 across a gate insulating film 14, and source to drain areas 16 and 17 formed in the strain Si layer 13 across the gate electrode 15. The strain Si layer 13 is machined in stripes orthogonally to a gate direction (gate width direction) and the SiGe layer 12 below the stripes are etched away. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a technology for realizing a high-performance semiconductor element by applying a strain to a layer in which a semiconductor channel is formed, and particularly to a semiconductor device using a strained Si layer.

  The performance of Si-LSI semiconductor devices, especially MOSFETs, has been improving year by year with advances in LSI. However, in recent years, it has been pointed out that the limit of the lithography technology from the viewpoint of the process technology, and saturation of the mobility from the viewpoint of the device physics, and the difficulty in improving the performance is increasing.

  As a method for improving electron mobility, which is one of the indexes for improving the performance of Si-MOSFETs, a technique of applying a strain to an active layer for element formation has attracted attention. When strain is applied to the active layer, the band structure changes, and scattering of carriers in the channel is suppressed, so that an improvement in mobility can be expected. Specifically, a mixed crystal layer made of a material having a larger lattice constant than Si, for example, a strain-relaxed SiGe mixed crystal layer having a Ge concentration of 20% (hereinafter, simply referred to as a SiGe layer) is formed on a Si substrate. When a Si layer is formed on the layer, a strained Si layer to which strain is applied due to a difference in lattice constant is formed. It has been reported that when such a strained Si layer is used for a channel of a semiconductor device, a significant improvement in electron mobility can be achieved, which is about 1.76 times that when a non-strained Si channel is used (for example, Non-Patent Document 1). Reference 1).

  The present inventors have realized a device structure by forming a strained Si layer on a strain-relaxed SiGe layer on a buried oxide layer in order to form the above-described strained Si channel on an SOI structure (for example, see Non-Patent Document) 2). In the transistor having this structure, suppression of a short channel effect (Short Channel Effect: SCE) can be expected, and a high-performance element can be realized.

  However, further miniaturization is expected to cause a related mobility drop around the channel. For example, the distance between the source and the drain becomes narrower with miniaturization, and the total thickness of the strained Si layer and the SiGe layer thereunder must be further reduced. In the future, for example, when fabricating a device with a 35 nm node, the thickness of the strained Si channel is empirically reduced to 1/3 to 1/4 of the gate length, that is, about several nm. Here, in order to realize the above-mentioned strained Si layer, a SiGe layer is usually indispensable as a stressor layer for applying strain, and the channel film thickness is increased by the thickness of the SiGe layer. For this reason, it is difficult to cope with the thinning of the strained Si channel in future miniaturization.

  In addition, when the strained Si channel is in contact with a semiconductor material different from Si, for example, when the strained Si channel is in contact with the underlying SiGe layer, Ge may be diffused from the SiGe layer to the strained Si layer. As a result, a change in strain, a change in carrier transport, an increase in interface state, and the like may occur during a device manufacturing process or during device operation, and there is a concern that device characteristics may be degraded.

On the other hand, in the conventional planar type MOS structure, the driving current: Ion is remarkably reduced due to the reduction in the power supply voltage accompanying the integration. This becomes more remarkable with the pursuit of higher speed and higher integration, and there is a concern that it may hinder future circuit design.
J. Welser, JLHoyl, S. Tagkagi, and JFGibbons, IEDM 94-373 T. Mizuno et al., 11-3, 2002 Symposia on VLSI Tech.

  As described above, conventionally, in a semiconductor device using a strained Si channel, it is difficult to reduce the thickness of the Si channel, which is a factor that hinders further miniaturization in the future. In addition, the diffusion of Ge from the underlying layer of the Si channel causes a change in distortion, a change in carrier transport, an increase in interface state, and the like, which causes a problem of deteriorating device characteristics.

  The present invention has been made in consideration of the above circumstances, and has as its object to realize a high-performance semiconductor device while applying sufficient strain to a Si channel, and to additionally provide a strained Si channel. It is an object of the present invention to provide a semiconductor device which can prevent Ge from diffusing from a base and can cope with further miniaturization in the future.

  In order to solve the above problems, the present invention employs the following configuration.

  That is, the present invention provides a semiconductor device using a strained Si channel, which has a strain-relaxed SiGe layer at least on the surface, and a portion of the SiGe layer which is removed in an island shape, and which is formed on the SiGe layer, And a strained Si layer formed so as to partially cross the removed portion of the SiGe layer; a gate electrode formed on a part of the crossed portion of the strained Si layer via a gate insulating film; And a source / drain region formed in the strained Si layer corresponding to the position of the gate electrode.

  According to the present invention, in a semiconductor device using a strained Si channel, a strain-relaxed SiGe layer partially removed in an island shape, and a portion formed on the SiGe layer and partially removed from the SiGe layer A strained Si layer formed so as to traverse the substrate, a plurality of pairs of stacked substrates, and a gate electrode formed on a part of the crossed portion of each strained Si layer of the substrate via a gate insulating film. And a source / drain region formed in each strained Si layer of the substrate corresponding to the position of the gate electrode.

  Here, preferred embodiments of the present invention include the following.

  (1) A substrate having a strain-relaxed SiGe layer on the surface is obtained by forming a strain-relaxed SiGe layer on a Si substrate via an insulating layer.

  (2) A substrate in which several sets of a strain relaxation SiGe layer and a strained Si layer are stacked is formed on a Si substrate via an insulating layer.

  (3) The gate electrodes are provided at two places on the front side and the back side of a part of the strained Si layer.

  (4) The gate electrode is provided so as to surround a part of the strained Si layer from above, below, left and right.

  (5) The length of the removed portion of the strain-relaxed SiGe layer is 1 μm or less in the channel length direction of the strained Si layer.

  (6) The strained Si layer is formed by a crosslinked structure sandwiched between source / drain regions, and retains the strain by the crosslinked structure.

  (7) Part or all of the strained Si layer is in contact with only the gate insulating material.

  (8) The thickness of the strained Si layer is 200 nm or less, preferably 60 nm or less.

  (9) The gate electrode material in contact with the gate insulating material in contact with the strained Si layer is divided into a plurality of parts, and an arbitrary potential voltage can be applied to each of them.

  (10) The strained Si layer has a Ge concentration x of the underlying SiGe layer in a range of x <30%, typically in a range of 30 ≦ x <50%, and preferably in a range of 50 ≦ x ≦ 70%. There is.

  (11) The strained Si layer differs in the range of | Δd | <± 3% compared to the lattice constant of the crystal constituting the layer, and typically in the range of | Δd | <± 2.5%, preferably in the range of | Δd | The layers must be different within the range of | Δd | <± 2%.

  (12) The strained Si layer is formed by epitaxial growth.

  (13) The strained Si layer is used as a channel layer of an FET device having a MOS structure, as an n-MOSFET or p-MOSFET of a single transistor, or as an n-MOSFET or p-MOSFET in a logic device having a C-MOSFET structure as a minimum constituent unit. -Applicable to either or both MOSFETs.

  According to the present invention, the thickness of the strained Si channel can be further reduced by selectively removing the strain-relaxed SiGe layer immediately below the strained Si layer serving as the channel of the MOSFET. Can be prevented beforehand. Therefore, a high-performance semiconductor device can be realized while applying sufficient strain to the Si channel, and it is possible to sufficiently cope with further miniaturization in the future. In addition, since the MOS structure can be formed at a time by crystal growth, not only cost reduction but also significant simplification of the manufacturing process and high performance can be achieved at the same time.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

(1st Embodiment)
FIG. 1 is a sectional view showing an element structure of a MOSFET according to the first embodiment of the present invention.

  An insulating layer (Buried oxide layer: Box layer) 11 is formed on a Si substrate 10, and a strain-relaxed SiGe layer 12 is laminated thereon. At this time, the Ge composition on the surface side of the SiGe layer 12 is typically 3% or more and less than 80%, and preferably 20% or more and less than 50%. The SiGe thin film is usually formed by a CVD (Chemical Vapor Deposition) or MBE (Molecular Beam Epitaxy) process. When the SiGe layer 12 is formed by CVD, a raw material gas of Si and a raw material gas of Ge are introduced on the Si substrate 10 heated to, for example, 550 ° C., and the SiGe layer 12 having a thickness of, for example, 30 nm is formed on the insulating layer 11. Deposited on

  The SiGe layer 12 is required to relieve the strain due to the lattice constant difference from the underlying layer by introducing dislocations into the layer, and to release the strain at least on the surface side of the crystal so that the strain becomes SiGe. . Therefore, the lattice constant of the SiGe layer 12 may be changed in the direction perpendicular to the substrate by changing the Ge concentration in the direction of crystal growth perpendicular to the substrate surface.

  Further, the SiGe layer 12 whose strain has been alleviated by a bonding or concentration method (T. Tezuka et al., IEDM Tech. Dig., 946 (2001)) is connected to the Si substrate via an insulating layer 11 such as an oxide film. 10 may be formed. As a result, the SiGe layer 12 can have a function as a stressor for applying a strain to a strained Si layer (strained Si channel) described later. Here, in the bonding method, for example, the substrate on which the strain-relaxed SiGe layer 12 has been formed is bonded directly or via an oxide film to the surface of the Si substrate 10, and then the support substrate on which the SiGe layer 12 has been formed is peeled off. Thus, there is a method in which only the relaxed SiGe layer 12 is left.

On the SiGe layer 12, a strained Si layer 13 serving as a channel of the MOSFET is formed to a thickness of, for example, 8 nm, and a gate electrode 15 is formed thereon via a gate insulating film. The gate insulating film 14 is usually formed by thermal oxidation, but a CVD oxide film or a TEOS film may be formed instead. Radical oxidation that can be formed at a lower temperature, laser ablation, and the like can be applied to the oxidation. Here, the gate insulating film 14 is not limited to SiO ₂ , but is recently focused on HfO ₂ , ZrO ₂ , Al ₂ O ₃ , SiON, La ₂ O ₃ , or Re, Ru, Sr, Th, Tl, N , Na, or Nb, or a high-k material having a composition of a combination thereof.

Further, for example, a cerium oxide film (CeO ₂ ) film may be formed by using a molecular beam epitaxy method (MBE method). In this case, any insulating film epitaxially grown on the strained Si layer 13 may be used, and a rare earth oxide represented by a cerium oxide film such as Ce or Pr is particularly suitable.

  The gate electrode 15 is made of, for example, polycrystalline silicon, is deposited by CVD or the like, and is formed by patterning into a desired pattern. Then, the source region 16 and the drain region 17 are formed in the strained Si layer 13 by ion implantation using the gate electrode 15 as a mask.

  On the strained Si layer 13 on which the source / drain regions 16 and 17 are formed and on the gate electrode 15, an interlayer insulating film 18 is formed. Contact holes for making contact with the gate electrode 15 and the source / drain regions 16 and 17 are formed in the interlayer insulating film 18, and wirings 19 (19a, 19b and 19c) are formed to fill these contact holes. .

  The basic configuration up to this point is the same as that of Non-Patent Document 2 described above, but in addition to this, in the present embodiment, the SiGe layer 12 below the strained Si layer 13 is removed, and the channel of the strained Si layer 13 is removed. The lower part of the part is a cavity 12 '. That is, the strained Si layer 13 is processed in the form of a stripe along the gate length direction, and the SiGe layer 12 is removed therefrom. The gate insulating film 14 is formed on the exposed surface where the SiGe layer 12 is removed.

  The present embodiment is realized by introducing a process for removing a stressor immediately below a strained Si channel. Specifically, in the structure of FIG. 1, the process utilizes a difference in etching rate between the strained Si layer 13 and the strain-relaxed SiGe layer 12. The present inventors have found that the selectivity by CDE (Chemical Dry Etching) is approximately 2: 1 between the strain-relaxed SiGe layer having a Ge concentration of about 28% and the strained Si layer directly formed thereon. did. Based on this idea, after forming the strained Si layer 13, the CVD insulating film formed on the strained Si layer 13 is patterned, an opening is provided around the channel region, and selective etching is performed by CDE. It has been found that the relaxed SiGe layer 12 immediately below the Si layer 13 can be selectively removed.

  As a result, for example, as shown in FIG. 1, a cavity 12 ′ can be formed above the insulating layer 11 below the strained Si channel. Furthermore, the strained Si layer 13 immediately after CDE can be held for the first time while maintaining the strain while being supported by the relaxed SiGe regions at both ends which will later become source / drain regions.

  FIG. 2 is a diagram showing a mask pattern made of a CVD insulating film used at this time. In the figure, reference numeral 21 shown by a solid line denotes an opening of the CVD insulating film, which is provided in a stripe shape on both sides of the channel region. Reference numeral 22 shown by a broken line denotes a boundary of the removed SiGe layer 12, and the inside of the reference numeral 22 is a region where the SiGe layer 12 is removed. The selective epitaxial depends on the CDE conditions, the Si / SiGe film thickness, the Ge composition, and the like, and can be increased to 10: 1 or more.

  FIG. 3 is a perspective view showing a pattern of a strained Si channel, and this figure includes a gate electrode portion. The strained Si layer 13 is processed into a stripe shape in a direction perpendicular to the gate stripe direction (gate width direction), and the lower portion of the strain-relaxed SiGe layer 12 is removed from the stripe portion (strained Si channel) of the strained Si layer 13. . That is, both ends of the strained Si channel are supported by the SiGe layer 12.

  If this process is used, the strained Si channel can achieve a desired thickness of 10 nm or less without contacting the underlying stressor while the strain is applied, so that the Ge from the underlying strain-relaxed SiGe layer 12 can be realized. Achieve desired channel thinning while eliminating channel deterioration factors such as diffusion of defects, propagation of defects, thickening of the channel layer, or reduction of the interface state at the interface between the insulating film and the strained channel layer due to the presence of Ge. It is possible. If the area of the SiGe layer 12 below the strained Si layer 13 to be removed is too large, the strain of the strained Si channel becomes small. According to the experiments of the present inventors, the strain of the Si channel could be sufficiently maintained within 1 μm in the gate length direction.

  Further, as will be described in detail in an embodiment which will be described later, by surrounding the periphery of the strained Si channel with a gate, it is possible to ideally suppress the SCE effect and the like. Therefore, the electric field of the channel is three-dimensionally reduced. The ultimate channel can be formed in that a desired thin film channel can be obtained while controlling. In addition, as shown in the figure, since the FETs can be individually formed on the insulating layer 11, element isolation is sufficiently achieved, and crosstalk is unlikely to occur. In addition, the removal of the strain-relaxed SiGe layer 12 immediately below the strained Si layer 13 is performed as far as possible in order to avoid the diffusion of Ge and the propagation of defects from the SiGe layer 12 that may occur due to a thermal process in the transistor formation process. Should be done early.

  Note that the etching of the SiGe layer 12 can be performed by solution chemical etching. The oxide film as the insulating layer 11 can be formed by a commonly used method such as thermal oxidation of a dry oxide film and a wet oxide film, radical oxidation, deposition (CVD), and wet oxidation by a solution treatment. Therefore, the Si substrate 10 is merely a supporting substrate, and its role is not impaired as long as the Si substrate 10 is made of a material that can withstand an element manufacturing process such as heat history or chemical treatment.

  As described above, according to the present embodiment, improvement in mobility can be expected because the strained Si layer 13 is used for the channel of the MOSFET, and the SiGe layer 12 immediately below the strained Si layer 13 is selectively removed. Accordingly, the film thickness of the strained Si channel can be further reduced, and the diffusion of Ge into the strained Si channel can be prevented. Therefore, a high-performance semiconductor device can be realized while applying sufficient strain to the Si channel.

  That is, by forming the strained Si channel into a cross-linked structure, problems such as SCE effect, stray capacitance, propagation of defects caused by the underlying stressor layer, increase in interface state, and the like, which have been problems in miniaturization of the device, are solved. The speed can be increased by further reducing the thickness of the channel. Therefore, a high-performance, high-reliability, low-power-consumption MOSFET device can be realized.

  Further, as an advantage in the element formation process, it is possible to form the gate insulating film 14 and the gate electrode 15 in contact with the strained Si channel continuously and in some cases at a low temperature. In addition, since the above structure is formed on a so-called SOI structure, it is effective in reducing power consumption. Therefore, element formation on a substrate having a low melting point, such as glass, which could not be produced conventionally, element formation with a so-called damascene structure can be realized, and a high-quality and high-performance semiconductor element can be manufactured at a low cost by reducing the number of processes. And the power consumption of the manufactured device can be reduced. Further, by using a crystal insulating layer having a lattice constant different from that of the channel layer for the gate insulating film, the dielectric constant of the gate insulating film can be increased.

(Second embodiment)
FIG. 4 is a sectional view showing an element structure of a MOSFET according to the second embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

This embodiment is an example in which the gate electrode 15 of FIG. 1 is arranged so as to surround the strained Si channel 360 degrees vertically, horizontally, and horizontally. In this case, the gate electrode 15 is formed by forming a compound such as silane (SiH ₄ ), disilane (Si ₂ H ₆ ), dicyclosilane (SiH ₂ Cl ₂ ), or silane tetrachloride (SiCl ₄ ) on the gate insulating film 14 serving as a base. It can be formed at a low temperature of typically 500 ° C. to 700 ° C. in a temperature range of about 400 ° C. to 1000 ° C. by using a growth method using a CVD raw material such as a gas or an MBE method. During the crystal growth, impurities can be added simultaneously, and B and Sb are added for forming a p-type gate electrode, and As and P are added for forming an n-type gate electrode.

Further, for example, phosphorus is implanted into the gate electrode 15 formed beforehand by ion implantation at 4 × 10 ¹⁵ cm ⁻² , and subsequently at a temperature of about 500 ° C. to 1100 ° C., typically about 950 ° C. for about 1 minute or less. Can also be formed by performing activation annealing. However, since the annealing process is performed at a high temperature, strain relaxation of the strained Si layer 13 and generation of crystal defects may occur, which may degrade device characteristics. In that respect, the simultaneous process of forming the low-temperature gate electrode and the low-temperature activation by the vapor phase growth method including the above-described example is effective in maintaining the device characteristics and reducing the process cost by reducing the number of steps.

  In order to form the gate electrode 15 entirely around the strained Si channel, for example, the following may be performed. When the SiGe layer 12 is etched, by setting the distance between the two openings 21 of the mask shown in FIG. 2 to about the gate width, a cavity about the gate width is formed below the strained Si layer 13. can do. Thereafter, by growing polycrystalline silicon by CVD, a polycrystalline Si layer can be embedded in the cavity and a polycrystalline Si layer can be formed on the strained Si layer 13. Then, the upper polycrystalline Si layer other than the cavity may be processed into a gate pattern.

  As described above, according to the present embodiment, the same effect as that of the first embodiment can be obtained, and by sandwiching the whole around the strained Si channel with the gate electrode 15, the source-drain gap can be obtained. By controlling the electric field distribution, the SCE effect can be suppressed to the maximum. As a result, further improvement in device characteristics due to an increase in mobility can be expected.

(Third embodiment)
FIG. 5 is a sectional view showing an element structure of a MOSFET according to the third embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  In the present embodiment, the gate electrode formed so as to surround the strained Si channel in the structure of FIG. 4 is formed in two upper and lower layers. That is, the upper gate electrode 15 is formed above the strained Si layer 13 via the gate insulating film 14, and the lower gate electrode 55 is formed below the strained Si layer via the gate insulating film 14. . The method of manufacturing the gate electrodes 15 and 55 is substantially the same as in the second embodiment.

  With such a configuration, wiring can be separately drawn out from the upper and lower two layers of gate electrodes 15 and 55, and a voltage can be applied independently. As a result, the distribution of the inversion layer of the strained Si channel can be more precisely controlled, so that higher-performance FET characteristics can be realized.

  In the present embodiment, the case where independent gate electrodes are formed on the upper and lower sides is shown. However, for example, by separately controlling the side surfaces, the formation process becomes complicated, but more ideal channel layer control becomes possible. Become.

(Fourth embodiment)
FIG. 6 is a sectional view showing an element structure of a MOSFET according to the fourth embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  In the present embodiment, in the structure of FIG. 5, the region from which the strain-relaxed SiGe layer 12 is removed is made wider than the width of the upper gate electrode 15 similarly to FIG. 1, and the width of the lower gate electrode 65 (the gate as a MOSFET). Length) is wider than that of the upper gate electrode 15.

  With such a configuration, it is possible to obtain the same effect as that of the third embodiment, as well as to secure the space for, for example, drawing out the electrodes, thereby simplifying the gate processing process and reducing the cost. It is possible to form upper and lower electrodes on the substrate.

(Fifth embodiment)
FIG. 7 is a sectional view showing an element structure of a MOSFET according to the fifth embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  Although the basic configuration is the same as that of FIG. 1, in this embodiment, silicide films 66 and 67 are provided in the source / drain regions 16 and 17. That is, a silicide film 66 is formed on the upper surface of the source region 16, and a silicide film 67 is formed on the upper surface of the drain region 17.

  Although thinning the channel is important in an actual structure, thinning makes it difficult to form a source / drain junction. Therefore, the junction resistance increases as the channel becomes thinner, and the transistor characteristics deteriorate. Therefore, in this embodiment, the silicide films 66 and 67 are formed on the upper surfaces of the source / drain regions 16 and 17. With such a configuration, higher performance device characteristics can be obtained by a combination of a thin channel and a low resistance junction.

  Although not shown in the figure, instead of forming the silicide films 66 and 67, an elevated source / drain formation technique for realizing a low-resistance layer on the source / drain regions 16 and 17 by epitaxial growth or the like is used. However, it is effective because the resistance can be improved.

(Sixth embodiment)
FIG. 8 is a sectional view showing an element structure of a MOSFET according to the sixth embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  In the present embodiment, the wiring for connecting to the source / drain and the gate electrode in the configuration of FIG. 4 is improved. That is, the wiring 19 (19a, 19b, 19c) is formed outside the electrode or the cavity.

  With such a configuration, an increase in parasitic resistance and the like is inevitable because the distance between the source and the gate and between the drain and the gate is widened. However, the actual device creation process is much easier, and the device can be manufactured at a lower cost. It can be manufactured and provided.

(Seventh embodiment)
FIG. 9 is a sectional view showing an element structure of a MOSFET according to the seventh embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  In this embodiment, a plurality of sets (for example, three sets) of the strain relaxation SiGe layer and the strained Si layer in the first embodiment are stacked.

  An insulating layer 11 is formed on a Si substrate 10, and three pairs (a to c) of a strain relaxation SiGe layer 12 and a strained Si layer 13 having the same configuration as in the first embodiment are laminated thereon. I have. A gate electrode 15 is formed on the uppermost strained Si layer 13c via a gate insulating film 14. The conditions such as the manufacturing method, material, and thickness of the gate insulating film 14 may be the same as those in the first embodiment. The gate electrode 15 is made of, for example, polycrystalline silicon, is deposited by CVD or the like, and is formed by patterning into a desired pattern. With respect to the uppermost strained Si layer 13c, the source region 16 and the drain region 17 are formed in the strained Si layer 13c by ion implantation using the gate electrode 15 as a mask.

  An interlayer insulating film 18 is formed on the uppermost strained Si layer 13c on which the source / drain regions 16 and 17 are formed and on the gate electrode 15. Contact holes for making contact with the gate electrode 15 and the source / drain regions 16 and 17 are formed in the interlayer insulating film 18, and wirings 19 (19a, 19b and 19c) are formed to fill these contact holes. .

  As in the first embodiment, the SiGe layer 12 has a cavity 12 ′ below the channel portion of the strained Si layer 13. That is, the strained Si layer 13 is processed in the form of a stripe along the gate length direction, and the SiGe layer 12 is removed therefrom. Then, a gate insulating film 14 is formed on the exposed surface where the SiGe layer 12 is removed.

  Therefore, the gate insulating film 14 and the gate electrode 15 are formed so as to surround not only the uppermost strained Si layer 13c but also the lower strained Si layers 13a and 13b. 15 are formed in this order. FIG. 9 shows a structure in which each gate electrode material fills a hollow portion, but there may be a space without completely filling the hollow portion.

  The ion implantation method using the gate electrode 15 as a mask is not suitable for the strained Si layers 13a and 13b other than the uppermost strained Si layer 13c. However, it is possible to perform (oblique) ion implantation using the side wall after the stripe processing. Thereafter, source / drain regions can be formed by diffusion by heat treatment.

Also, the formation of the SiGe layer can include a high concentration of impurities such as B and Sb when forming a p-type electrode, and high concentrations of As and P when forming an n-type electrode. In this case, the region where the gate insulating film is to be formed has the SiGe layer removed in advance, and a diffusion heat treatment for forming the source / drain regions can be performed. On the other hand, in the case of this method, the lattice constant of the SiGe layer changes depending on the concentration of the impurity used for adding the impurity. The impurity concentration for suppressing this change may be 10 ²¹ cm ^-3 , typically 10 ²⁰ cm ^-3 or less, preferably 10 ¹⁹ cm ^-3 or less.

  The present embodiment is realized by introducing a process for removing a stressor immediately below a strained Si channel. Specifically, after forming the uppermost strained Si layer 13c, the CVD insulating film formed on the strained Si layer 13c is patterned to provide an opening around the channel region, and is selectively etched by CDE. Thus, the relaxed SiGe layer 12 immediately below the strained Si layer 13 can be selectively removed. Further, in order to surely etch down to the lowermost relaxed SiGe layer 12a, the relaxed SiGe layer 12 under the strained Si layer 13 is etched by RIE using the mask shown in FIG. Partial removal may be performed.

  As a result, a cavity 12 'can be formed below the strained Si channel and above the insulating layer 11. Furthermore, the strained Si layer 13 immediately after CDE can be held for the first time while maintaining the strain while being supported by the relaxed SiGe regions at both ends which will later become source / drain regions.

  As described above, according to the present embodiment, not only the high-performance, high-reliability, and low-power-consumption MOSFET device can be realized as in the first embodiment, but also the MOSFETs are stacked vertically. Therefore, a MOSFET with higher driving capability can be realized.

(Eighth embodiment)
FIG. 10 is a sectional view showing an element structure of a MOSFET according to the eighth embodiment of the present invention. The same parts as those in FIG. 9 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  This embodiment is an example in which, in the configuration of the seventh embodiment, as in the second embodiment, the gate electrode 15 is arranged so as to surround the strained Si channel 360 degrees vertically and horizontally. In the present embodiment, the case where the distance between the source and the drain of the uppermost gate insulating film 14 and the distance between the source and the drain of the lower gate insulating film 14 are the same is shown. In this case, the gate electrode 15 can be formed by the same method as in the second embodiment.

  As described above, according to the present embodiment, the same effect as that of the seventh embodiment can be obtained, and by sandwiching the whole around the strained Si channel with the gate electrode 15, the source-drain gap can be obtained. By controlling the electric field distribution, the SCE effect can be suppressed to the maximum. As a result, further improvement in device characteristics due to an increase in mobility can be expected.

(Ninth embodiment)
FIG. 11 is a sectional view showing an element structure of a MOSFET according to the ninth embodiment of the present invention. The same parts as those in FIG. 9 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  In the present embodiment, the gate electrode 15 is formed so as to surround the strained Si channel in the configuration of the seventh embodiment, as in the second embodiment. The method for manufacturing the gate electrode 15 is substantially the same as in the second embodiment. However, the distance between the source and the drain of the uppermost gate insulating film 14 and the gate electrode 15 is longer than those of the lower layer.

  Even with such a configuration, it is possible to realize a high-performance, high-reliability, and low-power-consumption MOSFET device, as in the first embodiment, and also to vertically stack MOSFETs. , A MOSFET having a higher driving capability can be realized.

(Modification)
Note that the present invention is not limited to the above embodiments. In the embodiment, the substrate in which the strain relaxation SiGe layer is formed on the Si substrate via the insulating layer is used as the base substrate. However, the base substrate is not necessarily limited to this configuration, and may be a bulk SiGe substrate, Instead, another semiconductor substrate may be used. In other words, it is sufficient that the undersubstrate has a strain-relaxed SiGe layer at least on the surface. Further, the thickness and the like of the strain relaxation SiGe layer and the strained Si layer can be appropriately changed according to specifications.

  Specifically, the strained Si layer serving as a channel reduces the parasitic capacitance in the SOI structure and the like, and has a width approximately equal to or smaller than the width of the depletion layer. it can. In addition, in order to avoid the relaxation of the strained Si layer due to the difference in lattice constant from the underlying SiGe layer at the time of forming the strained Si, it is necessary to reduce the thickness. Therefore, for example, when the Ge concentration of the underlying SiGe layer is 30%, the thickness of the strained Si layer is desirably 200 nm or less, and is required to be 60 nm or less in order to achieve high performance.

  In addition, the higher the Ge concentration of the SiGe layer serving as the base of the strained Si, the higher the element performance. This tendency is that the n-MOSFET is saturated at the Ge concentration of 30% to 40%, and the element performance of the p-MOSFET further increases to about 50%. Higher concentrations are not currently studied, but device performance up to about 60% can be expected. Therefore, it is appropriate to define the Ge concentration at an upper limit of 70%.

  In addition, various modifications can be made without departing from the scope of the present invention.

FIG. 2 is a cross-sectional view illustrating an element structure of the semiconductor device according to the first embodiment. FIG. 4 is a plan view showing a mask pattern when etching a SiGe layer. FIG. 4 is a perspective view showing a pattern of a strained Si channel. FIG. 6 is a cross-sectional view illustrating an element structure of a semiconductor device according to a second embodiment. FIG. 13 is a sectional view showing the element structure of the semiconductor device according to the third embodiment. FIG. 14 is a sectional view showing an element structure of a semiconductor device according to a fourth embodiment. FIG. 14 is a sectional view showing an element structure of a semiconductor device according to a fifth embodiment. FIG. 14 is a sectional view showing an element structure of a semiconductor device according to a sixth embodiment. FIG. 14 is a sectional view showing the element structure of a semiconductor device according to a seventh embodiment. FIG. 19 is a sectional view showing the element structure of the semiconductor device according to the eighth embodiment. FIG. 19 is a sectional view showing an element structure of a semiconductor device according to a ninth embodiment.

Explanation of reference numerals

10: Si substrate 11: Insulating layer (Box layer)
DESCRIPTION OF SYMBOLS 12 ... Strain relaxation SiGe layer 12 '... Cavity 13 ... Strained Si layer 14 ... Gate insulating film 15, 55, 65 ... Gate electrode 16 ... Source region 17 ... Drain region 18 ... Interlayer insulating film 19 ... Electrode 21 ... Opening 22 ... Etching boundary 66,67 ... Silicide film

Claims (7)

A substrate having a strain-relaxed SiGe layer at least on the surface, and a part of the SiGe layer removed in an island shape;
A strained Si layer formed on the SiGe layer and partially formed so as to cross a removed portion of the SiGe layer;
A gate electrode formed on a part of the transverse portion of the strained Si layer via a gate insulating film;
Source / drain regions formed in the strained Si layer corresponding to the positions of the gate electrodes;
A semiconductor device comprising: A plurality of strain-relaxed SiGe layers partially removed in an island shape and a strained Si layer formed on the SiGe layer and partially formed so as to cross the removed portion of the SiGe layer are provided. A pair of laminated substrates,
A gate electrode formed on a part of the transverse portion of each strained Si layer of the substrate via a gate insulating film, respectively;
Source / drain regions respectively formed in each strained Si layer of the substrate corresponding to the position of the gate electrode,
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein the substrate is formed by forming a strain relaxation SiGe layer on a Si substrate via an insulating layer.   3. The semiconductor device according to claim 2, wherein the substrate is formed on an Si substrate via an insulating layer.   3. The semiconductor device according to claim 1, wherein the gate electrode is provided at two positions on a front surface side and a back surface side of a part of the strained Si layer. 4.   The semiconductor device according to claim 1, wherein the gate electrode is provided so as to surround a part of the strained Si layer from above, below, left, and right.   3. The semiconductor device according to claim 1, wherein a length of the removed portion of the SiGe layer is 1 μm or less in a channel length direction of the strained Si layer.

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