JP3790238B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a technique for realizing a high-performance semiconductor element by applying strain to a layer in which a semiconductor channel is formed, and particularly to a semiconductor device using a strained Si layer.

  The performance of Si-LSI semiconductor elements, especially MOSFETs, is improving year by year with the progress of LSIs. However, the limitations of lithography technology from the viewpoint of process technology in recent years and the saturation of mobility from the viewpoint of device physics are pointed out, and the degree of difficulty in achieving high performance is increasing.

  As a method for improving electron mobility, which is one of the indexes for improving the performance of Si-MOSFETs, a technique for applying strain to an active layer for forming an element has attracted attention. When strain is applied to the active layer, the band structure is changed and scattering of carriers in the channel is suppressed, so that improvement in mobility can be expected. Specifically, a mixed crystal layer made of a material having a larger lattice constant than Si, for example, a strain relaxation SiGe mixed crystal layer (hereinafter simply referred to as a SiGe layer) having a Ge concentration of 20% is formed on the Si substrate. When a Si layer is formed on the layer, a strained Si layer to which strain is applied due to a difference in lattice constant is formed. It has been reported that when such a strained Si layer is used for a channel of a semiconductor device, a significant improvement in electron mobility can be achieved, which is about 1.76 times that when an unstrained Si channel is used (for example, non-patented). Reference 1).

  In order to form the above-described strained Si channel on the SOI structure, the present inventors have realized a device structure by a method of forming a strained Si layer on a strain relaxation SiGe layer on a buried oxide layer (for example, non-patent document). 2). The transistor having this structure can be expected to suppress a short channel effect (SCE), and a high-performance element can be realized.

  However, with further miniaturization, it is expected that the mobility reduction associated with the channel will occur. For example, with the miniaturization, the distance between the source and the drain becomes narrower, and the total film thickness of the strained Si layer and the SiGe layer below it has to be made thinner and thinner. In the future, when a device with a node of, for example, 35 nm is manufactured, the thickness of the strained Si channel is empirically reduced to 1/3 to 1/4 of the gate length, that is, about several nm. Here, in order to realize the above-described strained Si layer, a SiGe layer is usually essential as a stressor layer to which strain is applied, and the channel thickness is increased by the thickness of the SiGe layer. For this reason, it is difficult to cope with the thinning of the strained Si channel in the future miniaturization.

  Further, when the strained Si channel is in contact with a semiconductor material different from Si, for example, when the strained Si channel is in contact with the underlying SiGe layer, there is a possibility that Ge may diffuse from the SiGe layer to the strained Si layer. As a result, a change in strain, a change in carrier transport, or an increase in interface state may occur during the element manufacturing process or during device operation, and there is a concern about deterioration of element characteristics.

On the other hand, in the conventional planar type MOS structure, the drive current: Ion is significantly reduced due to the power supply voltage reduction accompanying the integration. This becomes more conspicuous as a result of the pursuit of higher speed and higher integration, and there is concern that it may hinder future circuit design.
J. Welser, JLHoyl, S. Tagkagi, and JFGibbons, IEDM 94-373 T. Mizuno et al., 11-3, 2002 Symposia on VLSI Tech.

  As described above, conventionally, in a semiconductor device using a strained Si channel, it is difficult to reduce the thickness of the Si channel, which hinders further miniaturization in the future. Further, the diffusion of Ge from the Si channel underlayer causes a change in strain, a change in carrier transport, an increase in interface state, and the like, resulting in a deterioration in device characteristics.

  The present invention has been made in view of the above circumstances, and the object of the present invention is to realize a high-performance semiconductor element while applying sufficient strain to the Si channel, and in addition to the strained Si channel. An object of the present invention is to provide a semiconductor device that can reduce the thickness of the film and prevent the diffusion of Ge from the base, and can cope with further miniaturization in the future.

  In order to solve the above problems, the present invention adopts the following configuration.

  That is, the present invention is a semiconductor device using a strained Si channel, formed on the SiGe layer, a substrate having a strain relaxation SiGe layer at least on the surface, a part of the SiGe layer removed in an island shape, And a strained Si layer formed so as to partially traverse the removed portion of the SiGe layer, and a gate electrode formed on a part of the transverse portion of the strained Si layer via a gate insulating film, The strained Si layer includes a source / drain region formed corresponding to the position of the gate electrode.

  According to the present invention, in a semiconductor device using a strained Si channel, a strain relaxation SiGe layer partially removed in an island shape, and a portion formed on the SiGe layer and partially removed from the SiGe layer A substrate in which a plurality of sets of strained Si layers formed so as to cross the substrate, a gate electrode formed on a part of the transverse portion of each strained Si layer of the substrate via a gate insulating film, respectively And a source / drain region formed corresponding to the position of the gate electrode in each strained Si layer of the substrate.

  Here, preferred embodiments of the present invention include the following.

  (1) A substrate having a strain-relaxed SiGe layer on the surface is a substrate in which a strain-relaxed SiGe layer is formed on an Si substrate via an insulating layer.

  (2) A substrate in which several pairs of strain-relieving SiGe layers and strained Si layers are laminated is formed on an Si substrate via an insulating layer.

  (3) The gate electrode is provided at two locations on the front and back sides of a part of the strained Si layer.

  (4) The gate electrode is provided so as to surround a part of the strained Si layer from the top, bottom, left and right.

  (5) The length of the removed portion of the strain relaxation SiGe layer is 1 μm or less with respect to the channel length direction of the strain Si layer.

  (6) The strained Si layer is formed by a crosslinked structure sandwiched between source / drain regions, and the strain is retained by the crosslinked structure.

  (7) A part or the entire surface of the strained Si layer is in contact with only the gate insulating material.

  (8) The strained Si layer has a thickness of 200 nm or less, preferably 60 nm or less.

  (9) The gate electrode material in contact with the gate insulating material in contact with the strained Si layer is divided into a plurality of parts, and an arbitrary potential voltage can be applied to each.

  (10) In the strained Si layer, the Ge concentration x of the underlying SiGe layer is in the range of x <30%, typically in the range of 30 ≦ x <50%, preferably in the range of 50 ≦ x ≦ 70%. There is.

  (11) The strained Si layer differs in the range of | Δd | <± 3% as compared to the lattice constant of the crystal constituting the layer, typically in the range of | Δd | <± 2.5%, preferably Different layers in the range of | Δd | <± 2%.

  (12) The strained Si layer is formed by epitaxial growth.

  (13) The strained Si layer is used as a channel layer of a MOS-structure FET element, as a single-transistor n-MOSFET, p-MOSFET, or in a logic element having a C-MOSFET structure as a minimum unit, n-MOSFET, p -Applies to either or both MOSFETs.

  According to the present invention, by selectively removing the strain relaxation SiGe layer immediately below the strained Si layer that becomes the channel of the MOSFET, the thickness of the strained Si channel can be further reduced, and the Ge to the strained Si channel can be reduced. Can be prevented in advance. Therefore, it is possible to realize a high-performance semiconductor element while applying sufficient strain to the Si channel, and it can sufficiently cope with further miniaturization in the future. Moreover, since the MOS structure can be formed at a time by crystal growth, not only the cost can be reduced but also the manufacturing process can be greatly simplified and the performance can be improved.

  The details of the present invention will be described below with reference to the illustrated embodiments.

(First embodiment)
FIG. 1 is a cross-sectional view showing the element structure of a MOSFET according to the first embodiment of the present invention.

  An insulating layer (Buried oxide layer: Box layer) 11 is formed on the Si substrate 10, and a strain relaxation SiGe layer 12 is laminated thereon. At this time, the Ge composition on the surface side of the SiGe layer 12 is typically 3% or more and less than 80%, and preferably 20% or more and less than 50%. The SiGe thin film is usually formed by a CVD (Chemical Vapor Deposition) or MBE (Molecular Beam Epitaxy) process. When the SiGe layer 12 is formed by CVD, a Si raw material gas and a Ge raw material gas are introduced onto the Si substrate 10 heated to, for example, 550 ° C., and the SiGe layer 12 having a thickness of, for example, 30 nm is formed on the insulating layer 11. To deposit.

  The SiGe layer 12 needs to release strain so as to be strain-relaxed SiGe at least on the surface side of the crystal by relaxing dislocation due to a difference in lattice constant from the underlayer by introducing dislocations into the layer. . Therefore, the SiGe layer 12 may change the lattice constant in the direction perpendicular to the substrate by changing the Ge concentration in the crystal growth direction perpendicular to the substrate surface.

  Further, the SiGe layer 12 in which the strain relaxation is realized by the bonding or concentration method (T. Tezuka et al., IEDM Tech. Dig., 946 (2001)) is applied to the Si substrate through the insulating layer 11 such as an oxide film. 10 may be formed. As a result, the SiGe layer 12 can have a function as a stressor that applies strain to a strained Si layer (strained Si channel) described later. Here, for example, in the bonding method, the substrate on which the SiGe layer 12 that has been subjected to strain relaxation in advance is bonded to the surface of the Si substrate 10 directly or via an oxide film, and then the support substrate on which the SiGe layer 12 is formed is peeled off. Thus, there is a method of leaving only the relaxed SiGe layer 12.

A strained Si layer 13 serving as a MOSFET channel is formed on the SiGe layer 12 to a thickness of, for example, 8 nm, and a gate electrode 15 is further formed on the SiGe layer 12 via a gate insulating film 14. Although the gate insulating film 14 is usually formed by thermal oxidation, a CVD oxide film or a TEOS film may be formed instead. For oxidation, radical oxidation that can be formed at a lower temperature, laser ablation, and the like can also be applied. Here, the gate insulating film 14 is not limited to SiO _2, and HfO ₂ , ZrO ₂ , Al ₂ O ₃ , SiON, La ₂ O ₃ , or Re, Ru, Sr, Th, Tl, N, which have recently attracted attention. , Na, and Nb, or a high-k material having a composition composed of a combination thereof.

Further, for example, a cerium oxide film (CeO ₂ ) film may be formed by using a molecular beam epitaxy method (MBE method). In this case, any insulating film that epitaxially grows on the strained Si layer 13 may be used, and rare earth oxides represented by cerium oxide films such as Ce and Pr are particularly suitable.

  The gate electrode 15 is made of, for example, polycrystalline silicon, deposited by CVD or the like, and formed by patterning into a desired pattern. A source region 16 and a drain region 17 are formed in the strained Si layer 13 by ion implantation using the gate electrode 15 as a mask.

  On the strained Si layer 13 and the gate electrode 15 where the source / drain regions 16 and 17 are formed, an interlayer insulating film 18 is formed. Contact holes for making contact with the gate electrode 15 and the source / drain regions 16, 17 are formed in the interlayer insulating film 18, and wirings 19 (19a, 19b, 19c) are formed so as to fill these contact holes. .

  The basic configuration so far is the same as that of Non-Patent Document 2 described above. In addition, in this embodiment, the SiGe layer 12 below the strained Si layer 13 is removed, and the channel of the strained Si layer 13 is removed. The lower part of the part is a cavity 12 '. That is, the strained Si layer 13 is processed in a stripe shape along the gate length direction, and the SiGe layer 12 is removed under the strained Si layer 13. The gate insulating film 14 is formed on the exposed surface after the SiGe layer 12 is removed.

  This embodiment is realized by introducing a process for removing a stressor directly under a strained Si channel. Specifically, in the structure of FIG. 1, this is a process using the difference in etching rate between the strained Si layer 13 and the strain relaxation SiGe layer 12. The present inventors have found that a selective ratio by CDE (Chemical Dry Etching) is approximately 2: 1 between a strain relaxation SiGe layer having a Ge concentration of about 28% and a strained Si layer directly formed thereon. did. Based on this idea, after forming the strained Si layer 13, the CVD insulating film formed on the strained Si layer 13 is patterned, an opening is provided around the channel region, and selective etching is performed by CDE. It has been found that the relaxed SiGe layer 12 directly under the Si layer 13 can be selectively removed.

  As a result, for example, as shown in FIG. 1, a cavity 12 'can be formed above the insulating layer 11 below the strained Si channel. Further, the strained Si layer 13 immediately after the CDE can be held for the first time while maintaining the strain while being supported by the relaxed SiGe regions at both ends which will later become the source / drain regions.

  FIG. 2 is a diagram showing a mask pattern made of a CVD insulating film used at this time. Reference numeral 21 indicated by a solid line in the figure denotes an opening of the CVD insulating film, which is provided in stripes on both sides of the channel region. Further, 22 indicated by a broken line is the boundary of the removed SiGe layer 12, and the inside of the 22 is a region where the SiGe layer 12 is removed. The selective epitaxial depends on the CDE conditions, the Si / SiGe film thickness, the Ge composition, etc., and can be increased to 10: 1 or more.

  FIG. 3 is a perspective view showing a pattern of a strained Si channel. In this figure, the gate electrode portion is shown. The strained Si layer 13 is processed into a stripe shape in a direction perpendicular to the gate stripe direction (gate width direction), and the lower strain-relieving SiGe layer 12 is removed from the stripe portion (strained Si channel) of the strained Si layer 13. . That is, both ends of the strained Si channel are supported by the SiGe layer 12.

  By using this process, the strained Si channel can realize a desired thickness of 10 nm or less without being in contact with the underlying stressor while being applied with strain, so that the Ge from the strain-relieving SiGe layer 12 of the underlying layer can be realized. Achieves desired channel thinning while eliminating channel degradation factors such as diffusion of defects, propagation of defects, thickening of channel layer, or reduction of interface state at insulating film / strained channel layer interface due to presence of Ge Is possible. If the region where the SiGe layer 12 below the strained Si layer 13 is removed is too large, strain of the strained Si channel is reduced. According to the experiments by the present inventors, the strain of the Si channel can be sufficiently maintained within 1 μm in the gate length direction.

  Further, as will be described in detail in an embodiment described later, since the SCE effect and the like can be ideally suppressed by surrounding the strained Si channel with a gate, the electric field of the channel is three-dimensionally controlled. The ultimate channel can be formed in that a desired thin film channel can be obtained while being controlled. In addition, as shown in the figure, since FETs can be individually formed on the insulating layer 11, element isolation is sufficiently performed, and occurrence of crosstalk or the like is difficult. Further, the removal of the strain-relaxed SiGe layer 12 immediately below the strained Si layer 13 is performed as far as possible in order to avoid the diffusion of Ge and the propagation of defects from the SiGe layer 12 that would be caused by a thermal process in the transistor formation process. Should be done early on.

  The SiGe layer 12 can be etched by solution chemical etching. The oxide film as the insulating layer 11 can be formed by a commonly used method such as thermal oxidation such as dry oxide film or wet oxide film, radical oxidation, deposition (CVD), or wet oxidation by solution treatment. Therefore, the Si substrate 10 is a support substrate to the last, and does not hinder its role as long as it is a material that can withstand an element manufacturing process such as thermal history and chemical treatment.

  As described above, according to the present embodiment, since the strained Si layer 13 is used for the channel of the MOSFET, an improvement in mobility can be expected, and the SiGe layer 12 immediately below the strained Si layer 13 can be selectively removed. Thus, the thickness of the strained Si channel can be further reduced, and the diffusion of Ge into the strained Si channel can be prevented in advance. Therefore, a high-performance semiconductor element can be realized while applying sufficient strain to the Si channel.

  In other words, by forming a strained Si channel into a cross-linked structure, problems such as SCE effect, stray capacitance, propagation of defects caused by the underlying stressor layer, and increase in interface state, which have been problems in miniaturization of the device, are solved. It is possible to solve this problem, and it is possible to increase the speed by further reducing the thickness of the channel. Therefore, a high performance, high reliability, and low power consumption MOSFET device can be realized.

  Further, as an advantage in the element formation process, the gate insulating film 14 and the gate electrode 15 that are in contact with the strained Si channel can be formed continuously at a low temperature in some cases. In addition, since the above structure is formed on a so-called SOI structure, it is effective in reducing power consumption. Therefore, it is possible to realize element formation on a substrate having a low melting point such as glass, which could not be manufactured conventionally, and so-called damascene structure, and to produce a high-quality and high-performance semiconductor element by reducing the number of processes. In addition, it is possible to reduce the power consumption of the manufactured element. In addition, by using a crystal insulating layer having a lattice constant different from that of the channel layer for the gate insulating film, the dielectric constant of the gate insulating film can be increased.

(Second Embodiment)
FIG. 4 is a sectional view showing an element structure of a MOSFET according to the second embodiment of the present invention. In addition, the same code | symbol is attached | subjected to FIG. 1 and an identical part, and the detailed description is abbreviate | omitted.

This embodiment is an example in which the gate electrode 15 of FIG. 1 is arranged so as to surround the strained Si channel 360 ° vertically and horizontally. In this case, the gate electrode 15 is formed by forming a compound such as silane (SiH ₄ ), disilane (Si ₂ H ₆ ), dichlorosilane (SiH ₂ Cl ₂ ), or silane tetrachloride (SiCl ₄ ) on the gate insulating film 14 as a base. Using a growth method using a CVD raw material such as a gas, an MBE method, or the like, it can be formed at a low temperature, typically 500 ° C. to 700 ° C., in a temperature range of about 400 ° C. to 1000 ° C. During this crystal growth, impurities can be added simultaneously, and B and Sb are added to form a p-type gate electrode, and As and P are added to form an n-type gate electrode.

Further, for example, phosphorus is implanted at 4 × 10 ¹⁵ cm ⁻² by ion implantation into the gate electrode 15 formed in advance, and subsequently at a temperature of about 500 ° C. to 1100 ° C., typically about 950 ° C. for about 1 minute or less. It can also be formed by performing activation annealing. However, since this annealing process is performed at a high temperature, strain relaxation of the strained Si layer 13 or generation of crystal defects may occur, which may deteriorate device characteristics. In that respect, the simultaneous process of low-temperature gate electrode formation and low-temperature activation by the vapor phase growth method including the above-described example is effective in achieving both device characteristics maintenance and process cost reduction by reducing the number of steps.

  In order to form the gate electrode 15 around the entire strained Si channel, for example, the following may be performed. When etching the SiGe layer 12, the distance between the two openings 21 of the mask shown in FIG. 2 is set to about the gate width, thereby forming a cavity about the gate width below the strained Si layer 13. can do. Thereafter, by growing polycrystalline silicon by CVD, a polycrystalline Si layer can be embedded in the cavity and a polycrystalline Si layer can also be formed on the strained Si layer 13. Then, the upper polycrystalline Si layer other than the cavity may be processed into a gate pattern.

  As described above, according to the present embodiment, the same effect as that of the first embodiment can be obtained, and the entire area around the strained Si channel can be sandwiched between the gate electrode 15 and the source-drain region can be obtained. The electric field distribution can be controlled and the SCE effect can be suppressed to the maximum. As a result, further improvement in device characteristics due to an increase in mobility can be expected.

(Third embodiment)
FIG. 5 is a sectional view showing the element structure of a MOSFET according to the third embodiment of the present invention. In addition, the same code | symbol is attached | subjected to FIG. 1 and an identical part, and the detailed description is abbreviate | omitted.

  In the present embodiment, gate electrodes formed so as to surround a strained Si channel in the structure of FIG. 4 are formed in two upper and lower layers. That is, the upper gate electrode 15 is formed above the strained Si layer 13 via the gate insulating film 14, and the lower gate electrode 55 is formed below the strained Si layer via the gate insulating film 14. . The manufacturing method of the gate electrodes 15 and 55 is substantially the same as that of the second embodiment.

  With such a configuration, the wiring can be drawn separately by the upper and lower gate electrodes 15 and 55, and a voltage can be applied independently. Thereby, since the inversion layer distribution of the strained Si channel can be controlled more precisely, higher performance FET characteristics can be realized.

  In this embodiment, the case where independent gate electrodes are formed on the upper and lower sides is shown. However, by controlling the side surfaces separately, for example, the formation process becomes complicated, but more ideal channel layer control is possible. Become.

(Fourth embodiment)
FIG. 6 is a sectional view showing an element structure of a MOSFET according to the fourth embodiment of the present invention. In addition, the same code | symbol is attached | subjected to FIG. 1 and an identical part, and the detailed description is abbreviate | omitted.

  In the present embodiment, the region from which the strain relaxation SiGe layer 12 is removed in the structure of FIG. 5 is made wider than the width of the upper gate electrode 15 as in FIG. The length) is wider than that of the upper gate electrode 15.

  With such a configuration, the same effects as those of the third embodiment can be obtained, and, for example, a space for drawing out the electrodes is secured, so that the gate processing process can be simplified and less expensive. It is possible to form upper and lower electrodes.

(Fifth embodiment)
FIG. 7 is a sectional view showing an element structure of a MOSFET according to the fifth embodiment of the present invention. In addition, the same code | symbol is attached | subjected to FIG. 1 and an identical part, and the detailed description is abbreviate | omitted.

  Although the basic configuration is the same as that of FIG. 1, silicide films 66 and 67 are provided in the source / drain regions 16 and 17 in this embodiment. That is, a silicide film 66 is formed on the upper surface of the source region 16, and a silicide film 67 is formed on the upper surface of the drain region 17.

  In an actual structure, thinning the channel is important, but thinning makes it difficult to form a source / drain junction. For this reason, the junction resistance increases as the channel becomes thinner, and the transistor characteristics deteriorate. Therefore, in this embodiment, silicide films 66 and 67 are formed on the upper surfaces of the source / drain regions 16 and 17. With such a configuration, higher performance device characteristics can be obtained by a combination of channel thinning and low resistance junction.

  Although not shown in the drawing, instead of forming the silicide films 66 and 67, an elevated source / drain formation technique that realizes a low resistance layer on the source / drain regions 16 and 17 by epitaxial growth or the like is used. However, it is effective because it can improve the resistance.

(Sixth embodiment)
FIG. 8 is a sectional view showing an element structure of a MOSFET according to the sixth embodiment of the present invention. In addition, the same code | symbol is attached | subjected to FIG. 1 and an identical part, and the detailed description is abbreviate | omitted.

  In the present embodiment, the wiring for connecting to the source / drain and gate electrodes is improved in the configuration of FIG. That is, the wiring 19 (19a, 19b, 19c) is formed outside the electrode or the cavity.

  With such a configuration, the increase in parasitic resistance is inevitable because the distance between the source and gate and between the drain and gate is increased, but the actual device creation process is much easier and the device can be manufactured at a lower cost. It becomes possible to manufacture and provide.

(Seventh embodiment)
FIG. 9 is a sectional view showing an element structure of a MOSFET according to the seventh embodiment of the present invention. In addition, the same code | symbol is attached | subjected to FIG. 1 and an identical part, and the detailed description is abbreviate | omitted.

  In the present embodiment, a plurality of (for example, three) sets of strain relaxation SiGe layers and strained Si layers in the first embodiment are stacked.

  An insulating layer 11 is formed on the Si substrate 10, and three pairs (ac) of the strain relaxation SiGe layer 12 and the strained Si layer 13 having the same configuration as that of the first embodiment are stacked thereon. Yes. A gate electrode 15 is formed on the uppermost strained Si layer 13 c with a gate insulating film 14 interposed therebetween. Conditions such as the manufacturing method, material, and thickness of the gate insulating film 14 may be the same as those in the first embodiment. The gate electrode 15 is made of, for example, polycrystalline silicon, deposited by CVD or the like, and formed by patterning into a desired pattern. With respect to the uppermost strained Si layer 13c, the source region 16 and the drain region 17 are formed in the strained Si layer 13c by ion implantation using the gate electrode 15 as a mask.

  An interlayer insulating film 18 is formed on the uppermost strained Si layer 13 c where the source / drain regions 16 and 17 are formed and on the gate electrode 15. Contact holes for making contact with the gate electrode 15 and the source / drain regions 16, 17 are formed in the interlayer insulating film 18, and wirings 19 (19a, 19b, 19c) are formed so as to fill these contact holes. .

  As in the first embodiment, the SiGe layer 12 has a cavity 12 ′ below the channel portion of the strained Si layer 13. That is, the strained Si layer 13 is processed in a stripe shape along the gate length direction, and the SiGe layer 12 is removed under the strained Si layer 13. A gate insulating film 14 is formed on the exposed surface after the SiGe layer 12 is removed.

  Therefore, the gate insulating film 14 and the gate electrode 15 surround not only the uppermost strained Si layer 13c but also the lower strained Si layers 13a and 13b so as to surround them. It is formed in the order of 15. Although FIG. 9 shows a structure in which each gate electrode material fills the cavity, there may be a space without being completely filled.

  The ion implantation method using the gate electrode 15 as a mask is not suitable for the strained Si layers 13a and 13b other than the uppermost strained Si layer 13c. However, it is possible to implant ions (obliquely) using the side wall after the stripe processing. Thereafter, source / drain regions can be formed by diffusion by heat treatment.

In forming the SiGe layer, B or Sb can be included at a high concentration when a p-type electrode is formed, and As and P can be included at a high concentration when the p-type electrode is formed. In this case, the SiGe layer is previously removed from the region where the gate insulating film is formed, and diffusion heat treatment for forming the source / drain regions can be performed. On the other hand, in the case of this method, the lattice constant of the SiGe layer changes depending on the concentration of impurities used for impurity addition. The impurity concentration for suppressing this change may be 10 ²¹ cm ⁻³ , typically 10 ²⁰ cm ⁻³ or less, and desirably 10 ¹⁹ cm ⁻³ or less.

  This embodiment is realized by introducing a process for removing a stressor directly under a strained Si channel. Specifically, after forming up to the uppermost strained Si layer 13c, the CVD insulating film formed on the strained Si layer 13c is patterned, an opening is provided around the channel region, and selective etching is performed by CDE. Thus, the relaxed SiGe layer 12 immediately below the strained Si layer 13 can be selectively removed. In order to surely etch up to the lowermost relaxed SiGe layer 12a, the relaxed SiGe layer 12 under the strained Si layer 13 is etched using RIE using the mask shown in FIG. A part may be removed.

  As a result, a cavity 12 'can be formed above the insulating layer 11 below the strained Si channel. Further, the strained Si layer 13 immediately after CDE can be held for the first time while being supported by the relaxed SiGe regions at both ends, which will later become source / drain regions, while maintaining the strain.

  As described above, according to this embodiment, it is possible to realize a high-performance, high-reliability, and low-power consumption MOSFET element as in the first embodiment, and the MOSFETs are stacked vertically. Therefore, a MOSFET with higher driving capability can be realized.

(Eighth embodiment)
FIG. 10 is a sectional view showing the element structure of a MOSFET according to the eighth embodiment of the present invention. In addition, the same code | symbol is attached | subjected to FIG. 9 and an identical part, and the detailed description is abbreviate | omitted.

  In the configuration of the seventh embodiment, the present embodiment is an example in which the gate electrode 15 is arranged so as to surround the strained Si channel 360 ° vertically and horizontally as in the second embodiment. In the present embodiment, a case is shown in which the distance between the source and drain of the uppermost gate insulating film 14 and the distance between the source and drain of the lower gate insulating film 14 have the same dimensions. In this case, the gate electrode 15 can be formed by the same method as in the second embodiment.

  As described above, according to the present embodiment, the same effects as those of the previous seventh embodiment can be obtained, and by sandwiching the entire periphery of the strained Si channel with the gate electrode 15, the distance between the source and the drain can be increased. The electric field distribution can be controlled and the SCE effect can be suppressed to the maximum. As a result, further improvement in device characteristics due to an increase in mobility can be expected.

(Ninth embodiment)
FIG. 11 is a sectional view showing an element structure of a MOSFET according to the ninth embodiment of the present invention. In addition, the same code | symbol is attached | subjected to FIG. 9 and an identical part, and the detailed description is abbreviate | omitted.

  In this embodiment, the gate electrode 15 is formed so as to surround the strained Si channel in the configuration of the seventh embodiment as in the second embodiment. The manufacturing method of the gate electrode 15 is substantially the same as in the second embodiment. However, the distance between the source and drain of the uppermost gate insulating film 14 and the gate electrode 15 is longer than that of the lower layer.

  Even with such a configuration, it is possible to realize a high-performance, high-reliability, low-power-consumption MOSFET device as in the first embodiment, and the MOSFETs are stacked vertically. Thus, a MOSFET with higher driving capability can be realized.

(Modification)
The present invention is not limited to the above-described embodiments. In the embodiment, a substrate in which a strain relaxation SiGe layer is formed on an Si substrate via an insulating layer is used as a base substrate. However, the base substrate is not necessarily limited to this configuration, and may be a SiGe bulk substrate or a Si substrate. Instead of this, another semiconductor substrate may be used. In other words, the base substrate may be any substrate having at least a strain relaxation SiGe layer on the surface. Further, the thickness of the strain relaxation SiGe layer and the strained Si layer can be appropriately changed according to the specifications.

  Specifically, the strained Si layer serving as the channel is expected to improve performance by reducing the parasitic capacitance in the SOI structure and reducing it to the same or smaller width than the depletion layer. it can. Further, in order to avoid the relaxation of the strained Si layer due to the difference in lattice constant from the underlying SiGe layer at the time of strained Si formation: mismatch, it is essential to reduce the thickness. Therefore, for example, when the Ge concentration of the underlying SiGe layer is 30%, the thickness of the strained Si layer is desirably 200 nm or less, and 60 nm or less is essential to achieve high performance.

  In addition, the SiGe layer serving as the base of strained Si has higher device performance as the Ge concentration is higher. This tendency is that the n-MOSFET is saturated at a Ge concentration of 30% to 40%, and the device performance is further increased to about 50% in the p-MOSFET. At higher concentrations, it has not been studied at present, but the device performance can be sufficiently expected up to about 60%. Therefore, it is appropriate to define the Ge concentration with an upper limit of 70%.

  In addition, various modifications can be made without departing from the scope of the present invention.

1 is a cross-sectional view showing an element structure of a semiconductor device according to a first embodiment. The top view which shows the mask pattern at the time of etching a SiGe layer. The perspective view which shows the pattern of a distortion Si channel. Sectional drawing which shows the element structure of the semiconductor device concerning 2nd Embodiment. Sectional drawing which shows the element structure of the semiconductor device concerning 3rd Embodiment. Sectional drawing which shows the element structure of the semiconductor device concerning 4th Embodiment. Sectional drawing which shows the element structure of the semiconductor device concerning 5th Embodiment. Sectional drawing which shows the element structure of the semiconductor device concerning 6th Embodiment. Sectional drawing which shows the element structure of the semiconductor device concerning 7th Embodiment. Sectional drawing which shows the element structure of the semiconductor device concerning 8th Embodiment. Sectional drawing which shows the element structure of the semiconductor device concerning 9th Embodiment.

Explanation of symbols

10 ... Si substrate 11 ... Insulating layer (Box layer)
DESCRIPTION OF SYMBOLS 12 ... Strain relaxation SiGe layer 12 '... Cavity part 13 ... Strain Si layer 14 ... Gate insulating film 15,55,65 ... Gate electrode 16 ... Source region 17 ... Drain region 18 ... Interlayer insulating film 19 ... Electrode 21 ... Opening 22 ... Etching boundary 66, 67 ... Silicide film

Claims (7)

A substrate having at least a strain-relieving SiGe layer on the surface, and a part of the SiGe layer removed in an island shape;
A strained Si layer formed on the SiGe layer and partially formed across the removed portion of the SiGe layer;
A gate electrode formed on a part of the transverse portion of the strained Si layer via a gate insulating film;
Source / drain regions formed in the strained Si layer corresponding to the positions of the gate electrodes;
A semiconductor device comprising: A plurality of strain-relieving SiGe layers partially removed in the form of islands and strained Si layers formed on the SiGe layer and partially formed so as to cross the removed portions of the SiGe layer A laminated substrate;
A gate electrode formed on a part of the transverse portion of each strained Si layer of the substrate via a gate insulating film,
Source / drain regions respectively formed corresponding to the positions of the gate electrodes in each strained Si layer of the substrate;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein the substrate is obtained by forming a strain relaxation SiGe layer on an Si substrate via an insulating layer. The substrate, via an insulating layer on a Si substrate, a semiconductor device according to claim 2, wherein said plurality of sets of strain relaxed SiGe layer and a strained Si layer is characterized in that laminated.   3. The semiconductor device according to claim 1, wherein the gate electrode is provided at two locations on a front surface side and a back surface side of a part of the strained Si layer.   The semiconductor device according to claim 1, wherein the gate electrode is provided so as to surround a part of the strained Si layer from above, below, left and right. 3. The semiconductor device according to claim 1 , wherein a length along the channel length direction of the strained Si layer of the removed portion of the SiGe layer is 1 μm or less.

Images